IS42S16100E-7TLI [ISSI]
512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM; 512K字×16位×2组16Mb的同步动态RAM
| 型号： | IS42S16100E-7TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM |
| 文件： | 总82页 (文件大小：1535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S16100E
IS45S16100E
512K Words x 16 Bits x 2 Banks
16Mb SYNCHRONOUS DYNAMIC RAM
SEPTEMBER 2009
FEATURES
•ꢀ Clock frequency: 200, 166, 143 MHz
DESCRIPTION
ISSI’sꢀ16MbꢀSynchronousꢀDRAMꢀIS42/4516100Eꢀisꢀ
organizedꢀasꢀaꢀ524,288-wordꢀxꢀ16-bitꢀxꢀ2-bankꢀforꢀ
improvedꢀperformance.ꢀTheꢀsynchronousꢀDRAMsꢀ
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
•ꢀ Twoꢀbanksꢀcanꢀbeꢀoperatedꢀsimultaneouslyꢀandꢀ
independently
•ꢀ DualꢀinternalꢀbankꢀcontrolledꢀbyꢀA11ꢀ(bankꢀselect)
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7ꢀ
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
DQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
•ꢀ Programmableꢀburstꢀsequence:ꢀ
2
Sequential/Interleave
3
4
•ꢀ 2048ꢀrefreshꢀcyclesꢀeveryꢀ32msꢀ(Com,ꢀInd,ꢀA1ꢀ
grade)ꢀorꢀ16msꢀ(A2ꢀgrade)
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
5
6
7
8
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀ
precharge command
•ꢀ ByteꢀcontrolledꢀbyꢀLDQMꢀandꢀUDQM
•ꢀ Packages:ꢀ400-milꢀ50-pinꢀTSOP-IIꢀandꢀ60-ballꢀ
TF-BGA
•ꢀ TemperatureꢀGrades:
Commercialꢀ(0oC to +70oC)
Industrialꢀ(-40oCꢀtoꢀ+85oC)
ꢀꢀꢀꢀAutomotiveꢀA1ꢀ(-40oCꢀtoꢀ+85oC)
ꢀꢀꢀꢀAutomotiveꢀA2ꢀ(-40oCꢀtoꢀ+105oC)
A7
A6
A5
A4
VDD
GND
PIN DESCRIPTIONS
CAS
Column Address Strobe Command
A0-A10 ꢀ
RowꢀAddressꢀInput
BankꢀSelectꢀAddress
Column Address Input
DataꢀDQ
WEꢀ
WriteꢀEnable
A11ꢀꢀ
ꢀ
LDQMꢀ LowerꢀBye,ꢀInput/OutputꢀMask
UDQMꢀ UpperꢀBye,ꢀInput/OutputꢀMask
A0-A7
DQ0ꢀtoꢀDQ15ꢀ
VDDꢀ
GNDꢀ
Power
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
VDDQꢀ PowerꢀSupplyꢀforꢀDQꢀPin
GNDQꢀ GroundꢀforꢀDQꢀPin
Chip Select
RASꢀ
ꢀ
RowꢀAddress Strobe Command
NCꢀ
NoꢀConnection
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. D
08/24/09
IS42S16100E, IS45S16100E
PIN CONFIGURATION
package code: B 60 BaLL Tf-Bga (Tꢀꢁ Viꢂw) (10.1 mm x 6.4 mm Bꢀꢃy, 0.65 mm Bꢄll pitꢅh)
1 2 3 4 5 6 7
A
GND DQ15
DQ14 GND
DQ13 VDDQ
DQ12 DQ11
DQ10 GNDQ
DQ9 VDDQ
DQ8 NC
DQ0 VDD
VDDQ DQ1
GNDQ DQ2
DQ4 DQ3
VDDQ DQ5
GNDQ DQ6
B
C
D
E
F
G
H
J
NC
DQ7
NC
NC
NC UDQM
NC CLK
CKE NC
NC
VDD
LDQM WE
K
L
CAS
CS
RAS
NC
NC
A0
M
N
P
R
A11
A8
A9
A7
A5
NC
A10
A1
A6
A2
GND A4
VDD
A3
PIN DESCRIPTIONS
a0-a10
a0-a7
a11
Rꢀw aꢃꢃrꢂss Inꢁut
cꢀlumn aꢃꢃrꢂss Inꢁut
Bꢄnꢆ Sꢂlꢂꢅt aꢃꢃrꢂss
dꢄtꢄ I/o
WE
Writꢂ enꢄblꢂ
LdQM, UdQM
Vd d
x16 Inꢁut/outꢁut Mꢄsꢆ
pꢀwꢂr
dQ0 tꢀ dQ15
cLk
gNd
grꢀunꢃ
Systꢂm clꢀꢅꢆ Inꢁut
clꢀꢅꢆ enꢄblꢂ
Vd d q
pꢀwꢂr Suꢁꢁly ꢇꢀr I/o pin
grꢀunꢃ ꢇꢀr I/o pin
Nꢀ cꢀnnꢂꢅtiꢀn
cke
gNdq
Nc
CS
chiꢁ Sꢂlꢂꢅt
RAS
Rꢀw aꢃꢃrꢂss Strꢀbꢂ cꢀmmꢄnꢃ
CAS
cꢀlumn aꢃꢃrꢂss Strꢀbꢂ cꢀmmꢄnꢃ
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
PIN FUNCTIONS
TSOP Pin No. Symbol
Type
Function (In Detail)
ꢀ
20ꢀtoꢀ24ꢀ
A0-A10ꢀ
InputꢀPin
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32
command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOWꢀduringꢀprechargeꢀcommand,ꢀtheꢀbankꢀselectedꢀbyꢀA11ꢀisꢀprecharged,ꢀbutꢀifꢀA10ꢀisꢀ
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprecharged.
WhenꢀA10ꢀisꢀHIGHꢀinꢀreadꢀorꢀwriteꢀcommandꢀcycle,ꢀtheꢀprechargeꢀstartsꢀautomaticallyꢀ
after the burst access.
TheseꢀsignalsꢀbecomeꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀcommandꢀinput.
ꢀ
19ꢀ
A11ꢀ
InputꢀPinꢀ
A11ꢀisꢀtheꢀbankꢀselectionꢀsignal.ꢀWhenꢀA11ꢀisꢀLOW,ꢀbankꢀ0ꢀisꢀselectedꢀandꢀwhenꢀhigh,ꢀ
bankꢀ1ꢀisꢀselected.ꢀThisꢀsignalꢀbecomesꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀ
command input.
16
CASꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CAS, in conjunction with the RAS and WE, forms the device command. See the
“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
34ꢀ
CKEꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀWhenꢀisꢀ
CKEꢀHIGH,ꢀtheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalid,ꢀandꢀwhenꢀLOW,ꢀinvalid.ꢀ
WhenꢀCKEꢀisꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀtheꢀpower-downꢀmode,ꢀtheꢀclockꢀsuspendꢀ
mode,ꢀorꢀtheꢀselfꢀrefreshꢀmode.ꢀTheꢀCKEꢀisꢀanꢀasynchronousꢀinput.
35ꢀ
CLKꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀ
acquired in synchronization with the rising edge of this pin.
18
CSꢀ
TheꢀCS input determines whether command input is enabled within the device.
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀdeviceꢀ
remains in the previous state when CSꢀisꢀHIGH.
ꢀ
2,ꢀ3,ꢀ5,ꢀ6,ꢀ8,ꢀ9,ꢀ11ꢀ DQ0ꢀtoꢀ
DQꢀPinꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀDQꢀpins.ꢀDQꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
ꢀ 12,ꢀ39,ꢀ40,ꢀ42,ꢀ43,ꢀ
DQ15ꢀ
ꢀ
45,ꢀ46,ꢀ48,ꢀ49
ꢀ
ꢀ
14,ꢀ36ꢀ
ꢀ
LDQM,ꢀ
UDQMꢀ
InputꢀPinꢀ
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀDQꢀbuffers.ꢀInꢀread
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀꢀ
toꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀOE
inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀ
LDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀcanꢀbeꢀ
writtenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀandꢀcannotꢀbeꢀ
written to the device.
17
RASꢀ
ꢀWEꢀ
InputꢀPinꢀ
InputꢀPinꢀ
RAS, in conjunction with CAS and WE, forms the device command. See the “Command
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀ
15ꢀ
ꢀWE, in conjunction with RAS and CAS, forms the device command. See the “Command
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7,ꢀ13,ꢀ38,ꢀ44ꢀ
1,ꢀ25ꢀ
VDDQꢀ
VDDꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
VDDQꢀisꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
VDD is the device internal power supply.
GNDQꢀisꢀtheꢀoutputꢀbufferꢀground.
GND is the device internal ground.
4,ꢀ10,ꢀ41,ꢀ47ꢀ
26,ꢀ50ꢀ
GNDQꢀ
GNDꢀ
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. D
08/24/09
IS42S16100E, IS45S16100E
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
MEMORYꢀCELL
ROW
ADDRESS
BUFFER
ARRAY
2048
CLOCK
MODE
REGISTER
BANK 0
11
GENERATOR
11
A11
DQM
DATAꢀIN
BUFFER
11
SENSEꢀAMPꢀI/OꢀGATE
ꢀꢀ256
16
16
A10
8
ꢀSELF
DQꢀ0-15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
COLUMNꢀDECODER
REFRESH
8
CONTROLLER
ꢀꢀ256
DATAꢀOUT
BUFFER
SENSEꢀAMPꢀI/OꢀGATE
REFRESH
COUNTER
16
16
MEMORYꢀCELL
VDD/VDDQ
GND/GNDQ
ARRAY
2048
ROW
ADDRESS
BUFFER
BANK 1
ROW
ADDRESS
LATCH
11
11
11
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
VD D m a x ꢀ
VD D q m a x
ViNꢀ
Parameters
Rating
Unit
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–1.0ꢀtoꢀ+4.6ꢀ V
–1.0ꢀtoꢀ+4.6ꢀ V
–1.0ꢀtoꢀ+4.6ꢀ V
–1.0ꢀtoꢀ+4.6ꢀ V
Vo u t ꢀ
OutputꢀVoltageꢀ
PD m a x
Ic s
AllowableꢀPowerꢀDissipationꢀ
outputꢀShortedꢀCurrentꢀ
1ꢀ
50ꢀ
W
mA
ꢀ
ꢀ
ꢀ
ꢀ
To p r
operatingꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Commericalꢀ
Industrialꢀ
A1ꢀ
0ꢀtoꢀ+70ꢀ
°Cꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-40ꢀtoꢀ+85ꢀ °Cꢀ
-40ꢀtoꢀ+85ꢀ °Cꢀ
-40ꢀtoꢀ+105ꢀ °C
A2ꢀ
ꢀ
Ts t g ꢀ
StorageꢀTemperatureꢀ
ꢀ
–55ꢀtoꢀ+150ꢀ °C
(2)
DC RECOMMENDED OPERATING CONDITION
(AtꢀTa = 0oC to +70oCꢀforꢀCommercialꢀtemperature,ꢀTa = -40oCꢀtoꢀ+85oCꢀforꢀIndustrialꢀandꢀA1ꢀtemperature,ꢀTa = -40oC to
+105oC for A2 temperature)
Symbol
VD D , VD D qꢀ
Vihꢀ
Parameter
Min.
3.0ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
3.3ꢀ
—ꢀ
Max.
3.6ꢀ
VD D +ꢀ0.3ꢀ
+0.8ꢀ
Unit
V
V
ꢀ
ꢀ
ꢀ
SupplyꢀVoltageꢀ
InputꢀHighꢀVoltage(3)ꢀ
InputꢀLowꢀVoltage(4)ꢀ
Vilꢀ
—ꢀ
V
(1,2)
CAPACITANCE CHARACTERISTICS
(AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVDDꢀ=ꢀVDDQꢀ=ꢀ3.3ꢀ±ꢀ0.3V,ꢀfꢀ=ꢀ1ꢀMHz)
Symbol
CiN1ꢀ
Parameter
Typ.
—ꢀ
Max.
4ꢀ
Unit
pF
InputꢀCapacitance:ꢀA0-A11ꢀ
CiN2ꢀ
InputꢀCapacitance:ꢀ(CLK,ꢀCKE, CS, RAS, CAS, WE,ꢀLDQM,ꢀUDQM)ꢀ
—ꢀ
4ꢀ
pF
ꢀ
CI/Oꢀ
DataꢀInput/OutputꢀCapacitance:ꢀDQ0-DQ15ꢀ
—ꢀ
5ꢀ
pF
Notes:
1.ꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreli-
ability.
2.ꢀAllꢀvoltagesꢀareꢀreferencedꢀtoꢀGND.
3.ꢀVihꢀ(max)ꢀ=ꢀVD D q ꢀ+ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ≤ 3 ns.
4.ꢀVilꢀ(min)ꢀ=ꢀVD D q ꢀ-ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ≤ 3 ns.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
5
Rev. D
08/24/09
IS42S16100E, IS45S16100E
DC ELECTRICAL CHARACTERISTICS (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
InputꢀLeakageꢀCurrentꢀ
Test Condition
Speed Min.
Max. Unit
iil
0Vꢀ≤ꢀViN ≤ꢀVDD, with pins other thanꢀ
ꢀ
ꢀ
–5ꢀ
5ꢀ
µA
ꢀꢀ
ꢀ
theꢀtestedꢀpinꢀatꢀ0V
io l ꢀ
OutputꢀLeakageꢀCurrentꢀ Outputꢀisꢀdisabled,ꢀ0Vꢀ≤ Vo u t ≤ꢀVDDꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–5ꢀ
2.4ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
µAꢀ
V
Vo h ꢀ
Vo l ꢀ
ic c 1ꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ io u t ꢀ=ꢀ–2ꢀmAꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ io u t ꢀ=ꢀ+2ꢀmAꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
ꢀ
0.4ꢀ
170ꢀ
160ꢀ
140ꢀ
V
OperatingꢀCurrent(1,2)
ꢀ
ꢀ
OneꢀBankꢀOperation,ꢀ CASꢀlatencyꢀ=ꢀ3ꢀ Com.ꢀ
-5ꢀ
-6ꢀ
-7ꢀ
mA
ꢀꢀ
BurstꢀLength=1ꢀ
tr c ≥ tr c ꢀ(min.)ꢀ
Io u t = 0mA
ꢀ
ꢀ
Com.ꢀ
Com.ꢀ
Ind, A1
A2
Ind, A1
A2
-6
-6
-7
-7
—
—
—
—
170
180
160
170
ic c 2pꢀ
PrechargeꢀStandbyꢀCurrentꢀCKEꢀ≤ Vilꢀꢀ(m a x )ꢀ
tc k = tc k ꢀ(m iN )ꢀ
tc k = ∞
Comꢀ
Ind, A1
Com
Ind, A1
A2
—ꢀ
—
—
—
—
—ꢀ
—
—
—
—
3ꢀ
4
2
—
—
mAꢀ
mA
Ic c 2p s
(InꢀPower-DownꢀMode)
ic c 3Nꢀ
Ic c 3N s
ActiveꢀStandbyꢀCurrentꢀ
CKEꢀ≥ Vihꢀ(m iN )ꢀ
tc k = tc k ꢀ(m iN )ꢀ
tc k = ∞ꢀ
ꢀ
Com
Ind, A1
A2
—ꢀ
—
—
—
—ꢀ
—
—
—
40ꢀ
30
30
30
(InꢀNonꢀPower-DownꢀMode)
ic c 4ꢀ
ꢀꢀ
OperatingꢀCurrentꢀ
(InꢀBurstꢀMode)(1)ꢀ
tc k = tc k ꢀ(m iN )ꢀ
Io u t =ꢀ0mAꢀ
CASꢀlatencyꢀ=ꢀ3ꢀ Comꢀ
-5ꢀ
-6ꢀ
-6
-6
-7
—ꢀ
—ꢀ
—
—
—
170ꢀ
150ꢀ
170
180
130
150ꢀ
160
mA
ꢀ
ꢀ
Comꢀ
Ind, A1
A2
Com
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ind,ꢀA1ꢀꢀ -7ꢀ
—ꢀ
—
ꢀ
A2
-7
CAS latency = 2 Comꢀ
-5ꢀ
-6ꢀ
-6
-6
-7
—ꢀ
—ꢀ
—
—
—
170ꢀ
150ꢀ
170
180
130
150ꢀ
160
mA
ꢀ
Comꢀ
Ind, A1
A2
Com
ꢀꢀ
ꢀ
ꢀ
Ind,ꢀA1ꢀ
-7ꢀ
-7
—ꢀ
—
ꢀ
A2
Notes:
1.ꢀTheseꢀareꢀtheꢀvaluesꢀatꢀtheꢀminimumꢀcycleꢀtime.ꢀSinceꢀtheꢀcurrentsꢀareꢀtransient,ꢀtheseꢀvaluesꢀdecreaseꢀasꢀtheꢀcycleꢀtimeꢀin-
creases.ꢀAlsoꢀnoteꢀthatꢀaꢀbypassꢀcapacitorꢀofꢀꢀatꢀꢀleastꢀꢀ0.01ꢀµFꢀshouldꢀbeꢀinsertedꢀbetweenꢀVD D andꢀGNDꢀforꢀeachꢀmemoryꢀchipꢀ
toꢀsuppressꢀpowerꢀsupplyꢀvoltageꢀnoiseꢀ(voltageꢀdrops)ꢀdueꢀtoꢀtheseꢀtransientꢀcurrents.
2. Icc1 and Icc4ꢀdependꢀonꢀtheꢀoutputꢀload.ꢀTheꢀmaximumꢀvaluesꢀforꢀIcc1 and Icc4 are obtained with the output open state.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
DC ELECTRICAL CHARACTERISTICS (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
Speed Min.
Max. Unit
ic c 5ꢀ
Auto-RefreshꢀCurrentꢀ
tr c = tr c (m iN )ꢀ
CAS latency = 3 Com.ꢀ
-5ꢀ
-6
-6
-6
-7
-7
-7
—ꢀ
—
—
—
—
—
—
120ꢀ
100
110
120
80
mA
Com.
Ind, A1
A2
Com
Ind, A1
A2
90
100
CASꢀlatencyꢀ=ꢀ2ꢀ Comꢀ
-5ꢀ
-6
-6
-6
—ꢀ
—
—
—
120ꢀ
100
110
120
mA
Com
Ind, A1
A2
Com
Ind, A1
A2
-7
-7
-7
—
—
—
80
90
100
ic c 6ꢀ
Self-RefreshꢀCurrentꢀ
CKEꢀ≤ꢀ0.2Vꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
mA
Notes:
1.ꢀTheseꢀareꢀtheꢀvaluesꢀatꢀtheꢀminimumꢀcycleꢀtime.ꢀSinceꢀtheꢀcurrentsꢀareꢀtransient,ꢀtheseꢀvaluesꢀdecreaseꢀasꢀtheꢀcycleꢀtimeꢀin-
creases.ꢀAlsoꢀnoteꢀthatꢀaꢀbypassꢀcapacitorꢀofꢀꢀatꢀꢀleastꢀꢀ0.01ꢀµFꢀshouldꢀbeꢀinsertedꢀbetweenꢀVD D andꢀGNDꢀforꢀeachꢀmemoryꢀchipꢀ
toꢀsuppressꢀpowerꢀsupplyꢀvoltageꢀnoiseꢀ(voltageꢀdrops)ꢀdueꢀtoꢀtheseꢀtransientꢀcurrents.
2. Icc1 and Icc4ꢀdependꢀonꢀtheꢀoutputꢀload.ꢀTheꢀmaximumꢀvaluesꢀforꢀIcc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2,3)
AC CHARACTERISTICS
-5
-6
-7
Symbol Parameter
Min. Max.
Min.
Max.
Min.
Max.
Units
tck3ꢀ
tc k 2
ClockꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
5ꢀ
8ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
6ꢀ
8ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ta c 3ꢀ
ta c 2
AccessꢀTimeꢀFromꢀCLK(4)
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
ns
ns
tc h iꢀ
tc l ꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
ꢀ
2ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
to h 3ꢀ
to h 2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.0ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.0ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
2.5ꢀ ꢀ —ꢀ
tl z ꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ns
th z 3ꢀ
th z 2
OutputꢀHIGHꢀImpedanceꢀTime(5)
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
ns
ns
tD s ꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD h ꢀ
ta s ꢀ
ta h ꢀ
tc k s ꢀ
tc k h ꢀ
tc k a ꢀ
tc s ꢀ
CKEꢀSetupꢀTimeꢀ
CKEꢀHoldꢀTimeꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3ꢀ —ꢀ
1CLK+3ꢀ —ꢀ
1CLK+3ꢀ —ꢀ
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
tc h ꢀ
tr c ꢀ
50ꢀ ꢀ —ꢀ
35ꢀ ꢀ100,000ꢀ
15ꢀ ꢀ —ꢀ
15ꢀ ꢀ —ꢀ
10ꢀ ꢀ —ꢀ
2CLKꢀꢀ —ꢀ
54ꢀ
63ꢀ
tr a s ꢀ
tr p ꢀ
36ꢀ ꢀ100,000ꢀ
42ꢀ ꢀ100,000ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
18ꢀ
18ꢀ
12ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
21ꢀ
21ꢀ
14ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
tr c D ꢀ
tr r D ꢀ
tD p l 3ꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ ꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
ꢀ ꢀ ꢀ
tD p l 2
CAS Latencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
ns
tD a l 3ꢀ
ꢀ ꢀ ꢀ
tD a l 2
tx s r
tt
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)
2CLK+tr p —ꢀ
2CLK+tr p —ꢀ
2CLK+tr p
2CLK+tr p
—
ns
CAS Latencyꢀ=ꢀ2ꢀ
2CLK+tr p —ꢀ
55ꢀ ꢀ —ꢀ
2CLK+tr p —ꢀ
—
—ꢀ
1.2ꢀ
32
ns
ns
ns
ms
ExitꢀSelf-RefreshꢀtoꢀActiveꢀTimeꢀ
TransitionꢀTimeꢀ
ꢀ
ꢀ
60ꢀ
0.3ꢀ
—
ꢀ
ꢀ
—ꢀ
1.2ꢀ
32
70ꢀ
0.3ꢀ
—
ꢀ
ꢀ
0.3ꢀ ꢀ 1.2ꢀ
tr e f ꢀ
RefreshꢀCycleꢀTimeꢀ(2048)ꢀforꢀtemperatureꢀTa ≤ꢀ85oC
RefreshꢀCycleꢀTimeꢀ(2048)ꢀforꢀtemperatureꢀTa >ꢀ85oCꢀ(A2ꢀonly)6
—
—
32
—
tr e f ꢀ
—
—
—
16
ms
Notes:
1.ꢀWhenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ100ꢀµsꢀafterꢀVD D andꢀVD D q reach their stipulated voltages. Also note that the power-on
ꢀ
sequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2. measured with tt = 1 ns.
3.ꢀTheꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil (max.).
4.ꢀAccessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.
5.ꢀTheꢀtimeꢀth z (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ±ꢀ200ꢀmVꢀfromꢀVo h (min.)ꢀorꢀVo l ꢀ(max.)ꢀwhenꢀthe
output is in the high impedance state.
6.ꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ85oC.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS (CAS Latencyꢀ=ꢀ3)
SYMBOL PARAMETER
-5
5ꢀ
-6
6ꢀ
-7
7ꢀ
UNITS
ns
—ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
OperatingꢀFrequencyꢀ
200ꢀ
3ꢀ
166ꢀ
3ꢀ
143ꢀ
3ꢀ
MHz
tc a c
tr c D ꢀ
tr a c
tr c
CASꢀꢀLatencyꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(tr c D + tc a c )ꢀ
3ꢀ
3ꢀ
3ꢀ
6ꢀ
6ꢀ
6ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
10ꢀ
7ꢀ
9ꢀ
9ꢀ
tr a s ꢀ
tr p ꢀ
tr r D ꢀ
6ꢀ
6ꢀ
3ꢀ
3ꢀ
3ꢀ
2ꢀ
2ꢀ
2ꢀ
tc c D ꢀ
ꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(REꢀAD,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
1ꢀ
1ꢀ
ꢀ
tD p l ꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
cycle
cycle
tD a l ꢀ
ꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tr b D ꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
cycle
cycle
cycle
cycle
tw b D ꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)ꢀ
tr q l ꢀ
ꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
tw D l ꢀ
ꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)
tp q l ꢀ
tq m D ꢀ
tD m D ꢀ
tm c D ꢀ
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–2ꢀ
2ꢀ
–2ꢀ
2ꢀ
–2ꢀ
2ꢀ
cycle
cycle
cycle
cycle
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
0ꢀ
0ꢀ
0ꢀ
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
2ꢀ
2ꢀ
2ꢀ
AC TEST CONDITIONS (Input/OutputꢀReferenceꢀLevel:ꢀ1.4V)
Output Load
Input
t
CK
tCL
t
CHI
2.8V
1.4V
50ꢀΩ
CLK
0.0V
+1.4V
I/O
t
CS
tCH
2.8V
1.4V
0.0V
INPUT
ꢀ50ꢀpF
t
AC
t
OH
1.4V
1.4V
OUTPUT
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
08/24/09
IS42S16100E, IS45S16100E
COMMANDS
Active Command
Read Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
CAS
WE
WE
(1)
COLUMN
ROW
A0-A9
A10
A0-A9
AUTOꢀPRECHARGE
ROW
A10
A11
NOꢀPRECHARGE
BANKꢀ1
BANKꢀ1
A11
BANKꢀ0
BANKꢀ0
Write Command
Precharge Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
A0-A9
A0-A9
AUTOꢀPRECHARGE
BANKꢀ0ꢀANDꢀBANKꢀ1
A10
A11
A10
A11
NOꢀPRECHARGE
BANKꢀ0ꢀORꢀBANKꢀ1
BANKꢀ1
BANKꢀ1
BANKꢀ0
BANKꢀ0
Don'tꢀCare
Notes:
1.ꢀꢀA8-A9ꢀ=ꢀDon’tꢀCare.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
COMMANDS (cont.)
No-Operation Command
Device Deselect Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
A0-A9
A10
A11
A10
A11
Mode Register Set Command
Auto-Refresh Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0-A9
OP-CODE
OP-CODE
OP-CODE
A0-A9
A10
A11
A10
A11
Don'tꢀCare
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. D
08/24/09
IS42S16100E, IS45S16100E
COMMANDS (cont.)
Self-Refresh Command
Power Down Command
CLK
CLK
ALLꢀBANKSꢀIDLE
CKE
CKE
NOP
NOP
CS
CS
RAS
RAS
NOP
CAS
WE
CAS
WE
NOPꢀ
A0-A9
A0-A9
A10
A11
A10
A11
Clock Suspend Command
Burst Stop Command
CLK
CLK
BANK(S)ꢀACTIVE
CKE
HIGH
CKE
NOP
CS
CS
NOP
RAS
RAS
NOP
CAS
CAS
WE
NOP
WE
A0-A9
A0-A9
A10
A11
A10
A11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Mode Register Set Command
(CS, RAS, CAS, WEꢀ=ꢀLOW)
WhenꢀtheꢀA10ꢀpinꢀisꢀHIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀaꢀ
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
WhenꢀtheꢀA10ꢀpinꢀisꢀLOW,ꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀ
pin remains in the activated state after the burst read
completes.
Theꢀ IS42/4516100Eꢀ productꢀ incorporatesꢀ aꢀ registerꢀ
thatꢀdefinesꢀtheꢀdeviceꢀoperatingꢀmode.ꢀThisꢀcommandꢀ
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulatedꢀpower-onꢀsequenceꢀshouldꢀbeꢀexecutedꢀandꢀ
thenꢀtheꢀIS42/4516100Eꢀshouldꢀbeꢀinitializedꢀbyꢀexecutingꢀ
a mode register set command.
Noteꢀ thatꢀ theꢀ modeꢀ registerꢀ setꢀ commandꢀ canꢀ beꢀ
executedꢀonlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀstateꢀ(i.e.ꢀ
deactivated).
Write Command
(CS, CAS, WEꢀ=ꢀLOW,ꢀꢀRASꢀ=ꢀHIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
atꢀtheꢀstartꢀaddressꢀspecifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀThisꢀfirstꢀ
dataꢀmustꢀbeꢀinputꢀtoꢀtheꢀDQꢀpinsꢀinꢀtheꢀcycleꢀinꢀwhichꢀ
this command.
Anotherꢀ commandꢀ cannotꢀ beꢀ executedꢀ afterꢀ aꢀ modeꢀ
registersetcommanduntilafterthepassageoftheperiod
tm c D , which is the period required for mode register set
commandꢀexecution.
Theꢀ selectedꢀ bankꢀ mustꢀ beꢀ activatedꢀ beforeꢀ executingꢀ
this command.
Active Command
(CS, RASꢀ=ꢀLOW,ꢀCAS, WE=ꢀHIGH)
Whenꢀ A10ꢀ pinꢀ isꢀ HIGH,ꢀ thisꢀ commandꢀ functionsꢀ asꢀ aꢀ
write with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11
pin remains in the activated state after the burst write
completes.
TheꢀIS42/4516100Eꢀincludesꢀtwoꢀbanksꢀofꢀ2048ꢀrowsꢀeach.ꢀ
Thisꢀcommandꢀselectsꢀoneꢀofꢀtheꢀtwoꢀbanksꢀaccordingꢀ
to the A11 pin and activates the row selected by the pins
A0 to A10.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀfallꢀofꢀtheꢀRAS signal
fromꢀHIGHꢀtoꢀLOWꢀinꢀconventionalꢀDRAMs.
After the input of the last burst write data, the application
mustꢀwaitꢀforꢀtheꢀwriteꢀrecoveryꢀperiodꢀ(tD p l , tD a l )ꢀtoꢀelapseꢀ
according to CAS latency.
Precharge Command
(CS, RAS, WEꢀ=ꢀLOW,ꢀCASꢀ=ꢀHIGH)
Thisꢀcommandꢀstartsꢀprechargingꢀtheꢀbankꢀselectedꢀbyꢀ
pinsꢀA10ꢀandꢀA11.ꢀWhenꢀA10ꢀisꢀHIGH,ꢀbothꢀbanksꢀareꢀ
prechargedꢀatꢀtheꢀsameꢀtime.ꢀWhenꢀA10ꢀisꢀLOW,ꢀtheꢀ
bankꢀselectedꢀbyꢀA11ꢀisꢀprecharged.ꢀAfterꢀexecutingꢀthisꢀ
command,ꢀtheꢀnextꢀcommandꢀforꢀtheꢀselectedꢀbank(s)ꢀ
isꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtr p , which is the
period required for bank precharging.
Auto-Refresh Command
(CS, RAS, CASꢀ=ꢀLOW,ꢀWE,ꢀCKEꢀꢀ=ꢀHIGH)
Thisꢀcommandꢀexecutesꢀtheꢀauto-refreshꢀoperation.ꢀTheꢀ
row address and bank to be refreshed are automatically
generated during this operation.
Bothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀidleꢀstateꢀbeforeꢀexecutingꢀ
this command.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀRASꢀsignalꢀfromꢀLOWꢀ
toꢀHIGHꢀinꢀconventionalꢀDRAMs
Theꢀstipulatedꢀperiodꢀ(tr c )ꢀisꢀrequiredꢀforꢀaꢀsingleꢀrefreshꢀ
operation,ꢀandꢀnoꢀotherꢀcommandsꢀcanꢀbeꢀexecutedꢀduringꢀ
this period.
Read Command
Theꢀdeviceꢀgoesꢀtoꢀtheꢀidleꢀstateꢀafterꢀtheꢀinternalꢀrefreshꢀ
(CS, CASꢀ=ꢀLOW,ꢀRAS, WEꢀ=ꢀHIGH)
operation completes.
ThisꢀcommandꢀselectsꢀtheꢀbankꢀspecifiedꢀbyꢀtheꢀA11ꢀpinꢀ
and starts a burst read operation at the start address
specifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀDataꢀisꢀoutputꢀfollowingꢀCAS
latency.
Thisꢀcommandꢀmustꢀbeꢀexecutedꢀperiodicallyꢀaccordingꢀ
to tr e f ꢀspecificationꢀ(ACꢀCharacteristics).
Thisꢀ commandꢀ correspondsꢀ toꢀ CBRꢀ auto-refreshꢀ inꢀ
conventionalꢀDRAMs.
Theꢀselectedꢀbankꢀmustꢀbeꢀactivatedꢀbeforeꢀexecutingꢀ
this command.
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Self-Refresh Command
Power-Down Command
(CS, RAS, CAS,ꢀCKEꢀ=ꢀLOW,ꢀWEꢀ=ꢀHIGH)
(CKEꢀ=ꢀLOW)
Thisꢀcommandꢀexecutesꢀtheꢀself-refreshꢀoperation.ꢀTheꢀ
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation.ꢀTheꢀself-refreshꢀoperationꢀisꢀstartedꢀbyꢀdroppingꢀ
theꢀCKEꢀpinꢀfromꢀHIGHꢀtoꢀLOW.ꢀTheꢀself-refreshꢀoperationꢀ
continuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀremainsꢀLOWꢀandꢀthereꢀ
isꢀ noꢀ needꢀ forꢀ externalꢀ controlꢀ ofꢀ anyꢀ otherꢀ pins.ꢀTheꢀ
self-refreshꢀoperationꢀisꢀterminatedꢀbyꢀraisingꢀtheꢀCKEꢀ
pinꢀfromꢀLOWꢀtoꢀHIGH.ꢀTheꢀnextꢀcommandꢀcannotꢀbeꢀ
executedꢀuntilꢀtheꢀdeviceꢀinternalꢀrecoveryꢀperiodꢀ(tx s r )
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addressesꢀ(4096ꢀcycles).
Whenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀ(inactive)ꢀstate,ꢀorꢀwhenꢀ
atꢀleastꢀoneꢀofꢀtheꢀbanksꢀisꢀnotꢀinꢀtheꢀidleꢀ(inactive)ꢀstate,ꢀ
this command can be used to suppress device power
dissipation by reducing device internal operations to
theꢀabsoluteꢀminimum.ꢀPower-downꢀmodeꢀisꢀstartedꢀbyꢀ
droppingꢀtheꢀCKEꢀpinꢀfromꢀHIGHꢀtoꢀLOW.ꢀPower-downꢀ
modeꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀisꢀheldꢀlow.ꢀAllꢀpinsꢀ
otherꢀthanꢀtheꢀCKEꢀpinꢀareꢀinvalidꢀandꢀnoneꢀofꢀtheꢀotherꢀ
commandsꢀcanꢀbeꢀexecutedꢀinꢀthisꢀmode.ꢀTheꢀpower-downꢀ
operationꢀisꢀterminatedꢀbyꢀraisingꢀtheꢀCKEꢀpinꢀfromꢀLOWꢀ
toꢀHIGH.ꢀTheꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀ
recoveryꢀperiodꢀ(tc k a )ꢀhasꢀelapsed.
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tr e f ).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀpower-downꢀmodeꢀcanꢀbeꢀheldꢀisꢀ
just under the refresh cycle time.
Bothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀidleꢀstateꢀbeforeꢀexecutingꢀ
this command.
Burst Stop Command
(CS, WE,ꢀ=ꢀLOW,ꢀRAS, CASꢀ=ꢀHIGH)
Clock Suspend
(CKEꢀ=ꢀLOW)
Theꢀcommandꢀforciblyꢀterminatesꢀburstꢀreadꢀandꢀwriteꢀ
operations.ꢀWhenꢀthisꢀcommandꢀisꢀexecutedꢀduringꢀaꢀburstꢀ
read operation, data output stops after the CAS latency
period has elapsed.
Thisꢀcommandꢀcanꢀbeꢀusedꢀtoꢀstopꢀtheꢀdeviceꢀinternalꢀ
clock temporarily during a read or write cycle. Clock
suspendꢀmodeꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀfromꢀ
HIGHꢀtoꢀLOW.ꢀClockꢀsuspendꢀmodeꢀcontinuesꢀasꢀlongꢀasꢀ
theꢀCKEꢀpinꢀisꢀheldꢀLOW.ꢀAllꢀinputꢀpinsꢀotherꢀthanꢀtheꢀCKEꢀ
pin are invalid and none of the other commands can be
executedꢀinꢀthisꢀmode.ꢀAlsoꢀnoteꢀthatꢀtheꢀdeviceꢀinternalꢀ
state is maintained. Clock suspend mode is terminated
byꢀraisingꢀtheꢀCKEꢀpinꢀfromꢀLOWꢀtoꢀHIGH,ꢀatꢀwhichꢀpointꢀ
deviceꢀoperationꢀrestarts.ꢀTheꢀnextꢀcommandꢀcannotꢀbeꢀ
executedꢀuntilꢀtheꢀrecoveryꢀperiodꢀ(tc k a )ꢀhasꢀelapsed.
No Operation
(CS,ꢀ=ꢀLOW,ꢀRAS, CAS, WEꢀ=ꢀHIGH)
Thisꢀcommandꢀhasꢀnoꢀeffectꢀonꢀtheꢀdevice.
Device Deselect Command
(CSꢀ=ꢀHIGH)
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tr e f ).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀclockꢀsuspendꢀmodeꢀcanꢀbeꢀheldꢀ
is just under the refresh cycle time.
Thisꢀcommandꢀdoesꢀnotꢀselectꢀtheꢀdeviceꢀforꢀanꢀobjectꢀofꢀ
operation. In other words, it performs no operation with
respect to the device.
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2)
COMMAND TRUTH TABLE
CKE
n-1
Hꢀ Xꢀ
Hꢀ Hꢀ Lꢀ
Symbol Command
n
CS RAS CAS WEDQM A11 A10 A9-A0 I/On
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MRSꢀ
REFꢀ
SREFꢀ
PREꢀ
PALLꢀ
ACTꢀ
ModeꢀRegisterꢀSet(3,4)
Auto-Refresh(5)ꢀ
Self-Refresh(5,6)ꢀ
PrechargeꢀSelectedꢀBankꢀ
PrechargeꢀBothꢀBanksꢀ
BankꢀActivate(7)ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
ꢀ ꢀOPꢀCODEꢀ ꢀ
X
Lꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ HIGH-Z
Xꢀ HIGH-Z
Xꢀ
Xꢀ
Hꢀ Lꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ Xꢀ BSꢀ Rowꢀ Rowꢀ
Xꢀ BSꢀ
Xꢀ Xꢀ
X
X
X
Hꢀ
(18)
WRITꢀ
WRITAꢀ
READꢀ
READAꢀ
BSTꢀ
Writeꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Xꢀ BSꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Xꢀ BSꢀ
Lꢀ Hꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ
Lꢀ
Lꢀ
Xꢀ BSꢀ
Xꢀ BSꢀ
Lꢀ Column ꢀ X
WriteꢀWithꢀAuto-Precharge(8)ꢀ
Read(8)ꢀ
ReadꢀWithꢀAuto-Precharge(8)ꢀ
BurstꢀStop(9)ꢀ
Hꢀ Column ꢀ X
(18)
(18)
Lꢀ Column ꢀ X
(18)
HꢀꢀColumn ꢀ X
Xꢀ Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
NOPꢀ
NoꢀOperationꢀ
DESLꢀ
SBYꢀ
ENBꢀ
DeviceꢀDeselectꢀ
Hꢀ Xꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Lꢀ Xꢀ
Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Hꢀ Xꢀ
ClockꢀSuspendꢀ/ꢀStandbyꢀModeꢀ
DataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
DataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
X
Active
MASKꢀ
Xꢀ HIGH-Z
(1,2)
DQM TRUTH TABLE
CKE
DQM
UPPER
Symbol Command
n-1
n
LOWER
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ENBꢀ
DataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
DataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
UpperꢀByteꢀDataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
LowerꢀByteꢀDataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
L
H
X
L
X
H
MASKꢀ
ENBUꢀ
ENBLꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
MASKUꢀ UpperꢀByteꢀDataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
MASKLꢀ LowerꢀByteꢀDataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
(1,2)
CKE TRUTH TABLE
CKE
n-1
Hꢀ Lꢀ
Lꢀ Lꢀ
Symbol Command
Current State
Activeꢀ
OtherꢀStatesꢀ
n
CS RAS CAS WE A11 A10A9-A0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SPNDꢀ StartꢀClockꢀSuspendꢀModeꢀ
Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
X
X
X
X
—ꢀ
ClockꢀSuspendꢀ
—ꢀ
TerminateꢀClockꢀSuspendꢀModeꢀ ClockꢀSuspendꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Hꢀ Hꢀ Lꢀ
Hꢀ Lꢀ Lꢀ
REFꢀ
Auto-Refreshꢀ
Idleꢀ
Idleꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
SELFꢀ StartꢀSelf-RefreshꢀModeꢀ
ꢀ
ꢀ
SELFXꢀ TerminateꢀSelf-RefreshꢀModeꢀ
Self-Refreshꢀ
ꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
PDWNꢀ StartꢀPower-DownꢀModeꢀ
Idleꢀ
ꢀ
Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ
X
X
ꢀ
ꢀ
Hꢀ Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
ꢀ
—ꢀ
TerminateꢀPower-DownꢀModeꢀ
Power-Downꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
15
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
Idleꢀ
DESLꢀ
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Downꢀ
Illegalꢀ
ꢀ
ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READꢀ/ꢀREADAꢀ
WRIT/WRITAꢀ
ACTꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
ꢀ
Illegalꢀ
Lꢀ
ꢀ
RowꢀActiveꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperationꢀ
Lꢀ
X
ꢀ
Auto-RefreshꢀorꢀSelf-Refresh(13)
ModeꢀRegisterꢀSetꢀ
NoꢀOperationꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
RowꢀActiveꢀ
DESLꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
NoꢀOperationꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
NoꢀOperationꢀ
ReadꢀStart(17)
WriteꢀStart(17)
Illegal(10)
ꢀ
Hꢀ
Lꢀ
V
V
V
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
(18)
ꢀ
ꢀ
Lꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Precharge(15)
ꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODEꢀ
Readꢀ
DESLꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀInterrupted,ꢀReadꢀRestartꢀAfterꢀInterrupt(16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀInterruptedꢀWriteꢀStartꢀAfterꢀInterrupt(11,16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀReadꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Illegalꢀ
Lꢀ
X
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
Writeꢀ
DESLꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀWriteꢀInterrupted,ꢀReadꢀStartꢀAfterꢀInterrupt(11,16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀWriteꢀInterrupted,ꢀWriteꢀRestartꢀAfterꢀInterrupt(16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀWriteꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Lꢀ
X
Illegalꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
ReadꢀWithꢀ
Auto-ꢀ
DESLꢀ
NOPꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Prechargeꢀ
BSTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
V
V
V
(18)
(18)
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
Illegalꢀ
ꢀ OPꢀCODE
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
Write With
Auto-Prechargeꢀ
DESLꢀ
ꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
WhenꢀDone
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
NOPꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
BSTꢀ
Illegalꢀ
Illegalꢀ
X
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
V
V
V
(18)
(18)
Illegalꢀ
(10)
Illegal
Illegal
ꢀ
ꢀ
(10)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
Illegalꢀ
Illegalꢀ
ꢀ OPCODE
RowꢀPrechargeꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p ꢀHasꢀElapsedꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p HasꢀElapsedꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p ꢀHasꢀElapsedꢀ
X
(18)
(10)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal
Illegal
Illegal
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
V
V
V
(10)
(10)
(18)
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
(10)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p ꢀHasꢀElapsed
ꢀ
X
X
Illegalꢀ
Illegalꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
Immediatelyꢀ
Followingꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtr c D ꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtr c D ꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Xꢀ
Xꢀ
Vꢀ
ꢀ
RowꢀActiveꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtr c D ꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
X
(18)
(10)
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal
ꢀ
V
(10)
(10,14)
(10)
ꢀ
(18)
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Illegal
Illegal
Illegal
ꢀ
Lꢀ Hꢀ Lꢀ
Vꢀ Vꢀ V
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Hꢀ Vꢀ Vꢀ V
Lꢀ Hꢀ Lꢀ Vꢀ Vꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
Illegalꢀ
Illegalꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀOPꢀCODE
ꢀ
ꢀ
Writeꢀ
Recoveryꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtD p l HasꢀElapsedꢀ Hꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtD p l HasꢀElapsedꢀ Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtD p l ꢀHasꢀElapsedꢀ Lꢀ
Hꢀ Hꢀ Lꢀ
Xꢀ Xꢀ
X
(18)
(18)
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
ReadꢀStartꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Vꢀ Vꢀ V
WriteꢀRestartꢀ
(10)
Lꢀ Hꢀ Lꢀ
Lꢀ
Lꢀ Hꢀ Hꢀ Vꢀ Vꢀ V
Lꢀ Hꢀ Lꢀ Vꢀ Vꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Lꢀ
Vꢀ Vꢀ V
Illegal
Illegal
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
(10)
X
X
Illegalꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀOPꢀCODE
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
ꢀWriteꢀRecoveryꢀ
ꢀWithꢀAuto-ꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtD a l ꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtD a l ꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀPrechargeꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtD a l ꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
Illegal(10)
Illegal(10)
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
(18)
ꢀ
ꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
ꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
ꢀ OPꢀCODE
Refreshꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p HasꢀElapsedꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p ꢀHasꢀElapsedꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtr p ꢀHasꢀElapsedꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
Hꢀ
Lꢀ
X
ꢀ OPꢀCODE
ꢀ
ꢀ
ModeꢀRegisterꢀ DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtm c D ꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtm c D ꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Setꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtm c D ꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
V
V
V
(18)
(18)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
ꢀ OPꢀCODE
Notes:
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput,ꢀV:ꢀValidꢀdataꢀinput
2.ꢀAllꢀinputꢀsignalsꢀareꢀlatchedꢀonꢀtheꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignal.
3.ꢀBothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
4.ꢀTheꢀstateꢀofꢀtheꢀA0ꢀtoꢀA11ꢀpinsꢀisꢀloadedꢀintoꢀtheꢀmodeꢀregisterꢀasꢀanꢀOPꢀcode.
5.ꢀTheꢀrowꢀaddressꢀisꢀgeneratedꢀautomaticallyꢀinternallyꢀatꢀthisꢀtime.ꢀTheꢀDQꢀpinꢀandꢀtheꢀaddressꢀpinꢀdataꢀisꢀignored.
6.ꢀDuringꢀaꢀself-refreshꢀoperation,ꢀallꢀpinꢀdataꢀ(states)ꢀotherꢀthanꢀCKEꢀisꢀignored.
7.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
8.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀactiveꢀstateꢀinꢀadvance.
9.ꢀThisꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀburstꢀlengthꢀsetꢀtoꢀfullꢀpage.
10.ꢀThisꢀisꢀpossibleꢀdependingꢀonꢀtheꢀstateꢀofꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀpin.
11.ꢀTimeꢀtoꢀswitchꢀinternalꢀbussesꢀisꢀrequired.
12.ꢀTheꢀIS42/4516100Eꢀcanꢀbeꢀswitchedꢀtoꢀpower-downꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀꢀ
state.ꢀInputꢀpinsꢀotherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
ꢀꢀꢀꢀꢀꢀꢀ
13.ꢀTheꢀIS42/4516100Eꢀcanꢀbeꢀswitchedꢀtoꢀself-refreshꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀstate.ꢀꢀꢀꢀꢀꢀꢀꢀ
InputꢀpinsꢀotherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
14.ꢀPossibleꢀifꢀtr r D is satisfied.
15.ꢀIllegalꢀifꢀtr a s is not satisfied.
16.ꢀTheꢀconditionsꢀforꢀburstꢀinterruptionꢀmustꢀbeꢀobserved.ꢀAlsoꢀnoteꢀthatꢀtheꢀIS42/4516100Eꢀwillꢀenterꢀtheꢀprechargedꢀstateꢀꢀ ꢀꢀꢀꢀꢀꢀꢀ
immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period tr c D hasꢀelapsed.ꢀAlsoꢀnoteꢀthatꢀtheꢀIS42/4516100Eꢀwillꢀenterꢀtheꢀꢀ
precharged state immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don’t care.
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1)
CKE RELATED COMMAND TRUTH TABLE
CKE
n-1
Current State
Operation
n
CS RAS CAS WE A11 A10 A9-A0
ꢀ
ꢀ
ꢀ
Self-Refreshꢀ
Undefinedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ꢀ
ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Illegal(2)ꢀ
Lꢀ
Lꢀ
Illegal(2)ꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
Self-Refreshꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Self-RefreshꢀRecoveryꢀ
IdleꢀStateꢀAfterꢀtr c ꢀHasꢀElapsedꢀ
Idle State After tr c ꢀHasꢀElapsedꢀ
Illegalꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Illegalꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Power-DownꢀonꢀtheꢀNextꢀCycleꢀ
Power-DownꢀonꢀtheꢀNextꢀCycleꢀ
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycleꢀ(2)ꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ClockꢀSuspendꢀ
Undefinedꢀ
Lꢀ
Power-Downꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power-DownꢀModeꢀTermination,ꢀIdleꢀAfterꢀꢀ
ThatꢀTermination(2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power-DownꢀModeꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
BothꢀBanksꢀIdleꢀ
NoꢀOperationꢀ
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
BankꢀActiveꢀOrꢀPrechargeꢀ
Auto-Refreshꢀ
ꢀ
ꢀ
ꢀ
ModeꢀRegisterꢀSetꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
Self-Refresh(3)ꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
ꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
Power-DownꢀMode(3)ꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
OtherꢀStatesꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
ClockꢀSuspendꢀonꢀtheꢀNextꢀCycle(4)ꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycleꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycleꢀLꢀ Lꢀ
Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Notes:
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput
2.ꢀTheꢀCLKꢀpinꢀandꢀtheꢀotherꢀinputꢀareꢀreactivatedꢀasynchronouslyꢀbyꢀtheꢀtransitionꢀofꢀtheꢀCKEꢀlevelꢀfromꢀLOWꢀtoꢀHIGH.ꢀꢀ
Theꢀminimumꢀsetupꢀtimeꢀ(tc k a )ꢀrequiredꢀbeforeꢀallꢀcommandsꢀotherꢀthanꢀmodeꢀterminationꢀmustꢀbeꢀsatisfied.
3.ꢀBothꢀbanksꢀmustꢀbeꢀsetꢀtoꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvanceꢀtoꢀswitchꢀtoꢀpower-downꢀmodeꢀorꢀself-refreshꢀmode.
4.ꢀTheꢀinputꢀmustꢀbeꢀcommandꢀdefinedꢀinꢀtheꢀoperationꢀcommandꢀtable.
ꢀꢀꢀꢀꢀ
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. D
08/24/09
IS42S16100E, IS45S16100E
(1,2)
TWO BANKS OPERATION COMMAND TRUTH TABLE
Previous State
Next State
Operation
DESLꢀ
NOPꢀ
CS RAS CAS WE A11 A10A9-A0
Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ
BANK 0BANK 1 BANK 0BANK 1
ꢀ
ꢀ
ꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Any
Any
BSTꢀ
Lꢀ Hꢀ Hꢀ Lꢀ
Xꢀ Xꢀ Xꢀ
R/W/Aꢀ I/Aꢀ
I/A
I/Aꢀ R/W/Aꢀ
I/A
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ
I
I/Aꢀ
I/A
I/Aꢀ
Aꢀ
I/Aꢀ
Aꢀ
RPꢀ
RPꢀ
Rꢀ
Rꢀ
I/Aꢀ
Aꢀ
I/A
I/A
A
I
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I
I
READ/READAꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Hꢀ Hꢀ CA(3)ꢀ
RP
RP
R
R
I/A
A
I/A
A
WP
WP
W
W
I/A
A
H
H CA(3)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
ꢀ
WRIT/WRITAꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ CA(3)ꢀ
H
H CA(3)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
I/Aꢀ
Aꢀ
WPꢀ
WPꢀ
Wꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
I/A
A
Aꢀ
R/Wꢀ
Wꢀ
ꢀ
ꢀ
ACTꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ Hꢀ Hꢀ Hꢀ RAꢀ RAꢀ
Anyꢀ
Iꢀ
Iꢀ
Anyꢀ
Anyꢀ
Aꢀ
A
Any
ꢀ
ꢀ
ꢀ
Lꢀ RAꢀ RAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
PRE/PALLꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ Hꢀ Lꢀ
Xꢀ Hꢀ Xꢀ
Xꢀ Hꢀ Xꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
I/Aꢀ R/W/A/Iꢀ
R/W/A/Iꢀ I/Aꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
Iꢀ
Iꢀ
I/Aꢀ
I
I
I
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Lꢀ
Hꢀ Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
R/W/A/Iꢀ
Iꢀ
I
Lꢀ
Lꢀ
Lꢀ
Lꢀ
I/A
ꢀ
Iꢀ R/W/A/I
ꢀ
ꢀ
REFꢀ
MRSꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Lꢀ ꢀOPCODEꢀꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
I
I
Notes:
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput,ꢀRA:ꢀRowꢀAddress,ꢀCA:ꢀColumnꢀAddress
2.ꢀTheꢀdeviceꢀstateꢀsymbolsꢀareꢀinterpretedꢀasꢀfollows:
ꢀ
ꢀ
ꢀ
Iꢀ
Idleꢀ(inactiveꢀstate)
RowꢀActiveꢀState
Read
Aꢀ
Rꢀ
W
Write
ꢀ
ꢀ
RPꢀ ReadꢀWithꢀAuto-Precharge
WPꢀ WriteꢀWithꢀAuto-Precharge
Any Any State
3. CA: A8,A9 = don’t care.
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
SIMPLIFIED STATE TRANSITION DIAGRAM (OneꢀBankꢀOperation)
SELF
REFRESH
SREFꢀentry
SREFꢀexit
MRS
MODE
REGISTER
SET
AUTO
REF
IDLE
REFRESH
CKE_
CKE
IDLE
ACT
POWER
DOWN
ACTIVE
POWER
DOWN
CKE_
CKE
BANK
ACTIVE
BST
BST
READ
WRITꢀ
WRIT
CKE_
READ
CKE_
WRITA
READA
READ
WRITE
READ
WRIT
CKE
READA
CKE_
CLOCK
SUSPEND
CKE
CLOCK
SUSPEND
WRITA
WRITA
READA
CKE_
CKE
CKE
WRITEꢀWITH
AUTO
READꢀWITH
AUTO
PRECHARGE
PRECHARGE
PRE
PREꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
PRE
PRE-
CHARGE
PREꢀ
POWERꢀAPPLIED
POWERꢀON
Automatic transition following the
completion of command execution.
Transition due to command input.
Integrated Silicon Solution, Inc. — www.issi.com
21
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Device Initialization At Power-On
Burst Length
(Power-OnꢀSequence)
When writing or reading, data can be input or output data
continuously.In these operations, an address is input only
once and that address is taken as the starting address
internallyꢀ byꢀ theꢀ device.ꢀTheꢀ deviceꢀ thenꢀ automaticallyꢀ
generatesꢀ theꢀ followingꢀ address.ꢀTheꢀ burstꢀ lengthꢀ fieldꢀ
in the mode register stipulates the number of data items
inputꢀorꢀoutputꢀinꢀsequence.ꢀInꢀtheꢀIS42/4516100Eꢀproduct,ꢀ
a burst length of 1, 2, 4, 8, or full page can be specified.
Seeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀonꢀsettingꢀtheꢀ
mode register.
AsꢀisꢀtheꢀcaseꢀwithꢀconventionalꢀDRAMs,ꢀtheꢀIS42/4516100Eꢀ
productꢀmustꢀbeꢀinitializedꢀbyꢀexecutingꢀaꢀstipulatedꢀpower-
on sequence after power is applied.
AfterꢀpowerꢀisꢀappliedꢀandꢀVDDꢀandꢀVDDQꢀreachꢀtheirꢀ
stipulatedꢀvoltages,ꢀsetꢀandꢀholdꢀtheꢀCKEꢀandꢀDQMꢀpinsꢀ
HIGHꢀforꢀ100ꢀµs.ꢀThen,ꢀexecuteꢀtheꢀprechargeꢀcommandꢀ
toꢀprechargeꢀbothꢀbank.ꢀNext,ꢀexecuteꢀtheꢀauto-refreshꢀ
command twice or more and define the device operation
modeꢀbyꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀcommand.
Theꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀalsoꢀsetꢀbeforeꢀ
auto-refresh command.
Burst Type
Theꢀ burstꢀ dataꢀ orderꢀ duringꢀ aꢀ readꢀ orꢀ writeꢀ operationꢀ
is stipulated by the burst type, which can be set by the
modeꢀregisterꢀsetꢀcommand.ꢀTheꢀIS42/4516100Eꢀproductꢀ
supports sequential mode and interleaved mode burst
typeꢀsettings.ꢀSeeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀ
onꢀsettingꢀtheꢀmodeꢀregister.ꢀSeeꢀtheꢀ“BurstꢀLengthꢀandꢀ
ColumnꢀAddressꢀSequence”ꢀitemꢀforꢀdetailsꢀonꢀDQꢀdataꢀ
orders in these modes.
Mode Register Settings
Theꢀmodeꢀregisterꢀsetꢀcommandꢀsetsꢀtheꢀmodeꢀregister.ꢀ
Whenꢀthisꢀcommandꢀisꢀexecuted,ꢀpinsꢀA0ꢀtoꢀA9,ꢀA10,ꢀandꢀ
A11 function as data input pins for setting the register, and
thisꢀdataꢀbecomesꢀtheꢀdeviceꢀinternalꢀOPꢀcode.ꢀThisꢀOPꢀ
code has four fields as listed in the table below.
Input Pin
Field
Write Mode
BurstꢀwriteꢀorꢀsingleꢀwriteꢀmodeꢀisꢀselectedꢀbyꢀtheꢀOPꢀ
codeꢀ(A11,ꢀA10,ꢀA9)ꢀofꢀtheꢀmodeꢀregister.
ꢀA11,ꢀA10,ꢀA9,ꢀA8,ꢀA7ꢀ
ModeꢀOptions
CASꢀLatency
BurstꢀType
ꢀ
ꢀ
ꢀ
A6,ꢀA5,ꢀA4ꢀ
A3ꢀ
A2,ꢀA1,ꢀA0ꢀ
AꢀburstꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀtheꢀOPꢀcodeꢀ
(A11,ꢀA10,ꢀA9)ꢀtoꢀ(0,0,0).ꢀAꢀburstꢀwriteꢀstartsꢀonꢀtheꢀsameꢀ
cycleꢀasꢀaꢀwriteꢀcommandꢀset.ꢀTheꢀwriteꢀstartꢀaddressꢀisꢀ
specified by the column address and bank select address
at the write command set cycle.
BurstꢀLength
Noteꢀthatꢀtheꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀexecutedꢀ
onlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀ(inactive)ꢀstate.ꢀIfꢀ
theꢀModeꢀRegisterꢀSetꢀcommandꢀisꢀexecuted,ꢀtheꢀnextꢀ
commandꢀ(exceptꢀNOPꢀorꢀDeselect)ꢀcannotꢀbeꢀexecutedꢀ
until at least two clock cycles later, in order to avoid
violatingꢀtMCD.
AꢀsingleꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀOPꢀcodeꢀ(A11,ꢀ
A10,ꢀA9)ꢀtoꢀ(0,ꢀ0,1).ꢀInꢀaꢀsingleꢀwriteꢀoperation,ꢀdataꢀisꢀonlyꢀ
written to the column address and bank select address
specified by the write command set cycle without regard
to the bust length setting.
CAS Latency
Duringꢀaꢀreadꢀoperation,ꢀtheꢀbetweenꢀtheꢀexecutionꢀofꢀtheꢀ
read command and data output is stipulated as the CAS
latency.ꢀThisꢀperiodꢀcanꢀbeꢀsetꢀusingꢀtheꢀmodeꢀregisterꢀ
setꢀ command.ꢀTheꢀ optimalꢀ CAS latency is determined
by the clock frequency and device speed grade. See the
“OperatingꢀFrequencyꢀ/ꢀLatencyꢀRelationships”ꢀitemꢀꢀforꢀ
details on the relationship between the clock frequency
and the CASꢀlatency.ꢀSeeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀ
details on setting the mode register.
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
MODE REGISTER
AddressꢀBusꢀ(Ax)
ModeꢀRegisterꢀ(Mx)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ꢀWRITEꢀMODEꢀ ꢀ LTꢀꢀMODEꢀ ꢀ BTꢀ
ꢀ
BL
M2 M1 M0
Sequential Interleaved
ꢀ
BurstꢀLengthꢀ 0ꢀ
0ꢀ
0
1
0ꢀ
1
0
1ꢀ
2
4
1
2
4
8
0
0
0
1
1
8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
Reservedꢀ Reserved
Reservedꢀ Reserved
Reservedꢀ Reserved
FullꢀPageꢀ Reserved
M3
0ꢀ
Type
ꢀ
BurstꢀTypeꢀ
Sequential
1
Interleaved
M6 M5 M4 CAS Latency
ꢀ
ꢀ
LatencyꢀModeꢀ 0ꢀ
0ꢀ
0ꢀ
1
0ꢀ
1ꢀ
0
Reserved
Reserved
2
ꢀ
0ꢀ
0
0
1
1
3
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
Reserved
Reserved
Reserved
Reserved
M11
0ꢀ
0ꢀ
M10
0ꢀ
0ꢀ
M9
1ꢀ
0ꢀ
M8
0ꢀ
0ꢀ
M7
0ꢀ
0ꢀ
Write Mode
ꢀ
ꢀ
BurstꢀReadꢀ&ꢀSingleꢀWrite
BurstꢀReadꢀ&ꢀBurstꢀWrite
Note:ꢀOtherꢀvaluesꢀforꢀtheseꢀbitsꢀareꢀreserved.
Integrated Silicon Solution, Inc. — www.issi.com
23
Rev. D
08/24/09
IS42S16100E, IS45S16100E
BURST LENGTH AND COLUMN ADDRESS SEQUENCE
Column Address
A2 A1 A0
Address Sequence
Burst Length
Sequential
Interleaved
ꢀ
ꢀ
2ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
1ꢀ
0-1ꢀ
1-0ꢀ
0-1
1-0
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
2-3-4-5-6-7-0-1ꢀ
3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
FullꢀPageꢀ
(256)ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
Cn,ꢀCn+1,ꢀCn+2ꢀ
Cn+3,ꢀCn+4.....
...Cn-1(Cn+255),
Cn(Cn+256).....ꢀ
None
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:
1.ꢀTheꢀburstꢀlengthꢀinꢀfullꢀpageꢀmodeꢀisꢀ256.
24
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Rowꢀ
X0ꢀ
X1ꢀ
X2ꢀ
X3ꢀ
X4ꢀ
X5ꢀ
X6ꢀ
X7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
RowꢀAddress
RowꢀAddress
RowꢀAddress
RowꢀAddress
RowꢀAddress
RowꢀAddress
RowꢀAddress
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X8ꢀ
—ꢀ
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X9ꢀ
X10ꢀ
ꢀ
—ꢀ
0ꢀ
1ꢀ
RowꢀAddress
PrechargeꢀofꢀtheꢀSelectedꢀBankꢀ(PrechargeꢀCommand)ꢀ RowꢀAddress
PrechargeꢀofꢀBothꢀBanksꢀ(PrechargeꢀCommand)ꢀ
(Activeꢀ
Command)
ꢀ
ꢀ
ꢀ
ꢀ
X11ꢀ
ꢀ
0ꢀ
1ꢀ
Bankꢀ0ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommand)
Bankꢀ1ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommand)
Column
Y0
Y1
Y2
Y3
Y4
Y5ꢀ
Y6
Y7
Y8ꢀ
Y9ꢀ
Y10ꢀ
ꢀ
—
—
—
—
—
—ꢀ
—
—
—ꢀ
—ꢀ
0ꢀ
Column Address
Column Address
Column Address
Column Address
Column Address
ColumnꢀAddress
Column Address
Column Address
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Don’tꢀCareꢀ
Don’tꢀCare
ꢀ
ꢀ
Auto-Prechargeꢀ-ꢀDisabled
Auto-Prechargeꢀ-ꢀEnables
Bankꢀ0ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)
Bankꢀ1ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)
1ꢀ
0ꢀ
1ꢀ
Y11ꢀ
ꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
25
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Burst Read
Theꢀreadꢀcycleꢀisꢀstartedꢀbyꢀexecutingꢀtheꢀreadꢀcommand.ꢀ
Theꢀaddressꢀprovidedꢀduringꢀreadꢀcommandꢀexecutionꢀisꢀ
usedꢀasꢀtheꢀstartingꢀaddress.ꢀFirst,ꢀtheꢀdataꢀcorrespondingꢀtoꢀ
thisaddressisoutputinsynchronizationwiththeclocksignal
after the CASꢀlatencyꢀperiod.ꢀNext,ꢀdataꢀcorrespondingꢀtoꢀ
anaddressgeneratedautomaticallybythedeviceisoutput
in synchronization with the clock signal.
isꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀInꢀthisꢀcaseꢀtheꢀoutputꢀbuffersꢀ
mustꢀbeꢀsetꢀtoꢀtheꢀhighꢀimpedanceꢀstateꢀbyꢀexecutingꢀaꢀ
burst stop command.
Noteꢀ thatꢀ upperꢀ byteꢀ andꢀ lowerꢀ byteꢀ outputꢀ dataꢀ canꢀ
be masked independently under control of the signals
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tq m D )ꢀisꢀ
fixedꢀatꢀtwo,ꢀregardlessꢀofꢀtheꢀCAS latency setting, when
this function is used.
TheꢀoutputꢀbuffersꢀgoꢀtoꢀtheꢀLOWꢀimpedanceꢀstateꢀCAS
latency minus one cycle after the read command, and go
toꢀtheꢀHIGHꢀimpedanceꢀstateꢀautomaticallyꢀafterꢀtheꢀlastꢀ
data is output. However, the case where the burst length
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
UDQM
READꢀA0
tQMD=2
LDQM
DQ8-DQ15
DQ0-DQꢀ7
D
OUT A0
D
OUT A2
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
HI-Z
READꢀ(CA=A,ꢀBANKꢀ0)
DATAꢀMASKꢀ(LOWERꢀBYTE)
DATAꢀMASKꢀ(UPPERꢀBYTE)
CAS latency = 3, burst length = 4
Burst Write
Theꢀwriteꢀcycleꢀisꢀstartedꢀbyꢀexecutingꢀtheꢀcommand.ꢀTheꢀ
addressꢀprovidedꢀduringꢀwriteꢀcommandꢀexecutionꢀisꢀusedꢀ
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.
is zero, regardless of the CAS latency setting. However, a
waitꢀperiodꢀ(writeꢀrecovery:ꢀtD p l )ꢀafterꢀtheꢀlastꢀdataꢀinputꢀisꢀ
required for the device to complete the write operation.
Noteꢀthatꢀtheꢀupperꢀbyteꢀandꢀlowerꢀbyteꢀinputꢀdataꢀcanꢀ
be masked independently under control of the signals
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tD m D )ꢀisꢀ
fixedꢀatꢀzero,ꢀregardlessꢀofꢀtheꢀCAS latency setting, when
this function is used.
Next,ꢀdataꢀisꢀinputꢀinꢀotherꢀinꢀsynchronizationꢀwithꢀtheꢀ
clockꢀ signal.ꢀ Duringꢀ thisꢀ operation,ꢀ dataꢀ isꢀ writtenꢀ toꢀ
addressꢀgeneratedꢀautomaticallyꢀbyꢀtheꢀdevice.ꢀThisꢀcycleꢀ
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
caseꢀwhereꢀtheꢀburstꢀlengthꢀisꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀ
Inꢀthisꢀcaseꢀtheꢀwriteꢀcycleꢀmustꢀbeꢀterminatedꢀbyꢀexecutingꢀ
aꢀburstꢀꢀstopꢀcommand.ꢀꢀTheꢀlatencyꢀforꢀDQꢀpinꢀdataꢀinputꢀ
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
WRITE
DIN
0
DIN
1
DIN
2
DIN 3
BURSTꢀLENGTH
CAS latency = 2,3, burst length = 4
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read With Auto-Precharge
Theꢀreadꢀwithꢀauto-prechargeꢀcommandꢀfirstꢀexecutesꢀaꢀ
burst read operation and then puts the selected bank in
the precharged state automatically. After the precharge
completes,ꢀ theꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ state.ꢀ Thusꢀ thisꢀ
command performs a read command and a precharge
command in a single operation.
three, the precharge operation starts on two clock cycles
beforeꢀtheꢀlastꢀburstꢀdataꢀisꢀoutputꢀ(tp q l ꢀ=ꢀ–2).ꢀTherefore,ꢀ
the selected bank can be made active after a delay of tr p
from the start position of this precharge operation.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
Duringꢀthisꢀoperation,ꢀtheꢀdelayꢀperiodꢀ(tp q l )ꢀbetweenꢀtheꢀ
last burst data output and the start of the precharge opera-
tion differs depending on the CAS latency setting.
Theꢀauto-prechargeꢀfunctionꢀisꢀinvalidꢀifꢀtheꢀburstꢀlengthꢀ
is set to full page.
WhentheCASlatencysettingistwo, theprechargeopera-
tion starts on one clock cycle before the last burst data is
outputꢀ(tp q l ꢀ=ꢀ–1).ꢀWhenꢀtheꢀCAS latency setting is
CAS Latency
3
2
tp q l
–2
–1
CLK
COMMAND
DQ
READA 0
ACTꢀ0
t
PQL
DOUTꢀ
0
D
OUTꢀ
1
D
OUTꢀ
2
DOUTꢀ
3
tRP
PRECHARGEꢀSTART
READꢀWITHꢀAUTO-PRECHARGE
(BANKꢀ0)
CAS latency = 2, burstlength = 4
CLK
COMMAND
DQ
ACTꢀ0
READA 0
t
PQL
DOUTꢀ
0
D
OUTꢀ
1
D
OUTꢀ
2
DOUTꢀ3
t
RP
READꢀWITHꢀAUTO-PRECHARGE
(BANKꢀ0)
PRECHARGEꢀSTART
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
27
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write With Auto-Precharge
Theꢀwriteꢀwithꢀauto-prechargeꢀcommandꢀfirstꢀexecutesꢀaꢀ
burst write operation and then puts the selected bank in
the precharged state automatically. After the precharge
completesꢀ theꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ state.ꢀ Thusꢀ thisꢀ
command performs a write command and a precharge
command in a single operation.
Therefore,ꢀtheꢀselectedꢀbankꢀcanꢀbeꢀmadeꢀactiveꢀafterꢀaꢀ
delay of tD a l .
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
Theꢀauto-prechargeꢀfunctionꢀisꢀinvalidꢀifꢀtheꢀburstꢀlengthꢀ
is set to full page.
Duringꢀthisꢀoperation,ꢀtheꢀdelayꢀperiodꢀ(tD a l ) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
Theꢀdelayꢀ(tD a l )ꢀisꢀtr p ꢀplusꢀtwoꢀCLKꢀperiods.ꢀThatꢀis,ꢀtheꢀ
precharge operation starts two clock periods after the last
burst data input.
CAS Latency
3
2
tD a l ꢀ
2CLKꢀ
2CLK
+tr p
+tr p
CLK
ACTꢀ0
COMMAND
DQ
WRITEꢀA0
PRECHARGEꢀSTART
DINꢀ
0
D
INꢀ1
D
INꢀ
2
DINꢀ3
t
RP
WRITEꢀWITHꢀAUTO-PRECHARGE
(BANKꢀ0)
tDAL
CAS latency = 2, burstlength = 4
CLK
ACTꢀ0
COMMAND
DQ
WRITEꢀA0
PRECHARGEꢀSTART
DINꢀ
0
D
INꢀ1
D
INꢀ
2
DINꢀ3
t
RP
WRITEꢀWITHꢀAUTO-PRECHARGE
(BANKꢀ0)
tDAL
CAS latency = 3, burstlength = 4
28
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Interval Between Read Command
Aꢀnewꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀreadꢀcycleꢀisꢀ
in progress, i.e., before that cycle completes. When the
secondꢀreadꢀcommandꢀisꢀexecuted,ꢀafterꢀtheꢀCAS latency
haselapsed,datacorrespondingtothenewreadcommand
is output in place of the data due to the previous read
command.
Theꢀintervalꢀbetweenꢀtwoꢀreadꢀcommandꢀ(tc c D )ꢀmustꢀbeꢀ
at least one clock cycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
READꢀA0
READꢀB0
DOUT A0
DOUTꢀB0
D
OUTꢀB1
DOUTꢀB3
DOUTꢀB2
t
CCD
READꢀ(CA=A,ꢀBANKꢀ0) READꢀ(CA=B,ꢀBANKꢀ0)
CAS latency = 2, burstlength = 4
Interval Between Write Command
Aꢀnewꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀisꢀinꢀ
progress, i.e., before that cycle completes.At the point the
secondꢀwriteꢀcommandꢀisꢀexecuted,ꢀdataꢀcorrespondingꢀ
to the new write command can be input in place of the
data for the previous write command.
Theꢀintervalꢀbetweenꢀtwoꢀwriteꢀcommandsꢀ(tc c D )ꢀmustꢀbeꢀ
at least one clock cycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITEꢀA0 WRITEꢀB0
DIN A0
D
INꢀB0
D
INꢀB1
D
INꢀB2
DINꢀB3
WRITEꢀ(CA=A,ꢀBANKꢀ0) WRITEꢀꢀꢀ(CA=B,ꢀBANKꢀ0)
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
29
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Interval Between Write and Read Commands
Aꢀnewꢀreadꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀ
isꢀ inꢀ progress,ꢀ i.e.,ꢀ beforeꢀ thatꢀ cycleꢀ completes.ꢀ Dataꢀ
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
commandꢀwasꢀexecuted.ꢀTheꢀI/Onꢀpinsꢀmustꢀbeꢀplacedꢀinꢀ
theꢀHIGHꢀimpedanceꢀstateꢀatꢀleastꢀoneꢀcycleꢀbeforeꢀdataꢀ
is output during this operation.
Theꢀintervalꢀ(tc c D )ꢀbetweenꢀcommandꢀmustꢀbeꢀatꢀleastꢀ
one clock cycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITEꢀA0 READꢀB0
DIN A0
DOUTꢀB0
DOUTꢀB1
DOUTꢀB2
DOUTꢀB3
HI-Z
WRITEꢀ(CA=A,ꢀBANKꢀ0) READꢀ(CA=B,ꢀBANKꢀ0)
CAS latency = 2, burstlength = 4
CLK
t
CCD
COMMAND
DQ
WRITEꢀA0 READꢀB0
DIN A0
DOUTꢀB0
DOUTꢀB1
DOUTꢀB2
DOUTꢀB3
HI-Z
WRITEꢀ(CA=A,ꢀBANKꢀ0) READꢀ(CA=B,ꢀBANKꢀ0)
CAS latency = 3, burstlength = 4
30
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Interval Between Read and Write Commands
A read command can be interrupted and a new write
commandꢀexecutedꢀwhileꢀtheꢀreadꢀcycleꢀisꢀinꢀprogress,ꢀ
i.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀDataꢀcorrespondingꢀ
to the new write command can be input at the point
newꢀwriteꢀcommandꢀisꢀexecuted.ꢀToꢀpreventꢀcollisionꢀ
betweenꢀinputꢀandꢀoutputꢀdataꢀatꢀtheꢀDQnꢀpinsꢀduringꢀ
this operation, the
outputꢀdataꢀmustꢀbeꢀmaskedꢀusingꢀtheꢀU/LDQMꢀpins.ꢀTheꢀ
intervalꢀ(tc c D )ꢀbetweenꢀtheseꢀcommandsꢀmustꢀbeꢀatꢀleastꢀ
one clock cycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
WRITEꢀB0
COMMAND
U/LDQM
DQ
READꢀA0
HI-Z
DINꢀB0
D
INꢀB1
DINꢀB2
DINꢀB3
READꢀ(CA=A,ꢀBANKꢀ0) WRITEꢀ(CA=B,ꢀBANKꢀ0)
CAS latency = 2, 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Precharge
Read Cycle Interruption
TheꢀprechargeꢀcommandꢀsetsꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀ
toꢀtheꢀprechargedꢀstate.ꢀThisꢀcommandꢀcanꢀbeꢀexecutedꢀatꢀ
a time tr a s followingꢀtheꢀexecutionꢀofꢀanꢀactiveꢀcommandꢀ
toꢀ theꢀ sameꢀ bank.ꢀTheꢀ selectedꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ
state at a time tr p ꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀprechargeꢀ
command,ꢀandꢀanꢀactiveꢀcommandꢀcanꢀbeꢀexecutedꢀagainꢀ
for that bank.
Using the Precharge Command
Aꢀreadꢀcycleꢀcanꢀbeꢀinterruptedꢀbyꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀcommandꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀTheꢀ
delayꢀtimeꢀ(tr q l )ꢀfromꢀtheꢀexecutionꢀofꢀtheꢀprechargeꢀ
command to the completion of the burst output is the
clock cycle of CAS latency.
IfꢀpinꢀA10ꢀisꢀlowꢀwhenꢀthisꢀcommandꢀisꢀexecuted,ꢀtheꢀbankꢀ
selected by pin A11 will be precharged, and if pin A10 is
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprechargedꢀatꢀtheꢀsameꢀtime.ꢀThisꢀ
input to pin A11 is ignored in the latter case.
CAS Latency
3
2
tr q l
3
2
CLK
tRQL
PREꢀ0
COMMAND
DQ
READꢀA0
DOUT A0
DOUT A1
DOUT A2
HI-Zꢀ
READꢀ(CA=A,ꢀBANKꢀ0)
PRECHARGEꢀ(BANKꢀ0)
CAS latency = 2, burstlength = 4
CLK
t
RQL
PREꢀ0
COMMAND
DQ
READꢀA0
DOUT A0
DOUT A1
DOUT A2
HI-Zꢀ
READꢀ(CA=A,ꢀBANKꢀ0)
PRECHARGEꢀ(BANKꢀ0)
CAS latency = 3, burstlength = 4
32
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle Interruption Using the
Precharge Command
Aꢀwriteꢀcycleꢀcanꢀbeꢀinterruptedꢀbyꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀ commandꢀ beforeꢀ thatꢀ cycleꢀ completes.ꢀTheꢀ
delayꢀtimeꢀ(tw D l )ꢀfromꢀtheꢀprechargeꢀcommandꢀtoꢀtheꢀpointꢀ
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
Inversely, to write all the burst data to the device, the
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀafterꢀtheꢀwriteꢀ
dataꢀrecoveryꢀperiodꢀ(tD p l )ꢀhasꢀelapsed.ꢀTherefore,ꢀtheꢀ
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀtwoꢀclockꢀcyclesꢀ
after the input of the last burst data item.
Toꢀinhibitꢀinvalidꢀwrite,ꢀtheꢀDQMꢀsignalꢀmustꢀbeꢀassertedꢀ
HIGHꢀwithꢀtheꢀprechargeꢀcommand.
CAS Latency
3
2
tw D l
0
0
Thisꢀprechargeꢀcommandꢀandꢀburstꢀwriteꢀcommandꢀmustꢀ
beofthesamebank, otherwiseitisnotprechargeinterrupt
but only another bank precharge of dual bank operation.
tD p l
2
2
CLK
tWDL=0
PREꢀ0
COMMAND
WRITEꢀA0
DQM
DQ
DIN A0
DIN A1
DIN A2
DIN A3
MASKEDꢀBYꢀDQM
PRECHARGEꢀ(BANKꢀ0)
WRITEꢀ(CA=A,ꢀBANKꢀ0)
CAS latency = 2, burstlength = 4
CLK
t
DPL
COMMAND
DQ
WRITEꢀA0
PREꢀ0
DIN A0
D
IN
A1 DIN A2
DIN A3
WRITEꢀ(CA=A,ꢀBANKꢀ0)
PRECHARGEꢀ(BANKꢀ0)
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
33
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
TheꢀIS42/4516100Eꢀcanꢀoutputꢀdataꢀcontinuouslyꢀfromꢀ
theꢀ burstꢀ startꢀ addressꢀ (a)ꢀ toꢀ locationꢀ a+255ꢀ duringꢀ aꢀ
read cycle in which the burst length is set to full page.
Theꢀ IS42/4516100Eꢀ repeatsꢀ theꢀ operationꢀ startingꢀ atꢀ
theꢀ256thꢀcycleꢀwithꢀtheꢀdataꢀoutputꢀreturningꢀtoꢀlocationꢀ
(a)ꢀandꢀcontinuingꢀwithꢀa+1,ꢀa+2,ꢀa+3,ꢀetc.ꢀAꢀburstꢀstopꢀ
commandꢀ mustꢀ beꢀ executedꢀ toꢀ terminateꢀ thisꢀ cycle.ꢀ Aꢀ
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀwithinꢀtheꢀACTꢀ
toꢀPREꢀcommandꢀperiodꢀ(tr a s ꢀmax.)ꢀfollowingꢀtheꢀburstꢀ
stop command.
Afterꢀtheꢀperiodꢀ(tr b D )ꢀrequiredꢀforꢀburstꢀdataꢀoutputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀimpedanceꢀ
state.ꢀThisꢀperiodꢀ(tr b D )ꢀisꢀtwoꢀclockꢀcycleꢀwhenꢀtheꢀ
CAS latency is two and three clock cycle when the CAS
latency is three.
CAS Latency
3
2
tr b D
3
2
CLK
tRBD
BST
COMMAND
DQ
READꢀA0
D
OUT A0
DOUT A0
D
OUT A1
D
OUT A2
DOUT A3
HI-Z
BURSTꢀSTOP
READꢀ(CA=A,ꢀBANKꢀ0)
CAS latency = 2, burstlength = 4
CLK
t
RBD
BST
COMMAND
DQ
READꢀA0
D
OUT A0
D
OUT A0
D
OUT A2
D
OUT A3
D
OUT A1
HI-Z
ꢀREADꢀꢀ(CA=A,ꢀBANKꢀ0)
BURSTꢀSTOP
CAS latency = 3, burstlength = 4
34
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
mustꢀbeꢀexecutedꢀwithinꢀtheꢀACTꢀtoꢀPREꢀcommandꢀ
periodꢀ(tr a s ꢀmax.)ꢀfollowingꢀtheꢀburstꢀstopꢀcommand.ꢀ
Afterꢀtheꢀperiodꢀ(tw b D )ꢀrequiredꢀforꢀburstꢀdataꢀꢀinputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀwriteꢀcycleꢀterminates.ꢀThisꢀperiodꢀ
(tw b D )ꢀisꢀzeroꢀclockꢀcycles,ꢀregardlessꢀofꢀtheꢀCAS
latency.
TheꢀIS42/4516100Eꢀcanꢀinputꢀdataꢀcontinuouslyꢀfromꢀ
theꢀburstꢀstartꢀaddressꢀ(a)ꢀtoꢀlocationꢀa+255ꢀduringꢀaꢀ
write cycle in which the burst length is set to full page.
TheꢀIS42/4516100Eꢀrepeatsꢀtheꢀoperationꢀstartingꢀatꢀ
theꢀ256thꢀcycleꢀwithꢀdataꢀinputꢀreturningꢀtoꢀlocationꢀ(a)ꢀ
and continuing with a+1, a+2, a+3, etc. A burst stop
commandꢀmustꢀbeꢀexecutedꢀtoꢀterminateꢀthisꢀcycle.ꢀAꢀ
precharge command
CLK
t
WBD=0
BST
INVALIDꢀDATA
tRP
PREꢀ0
COMMAND
DQ
WRITEꢀA0
DIN A0
DIN A1
DIN
A
DIN A1
DIN A2
READꢀ(CA=A,ꢀBANKꢀ0)
BURSTꢀSTOP PRECHARGEꢀ(BANKꢀ0)
Don'tꢀCare
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
output control operates independently on a byte basis
withꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀoutputꢀ(pinsꢀ
DQ8-DQ15)ꢀ andꢀ theꢀ LDQMꢀ pinꢀ controllingꢀ lowerꢀ byteꢀ
outputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
Burstꢀdataꢀoutputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(masked)ꢀ
duringꢀaꢀreadꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀofꢀ
the CASꢀlatency,ꢀtwoꢀclockꢀcyclesꢀ(tq m D )ꢀafterꢀoneꢀofꢀtheꢀ
U/LDQMꢀpinsꢀgoesꢀHIGH,ꢀtheꢀcorrespondingꢀoutputsꢀgoꢀ
toꢀtheꢀHIGHꢀimpedanceꢀstate.ꢀSubsequently,ꢀtheꢀoutputsꢀ
are maintained in the high impedance state as long as
thatꢀU/LDQMꢀpinꢀremainsꢀHIGH.ꢀWhenꢀtheꢀU/LDQMꢀpinꢀ
goesꢀLOW,ꢀoutputꢀisꢀresumedꢀatꢀaꢀtimeꢀtq m D ꢀlater.ꢀThisꢀ
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀoutputꢀbuffersꢀ
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CLK
COMMAND
UDQM
READꢀA0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQꢀ7
D
OUT A0
D
OUT A2
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
HI-Z
READꢀ(CA=A,ꢀBANKꢀ0)
DATAꢀMASKꢀ(LOWERꢀBYTE)
DATAꢀMASKꢀ(UPPERꢀBYTE)
CAS latency = 2, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
35
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burstꢀdataꢀinputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(mutedꢀ)ꢀ
duringꢀaꢀwriteꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀ
of the CASꢀlatency,ꢀasꢀsoonꢀasꢀoneꢀofꢀtheꢀU/LDQMꢀpinsꢀ
goesꢀHIGH,ꢀtheꢀcorrespondingꢀexternallyꢀappliedꢀinputꢀ
data will no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
mutedꢀasꢀlongꢀasꢀthatꢀU/LDQMꢀpinꢀremainsꢀHIGH.
thatꢀpinꢀisꢀdroppedꢀtoꢀLOWꢀandꢀdataꢀwillꢀbeꢀwrittenꢀtoꢀtheꢀ
device.ꢀThisꢀinputꢀcontrolꢀoperatesꢀindependentlyꢀonꢀaꢀbyteꢀ
basisꢀwithꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀinputꢀ(pinꢀ
DQ8ꢀtoꢀDQ15)ꢀandꢀtheꢀLDQMꢀpinꢀcontrollingꢀtheꢀlowerꢀ
byteꢀinputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀinputꢀbuffersꢀ
only, the cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
TheꢀIS42/4516100Eꢀwillꢀrevertꢀtoꢀacceptingꢀinputꢀasꢀsoonꢀ
as
CLK
COMMAND
UDQM
WRITEꢀA0
t
DMD=0
LDQM
DQ8-DQ15
DQ0-DQ7
DIN A1
D
IN A3
DIN A2
D
IN A0
DIN A3
WRITEꢀ(CA=A,ꢀBANKꢀ0)
DATAꢀMASKꢀ(LOWERꢀBYTE)
Don'tꢀCare
DATAꢀMASKꢀ(UPPERꢀBYTE)
CAS latency = 2, burstlength = 4
Burst Read and Single Write
Theꢀburstꢀreadꢀandꢀsingleꢀwriteꢀmodeꢀisꢀsetꢀupꢀusingꢀtheꢀ
modeꢀregisterꢀsetꢀcommand.ꢀDuringꢀthisꢀoperation,ꢀtheꢀburstꢀ
readcycleoperatesnormally,butthewritecycleonlywrites
aꢀsingleꢀdataꢀitemꢀforꢀeachꢀwriteꢀcycle.ꢀTheꢀCAS latency
andꢀDQMꢀlatencyꢀareꢀtheꢀsameꢀasꢀinꢀnormalꢀmode.
CLK
COMMAND
DQ
WRITEꢀA0
DIN A0
WRITEꢀ(CA=A,ꢀBANKꢀ0)
CAS latency = 2, 3
36
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state,
theꢀbankꢀcanꢀbeꢀactivatedꢀbyꢀexecutingꢀtheꢀactiveꢀ
command. If the other bank is in the idle state at that
time,ꢀtheꢀactiveꢀcommandꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbankꢀ
after the period tr r D has elapsed. At that point both
banks will be in the active state. When a bank active
commandꢀhasꢀbeenꢀexecuted,ꢀaꢀprechargeꢀcommandꢀ
mustꢀbeꢀexecutedꢀforꢀthatꢀbankꢀwithinꢀtheꢀACTꢀtoꢀPREꢀ
commandꢀperiodꢀ(tr a s ꢀmax).ꢀAlsoꢀnoteꢀthatꢀaꢀprechargeꢀ
commandꢀcannotꢀbeꢀexecutedꢀforꢀanꢀactiveꢀbankꢀbeforeꢀ
tr a s ꢀ(min)ꢀhasꢀelapsed.
Afterꢀ aꢀ bankꢀ activeꢀ commandꢀ hasꢀ beenꢀ executedꢀ andꢀ
theꢀtrcdꢀperiodꢀhasꢀelapsed,ꢀreadꢀwriteꢀ(includingꢀauto-
precharge)ꢀcommandsꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbank.
CLK
tRRD
COMMAND
ACTꢀ0
ACTꢀ1
BANKꢀACTIVEꢀ(BANKꢀ0)
BANKꢀACTIVEꢀ(BANKꢀ1)
CLK
COMMAND
tRCD
ACTꢀ0
READꢀ0
BANKꢀACTIVEꢀ(BANKꢀ0)
BANKꢀACTIVEꢀ(BANKꢀ0)
CAS latency = 3
Clock Suspend
WhenꢀtheꢀCKEꢀpinꢀisꢀdroppedꢀfromꢀHIGHꢀtoꢀLOWꢀduringꢀ
aꢀ readꢀ orꢀ writeꢀ cycle,ꢀ theꢀ IS42/4516100Eꢀ entersꢀ clockꢀ
suspendꢀmodeꢀonꢀtheꢀnextꢀCLKꢀrisingꢀedge.ꢀThisꢀcommandꢀ
reduces the device power dissipation by stopping the
device internal clock. Clock suspend mode continues as
longꢀasꢀtheꢀCKEꢀpinꢀremainsꢀlow.ꢀInꢀthisꢀstate,ꢀallꢀinputsꢀ
otherꢀthanꢀCKEꢀpinꢀareꢀinvalidꢀandꢀnoꢀotherꢀcommandsꢀ
canꢀ beꢀ executed.ꢀ Also,ꢀ theꢀ deviceꢀ internalꢀ statesꢀ areꢀ
maintained.ꢀWhenꢀtheꢀCKEꢀpinꢀgoesꢀfromꢀLOWꢀtoꢀHIGHꢀ
clockꢀsuspendꢀmodeꢀisꢀterminatedꢀonꢀtheꢀnextꢀCLKꢀrisingꢀ
edge and device operation resumes.
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀrecoveryꢀ
periodꢀ(tc k a )ꢀhasꢀelapsed.
Sincethiscommanddiffersfromtheself-refreshcommand
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tref).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀclockꢀsuspendꢀmodeꢀcanꢀbeꢀheldꢀ
is just under the refresh cycle time.
CLK
CKE
COMMAND
DQ
READꢀ0
D
OUT
0
DOUT
1
DOUT
2
DOUT 3
READꢀ(BANKꢀ0)
CLOCKꢀSUSPEND
CAS latency = 2, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
37
Rev. D
08/24/09
IS42S16100E, IS45S16100E
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0
T1
T2
T3
T10
T17ꢀꢀꢀ
T18
T19
T20
CLK
tCHI
tCK
tCL
HIGH
CKE
t
CS
tCH
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
t
WE
t
AS
tAH
ROW
CODE
CODE
CODE
A0-A9
A10
t
t
AS
AS
tAH
tAS
tAH
ROW
BANKꢀ0ꢀ&ꢀ1
tAH
BANKꢀ1
A11
BANKꢀ0ꢀ
HIGH
DQM
DQ
WAITꢀTIME
t
RAS
t
MCD
t
RP
tRC
tRC
T=100ꢀµs
t
RC
Undefined
Don'tꢀCare
CAS latency = 2, 3
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Power-Down Mode Cycle
T0
T1
T2
T3
Tnꢀꢀ
Tn+1
Tn+2
Tn+3
CLK
t
CHI
t
CKH
tCKS
t
CK
tCL
tCKS
CKE
t
CKA
t
CKA
tCS
tCH
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
ROW
A0-A9
A10
tAS
tAH
BANKꢀ0ꢀ&ꢀ1
BANKꢀ0ꢀORꢀ1
BANKꢀ1
ROW
BANKꢀ1
A11
BANKꢀ0ꢀ
BANKꢀ0
DQM
DQ
EXIT
t
RAS
tRP
POWERꢀDOWNꢀMODE
POWERꢀDOWNꢀMODE
tRC
<
PRE
>
<SBY>
<ACT>
Undefined
Don'tꢀCare
CAS latency = 2, 3
Integrated Silicon Solution, Inc. — www.issi.com
39
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Auto-Refresh Cycle
T0
T1
T2
T3
Tl
Tm
Tn
Tn+1
CLK
t
CHI
t
CK
tCKS
tCL
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
ROW
A0-A9
A10
t
AS
tAH
ROW
BANKꢀ0ꢀ&ꢀ1
BANKꢀ1
A11
BANKꢀ0ꢀ
DQM
DQ
t
RC
t
RAS
RC
tRP
t
RC
tRC
t
Undefined
Don'tꢀCare
CAS latency = 2, 3
40
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Self-Refresh Cycle
T0
T1
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
t
CHI
t
CKS
tCK
t
CKS
tCL
CKE
CS
t
CKA
t
CS
t
CH
t
CS
tCH
RAS
t
CS
CS
tCH
CAS
t
t
CH
WE
A0-A9
A10
t
AS
tAH
BANKꢀ0ꢀ&ꢀ1
A11
DQM
DQ
t
XSR
SELFꢀREFRESHꢀMODE
t
RC
t
RP
Undefined
Don'tꢀCare
CAS latency = 2, 3
Nꢀtꢂ:
1: a8, a9 = dꢀn’t cꢄrꢂ.
2. Sꢂlꢇ-Rꢂꢇrꢂsh Mꢀꢃꢂ is nꢀt suꢁꢁꢀrtꢂꢃ ꢇꢀr a2 ꢈrꢄꢃꢂ with Ta > 85ꢀc.
Integrated Silicon Solution, Inc. — www.issi.com
41
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
NOꢀPRE
ROW
t
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ1
BANKꢀ0
A11
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
RAS
t
RCD
t
CAC
tRQL
t
t
RAS
RC
t
RP
t
RC
t
<
PRE>
<
ACT>
<ACT
>
<READ>
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
42
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
t
WE
(1)
t
AS
AS
t
AH
COLUMNꢀm
ROW
ROW
ROW
A0-A9
A10
t
t
AH
AH
AUTOꢀPRE
ROW
t
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
A11
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
tRCD
tRCD
tCAC
tPQL
t
RAS
t
RAS
RC
tRP
t
RC
t
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
43
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263ꢀꢀ
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ0
t
AS
BANKꢀ0
BANKꢀ0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
tRCD
t
CAC
t
RBD
(BANKꢀ0)
t
RP
t
RAS
(BANKꢀ0)
t
RC
(BANKꢀ0)
BST
PREꢀ0
ACTꢀ0
READ0
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = full page
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
44
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
ROW
COLUMN
A0-A9
AUTOꢀPRE
AUTOꢀPRE
t
t
t
AH
AH
A10
A11
NOꢀPREꢀ
BANKꢀ0ꢀORꢀ1
BANKꢀ0ꢀORꢀ1
BANKꢀ1
NOꢀPRE
t
AS
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
BANKꢀ1
BANKꢀ1
tCH
tCS
tQMD
DQM
t
AC
tAC
t
AC
t
AC
tOH
tOH
tOH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
DQ
t
LZ
t
LZ
t
HZ
tHZ
t
RRD
(BANKꢀ0ꢀTOꢀ1)
RCD
(BANKꢀ0)
t
t
CAC
t
CAC
t
RCD
(BANKꢀ1)
t
RCD
(BANKꢀ0)
RAS
(BANKꢀ0)
(BANKꢀ1)
(BANKꢀ1)
t
RP
(BANKꢀ0)
t
t
RAS
(BANKꢀ0)
t
RC
t
RC
(BANKꢀ0)
(BANKꢀ0)
t
RAS
t
RP
(BANKꢀ1)
(BANK1)
t
RC
(BANKꢀ1)
<
ACTꢀ0>
<ACT1>
<
READꢀ0
READAꢀ0
>
<
READꢀ1
READAꢀ1>
>
<
PREꢀ0
>
<
ACTꢀ0>
<PREꢀ1>
<
>
<
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
45
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle
T0
T1
T2
T3
T4
T5
T6ꢀꢀ
T7ꢀ
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
ROW
ROW
COLUMNꢀmꢀ
ROW
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
AS
t
t
AH
AH
NOꢀPRE
ROW
A10
A11
tAS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
tRPꢀ
t
t
t
t
<
PRE
>
<
ACT>
<WRIT
>
<ACT>
PALL
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
46
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6ꢀꢀ
T7ꢀ
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMNꢀmꢀ
ROW
A0-A9
t
AS
t
t
AH
AH
ROW
AUTOꢀPRE
A10
A11
tAS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0
tCS
tCH
DQM
DQ
t
DH
t
DS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
tRPꢀ
t
t
t
t
Undefined
Don'tꢀCare
CAS latency = 2, burstlength = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
47
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262ꢀꢀ
CLK
t
CHI
tCKS
tCL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
t
AH
(1)
COLUMNꢀm
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
BANKꢀ0ꢀORꢀ1
BANKꢀ0
NOꢀPRE
t
t
AS
BANKꢀ0
BANKꢀ0
t
CH
tCS
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN 0m+2
D
IN 0m
D
IN 0m-1
D
INꢀ0m
D
IN 0m+1
tDPL
tRCD
t
RAS
RC
tRP
t
BST
PREꢀ0
Undefined
Don'tꢀCare
CAS latency = 2, burst length = full page
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Ping-Pong Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
t
AUTOꢀPRE
AUTOꢀPRE
t
AH
AH
ROW
A10
A11
NOꢀPREꢀ
BANKꢀ0ꢀORꢀ1
NOꢀPRE
t
t
AS
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
BANKꢀ1
BANKꢀ1
tCH
t
CS
DQM
DQ
t
DS
t
DS
tDS
tDS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANKꢀ0ꢀTOꢀ1)
RCD
(BANKꢀ0)
tDPL
t
DPL
t
t
RCD
tRCD
(BANKꢀ1)
(BANKꢀ0)
t
RP
t
RAS
t
RAS
(BANKꢀ0)
(BANKꢀ0)
(BANKꢀ0)
t
RC
t
RC
(BANKꢀ0)
(BANKꢀ0)
t
RAS
(BANKꢀ1)
t
RC
(BANKꢀ1)
<
ACTꢀ0>
<ACTꢀ1>
<
WRITꢀ0
WRITAꢀ0
>
<
WRITꢀ1
WRITAꢀ1
>
<PREꢀ0
>
<ACTꢀ0>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
49
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
BANKꢀ0ꢀANDꢀ1
AUTOꢀPRE
tAH
tAH
NOꢀPRE
NOꢀPRE
A10
A11
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ1
BANKꢀ1
tAS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
tCH
tCS
tQMD
DQM
DQ
tAC
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUTꢀo
D
OUT o+1
tLZ
tHZ
tRCD
tRAS
tCAC
tCAC
tCAC
tRQL
tRP
tRC
<ACT>
<READ>
<READ>
<READ>
<PRE>
READA
PALL
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
NOꢀPRE
A10
A11
NOꢀPRE
NOꢀPREꢀ
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0ꢀ
t
CH
tQMD
t
CS
tQMD
DQM
DQ
tAC
t
AC
t
AC
tAC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUTꢀ
o
D
OUT o+1
t
LZ
tLZ
tHZ
tHZ
t
RCD
tCAC
tCAC
tCAC
t
t
RQL
RP
tRAS
tRC
<
ACT>
<READ
>
<
MASK>
<
READ,ꢀENB
>
<
PRE
>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
51
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
BANKꢀ0ꢀANDꢀ1
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
NOꢀPRE
A10
A11
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ1
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
t
CH
tCS
DQM
DQ
t
DH
t
DS
tDS
t
DH
tDH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
D
IN
m
D
INꢀn
D
INꢀn+1
D
INꢀo
D
INꢀo+1
D
IN m+1
tRCD
t
DPL
t
RAS
tRP
t
RC
<ACT>
<WRIT
>
<
WRIT>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
52
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
t
t
AS
AS
tAH
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ1ORꢀ0
AUTOꢀPRE
t
AH
AH
NOꢀPRE
NOꢀPRE
A10
A11
NOꢀPRE
t
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
t
CS
tCH
DQM
DQ
t
DH
t
DH
tDH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDS
D
INꢀn
D
INꢀo
D
IN
m
D
INꢀo+1
D
IN m+1
tRCD
tDPL
tRAS
tRP
tRC
<
ACT>
<
WRIT>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
53
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
tCHI
tCKS
tCKS
tCKH
tCL
tCK
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
tAH
tAH
ROW
A10
A11
NOꢀPRE
BANKꢀ1
tAS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ0
tCH
tAC
tCS
tQMD
DQM
DQ
tAC
tOH
tOH
D
OUT
m
DOUT m+1
tLZ
tHZ
tRCD
tRAS
tCAC
tRAS
tRC
tRP
tRC
<SPND>
<SPND>
<PRE>
<ACTꢀ0>
<READ>
READꢀA
<ACTꢀ>
<PALL>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
t
CHI
t
CKS
tCKS
CL
tCKH
t
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ0
t
CH
tCS
DQM
DQ
t
DS
tDS
tDH
tDH
DIN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<
ACT>
<
WRIT,ꢀSPND
>
<ACTꢀ>
WRITA,ꢀSPND
PALL
Undefined
CAS latency = 2, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
55
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
t
CHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
(1)
COLUMNꢀm
COLUMNꢀn
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ0
NOꢀPRE
BANKꢀ0
BANKꢀ1
t
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
t
CAC
t
RQL
RP
tCAC
t
RCD
RAS
RC
t
RAS
RC
t
t
t
t
<PREꢀ0
>
<
READ
>
<
ACTꢀ0>
<
READꢀ0
>
<ACTꢀ>
READA
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
(1)
COLUMNꢀm
COLUMNꢀn
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ0
NOꢀPRE
BANKꢀ0
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ0
tCS
tCH
BANKꢀ0
CS
tCS
tCH
t
DQM
DQ
t
DH
DS
t
DH
DS
t
DH
tDH
tDS
t
t
tDS
DIN 0m+2
D
IN 0m+1
D
IN 0m
D
IN 0n
t
RCD
t
RCD
RAS
RC
t
t
RAS
t
tRP
RC
t
<
PREꢀ0>
<
WRIT
>
<ACTꢀ0
>
<
WRITꢀ0
>
<ACTꢀ>
WRITA
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
57
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMNꢀm
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ0
BANKꢀ1ꢀ
BANKꢀ1ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
t
CH
t
CS
t
QMD
UDQM
t
QMD
tCS
tCH
LDQM
t
t
AC
t
HZ
t
AC
t
AC
t
OH
tOH
t
LZ
t
OH
tLZ
DQ8-15
D
OUT
m
D
OUT m+2
DOUT m+3
AC
t
t
AC
t
OH
tOH
LZ
D
OUT m+1
DOUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE>
<
ACT>
<
READ
READA
>
<MASKU
>
<ACT>
<
ENBU,ꢀMASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
t
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ0
BANKꢀ1ꢀ
BANKꢀ1ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCH
tCS
UDQM
tCS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
tDH
t
DH
t
DS
DH
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
DIN m+3
t
RCD
t
DPL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<ENB>
<
>
<
>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
59
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
(1)
t
t
AS
AS
tAH
COLUMNꢀm
COLUMNꢀn
ROW
ROW
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
A10
A11
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
DS
t
OH
t
OH
t
OH
tOH
t
DH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
DIN
n
t
LZ
t
HZ
t
RCD
t
CAC
tDPL
t
RAS
RC
tRP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<ACT
>
<READ>
Undefined
Don'tꢀCare
CAS latency = 2, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
T11ꢀꢀꢀꢀꢀꢀꢀ
T12ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
NOꢀPRE
ROW
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ1
BANKꢀ0
A11
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCH
tCS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tHZ
t
RCD
tRCD
t
CAC
t
RQL
t
RAS
t
RAS
RC
tRP
tRC
t
<
PRE>
<
ACT>
<READ>
<ACT>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
61
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
T11ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
T12
CLK
tCHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN
ROW
ROW
ROW
A0-A9
A10
AUTOꢀPRE
t
t
AH
AH
ROW
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ1ꢀ
A11
BANKꢀ0
BANKꢀ0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
tLZ
t
HZ
tRCD
tRCD
tCAC
t
PQL
RP
t
RAS
t
RAS
RC
t
t
RC
t
Undefined
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
62
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265ꢀꢀ
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN
ROW
ROW
A0-A9
t
AH
AH
NOꢀPRE
A10
A11
BANKꢀ0ꢀORꢀ1
BANKꢀ0
t
t
AS
BANKꢀ0
BANKꢀ0
t
CH
t
CS
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
(BANKꢀ0)
RAS
(BANKꢀ0)
t
CAC
tRBD
(BANKꢀ0)
t
RP
t
(BANKꢀ0)
t
RC
(BANKꢀ0)
BST
PREꢀ0
ACTꢀ0
READ0
Undefined
Don'tꢀCare
CAS latency = 3, burst length = full page
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
63
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Ping Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
T11
T12ꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
COLUMN
COLUMN
ROW
A0-A9
AUTOꢀPRE
AUTOꢀPRE
t
t
AH
AH
ROW
A10
A11
NOꢀPREꢀ
BANKꢀ0ꢀORꢀ1
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ0
t
AS
BANKꢀ0ꢀ
BANKꢀ0
BANKꢀ0
BANK1
BANKꢀ1
BANKꢀ1
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
t
CAC
t
RCD
t
HZ
t
RRD
(BANKꢀ0ꢀTOꢀ1)
RCD
(BANKꢀ0)
(BANKꢀ1)
(BANKꢀ1)
t
CAC
t
t
RQL
(BANKꢀ0)
RP
(BANKꢀ0)
t
RCD
(BANKꢀ0)
RAS
(BANKꢀ0)
(BANKꢀ0)
t
t
t
RAS
(BANKꢀ0)
t
RC
t
RC
(BANKꢀ0)
(BANKꢀ0)
t
RAS
t
RP
(BANKꢀ1)
(BANK1)
t
RC
(BANKꢀ1)
<ACTꢀ0>
<
ACT1>
<
READꢀ0
READAꢀ0
>
<
READꢀ1
READAꢀ1>
>
<
PREꢀ0>
<
PREꢀ1>
<
ACTꢀ0>
<
>
<
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
64
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle
T12ꢀꢀꢀꢀꢀꢀꢀ
T0
T1
T2
T3
T4
T5
T6ꢀꢀ
T7ꢀ
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀꢀ
T11ꢀꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
t
CK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
ROW
ROW
COLUMNꢀ
ROW
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
AS
t
AH
AH
NOꢀPRE
ROW
A10
A11
t
tAS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ0
t
CS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
t
DS
t
DH
tDS
tDH
D
IN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
t
RPꢀ
t
t
t
t
<
PRE
>
<ACT>
<
WRIT>
<ACT>
PALL
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
65
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Auto-Precharge
T11
T12ꢀꢀꢀꢀꢀꢀꢀ
T0
T1
T2
T3
T4
T5
T6ꢀꢀ
T7ꢀ
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMNꢀ
ROW
A0-A9
A10
AUTOꢀPRE
t
AS
t
t
AH
AH
ROW
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
A11
BANKꢀ0
t
CS
t
tCH
DQM
DQ
t
DH
tDS
DS
t
DH
t
DS
t
DH
t
DS
tDH
DIN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
t
RPꢀ
t
t
t
t
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
66
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262ꢀꢀꢀ
T263
T264ꢀꢀ
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN
NOꢀPRE
BANKꢀ0
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
BANKꢀ0ꢀORꢀ1
BANKꢀ0
t
AS
BANKꢀ0
t
CH
tCS
DQM
DQ
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
D
IN 0m
D
IN 0m+2
D
INꢀ0m-1
DIN 0m
D
IN 0m+1
t
RCD
tDPL
t
RAS
RC
tRP
t
BST
PREꢀ0
ACTꢀ0
WRIT0
Undefined
Don'tꢀCare
CAS latency = 3, burst length = full page
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
67
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
T11
T12ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
ROW
ROW
COLUMN
COLUMN
A0-A9
AUTOꢀPRE
AUTOꢀPRE
t
AH
AH
A10
A11
NOꢀPREꢀ
NOꢀPRE
BANKꢀ0ꢀORꢀ1
BANKꢀ0
t
t
AS
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ1
BANKꢀ1
t
CH
tCS
DQM
DQ
t
DS
tDS
tDS
t
DS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANKꢀ0ꢀTOꢀ1)
RCD
(BANKꢀ0)
t
DPL
tDPL
(BANKꢀ0)
t
t
RCD
t
RCD
RAS
RC
(BANKꢀ1)
t
RP
t
RAS
t
(BANKꢀ0)
(BANKꢀ0)
t
RC
t
(BANKꢀ0)
tRAS
(BANKꢀ1)
t
RC
(BANKꢀ1)
<ACTꢀ0
>
<
ACTꢀ1>
<
WRITꢀ0
WRITAꢀ0
>
<
WRITꢀ1
WRITAꢀ1
>
<PREꢀ0
>
<ACTꢀ0>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
68
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
T11
T12ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
AUTOꢀPRE
t
AH
AH
NOꢀPRE
NOꢀPRE
NOꢀPRE
BANKꢀ1
t
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
A11
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0
t
CH
tCS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUTꢀ
o
D
OUTꢀo+1
t
CAC
t
HZ
t
CAC
t
RCD
t
CAC
tRQL
t
RAS
t
RP
tRC
<
ACT>
<
READ>
<
READ>
<
READ
>
<
PRE>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
69
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode; Data Masking
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
AH
AH
NOꢀPRE
NOꢀPRE
NOꢀPRE
t
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ1
BANKꢀ0
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
A11
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
t
CH
tQMD
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
AC
t
OH
tLZ
t
OH
m
t
OH
t
OH
t
OH
D
OUT
D
OUT m+1
D
OUT
n
D
OUTꢀ
o
D
OUTꢀo+1
t
HZ
t
CAC
t
CAC
tRCD
t
CAC
t
RQL
t
RAS
tRP
t
RC
<ACT>
<READ
>
<
READ>
<
READ,ꢀMASK
>
<ENB>
<
PRE
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
70
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
T11
T12ꢀꢀꢀꢀ
CLK
t
CHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
t
AH
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
NOꢀPRE
A10
A11
NOꢀPRE
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ0ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
t
CH
t
CS
t
DQM
DQ
tDH
t
DS
t
DH
tDH
DS
t
DH
tDS
t
DH
tDS
tDS
DIN
m
DINꢀn
DINꢀo
D
INꢀo+1
DIN m+1
tRCD
t
DPL
tRAS
tRP
t
RC
<
ACT>
<
WRIT>
<WRIT
>
<MASK
>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
71
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
T11ꢀꢀꢀꢀꢀꢀꢀ
T12ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
t
WE
t
AS
AS
t
AH
(1)
(1)
(1)
COLUMNꢀm
ROW
ROW
COLUMNꢀn
COLUMNꢀo
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ1ORꢀ0
t
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
NOꢀPRE
NOꢀPRE
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ0ꢀ
BANKꢀ1
A11
BANKꢀ0ꢀ
BANKꢀ0ꢀ
BANKꢀ0ꢀ
tCS
tCH
DQM
DQ
t
DH
t
DH
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
t
DS
D
INꢀn
D
INꢀo
D
IN
m
D
INꢀo+1
D
IN m+1
tRCD
t
DPL
tRAS
t
RP
t
RC
<
ACT>
<WRIT
>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
72
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11ꢀ
T12ꢀ
CLK
t
CHI
tCKS
t
CKS
tCKH
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
t
AH
(1)
COLUMNꢀm
ROW
ROW
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
t
AH
AH
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
A11
tCS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
OH
t
OH
D
OUT
m
D
OUT m+1
t
LZ
t
HZ
t
RCD
t
CAC
t
RAS
RC
tRP
t
<
SPND>
<
SPND>
<
PRE
PALL
>
<ACT>
<
READ
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
73
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Clock Suspend
T11
T12ꢀ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
tCHI
t
CKS
tCKS
tCKH
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
t
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
AH
AH
ROW
NOꢀPRE
BANKꢀ1
t
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
A11
BANKꢀ0
t
CH
t
CS
DQM
DQ
tDS
tDS
tDH
tDH
D
IN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<ACT
>
<
WRIT,ꢀSPND
>
<ACTꢀ>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
74
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Precharge Termination
T11
T12ꢀ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
tCHI
t
CKS
tCL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
t
t
t
AH
AH
ROW
A10
A11
BANKꢀ0ꢀORꢀ1
BANKꢀ0
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ0
BANKꢀ0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
t
LZ
t
RCD
t
CAC
t
RQL
RP
t
RCD
RAS
RP
tRAS
RC
t
t
t
t
<
PREꢀ0>
ACTꢀ0
READꢀ0
ACT
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
75
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Precharge Termination
T11
T12ꢀ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀ
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
A10
t
AH
AH
ROW
BANKꢀ0ꢀORꢀ1
BANKꢀ0
NOꢀPRE
t
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ0
A11
t
CS
BANKꢀ0
t
CS
t
CH
t
CH
DQM
DQ
t
DH
DS
t
DH
DS
tDH
tDS
t
t
DIN 0m+2
D
IN 0m+1
D
IN 0m
tRCD
tRCD
t
RAS
RC
t
RAS
t
RP
t
t
RP
ACTꢀ
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
76
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Byte Operation
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀꢀ
T11
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
t
AS
BANKꢀ1
BANKꢀ1
BANKꢀ0
BANKꢀ1ꢀ
BANKꢀ1ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
tCH
t
CS
t
QMD
QMD
UDQM
t
t
CS
t
CH
LDQM
t
t
AC
t
HZ
t
AC
t
AC
t
HZ
t
OH
t
LZ
t
OH
tLZ
DQ8-15
D
OUT
m
D
OUT m+2
D
OUT m+3
AC
t
t
AC
t
HZ
LZ
t
OH
t
OH
DOUT m+1
D
OUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
RP
t
RCD
RAS
RP
tRAS
RC
t
t
t
t
<
PRE>
<ACT>
<
READ
READA
>
<
MASKU
>
<ACT>
<
ENBU,ꢀMASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
77
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Byte Operation
T11ꢀ
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMNꢀm
ROW
ROW
ROW
A0-A9
AUTOꢀPRE
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
t
t
AH
AH
ROW
A10
A11
NOꢀPRE
BANKꢀ1
t
AS
BANKꢀ1
BANKꢀ0
BANKꢀ1ꢀ
BANKꢀ1ꢀ
BANKꢀ0
BANKꢀ0
BANKꢀ0
t
CS
tCH
UDQM
t
CS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
DH
tDH
t
DH
t
DS
tDS
D
INꢀ
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
INꢀ
m
D
IN m+3
t
RCD
t
DPL
t
RCD
RAS
RP
t
RAS
RC
tRP
t
t
t
<
PRE
PALL
>
<ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<
ENB>
<
>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
78
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Read Cycle, Write Cycle / Burst Read, Single Write
T11
T12ꢀꢀꢀꢀꢀ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10ꢀꢀꢀꢀꢀꢀ
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
t
WE
t
t
AS
AS
t
AH
(1)
(1)
COLUMNꢀm
COLUMNꢀn
ROW
ROW
A0-A9
A10
BANKꢀ0ꢀANDꢀ1
BANKꢀ0ꢀORꢀ1
AUTOꢀPRE
t
AH
AH
NOꢀPRE
NOꢀPRE
t
t
AS
BANKꢀ1
BANKꢀ1ꢀ
BANKꢀ1
BANKꢀ0
BANKꢀ1
BANKꢀ0
A11
BANKꢀ0
BANKꢀ0
t
CS
tCH
tQMD
DQM
DQ
tAC
t
AC
t
DS
t
OH
t
OH
tDH
D
OUT
m
D
OUT m+1
DIN
n
t
LZ
tHZ
tRC
tCAC
t
DPL
t
RAS
RC
t
RP
t
<
WRIT
>
<
PRE
>
<
ACT>
<
READ>
Undefined
Don'tꢀCare
CAS latency = 3, burst length = 2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com
79
Rev. D
08/24/09
IS42S16100E, IS45S16100E
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency
Speed (ns)
Order Part No.
Package
200 MHz
5
6
7
IS42S16100e-5T
IS42S16100e-5TL
IS42S16100e-5BL
400-mil TSop II
400-mil TSop II, Lꢂꢄꢃ-ꢇrꢂꢂ
60-bꢄll Bga, Lꢂꢄꢃ-ꢇrꢂꢂ
166 MHz
143MHz
IS42S16100e-6T
IS42S16100e-6TL
IS42S16100e-6BL
400-mil TSop II
400-mil TSop II, Lꢂꢄꢃ-ꢇrꢂꢂ
60-bꢄll Bga, Lꢂꢄꢃ-ꢇrꢂꢂ
IS42S16100e-7T
IS42S16100e-7TL
IS42S16100e-7BL
400-mil TSop II
400-mil TSop II, Lꢂꢄꢃ-ꢇrꢂꢂ
60-bꢄll Bga, Lꢂꢄꢃ-ꢇrꢂꢂ
Industrial Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
166 MHz
6
7
IS42S16100e-6TLI
IS42S16100e-6BLI
400-mil TSop II, Lꢂꢄꢃ-ꢇrꢂꢂ
60-bꢄll Bga, Lꢂꢄꢃ-ꢇrꢂꢂ
143MHz
IS42S16100e-7TLI
IS42S16100e-7BLI
400-mil TSop II, Lꢂꢄꢃ-ꢇrꢂꢂ
60-bꢄll Bga, Lꢂꢄ-ꢇrꢂꢂ
plꢂꢄsꢂ ꢅꢀntꢄꢅt thꢂ prꢀꢃuꢅt Mꢄnꢄꢈꢂr ꢇꢀr lꢂꢄꢃꢂꢃ ꢁꢄrts suꢁꢁꢀrt.
ORDERING INFORMATION
Automotive Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
166ꢀMHzꢀ
6ꢀ
IS45S16100E-6TLA1ꢀ
400-milꢀTSOPꢀII,ꢀLead-free
ꢀ
ꢀ
143MHzꢀ
ꢀ
7ꢀ
ꢀ
IS45S16100E-7TLA1ꢀ
IS45S16100E-7BLA1ꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-freeꢀ
Automotive Range: -40°C to +105°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
143MHzꢀ
ꢀ
7ꢀ
ꢀ
IS45S16100E-7TLA2ꢀ
IS45S16100E-7BLA2ꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-free
80
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
IS42S16100E, IS45S16100E
Integrated Silicon Solution, Inc. — www.issi.com
81
Rev. D
08/24/09
IS42S16100E, IS45S16100E
82
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
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