IS42S16160A-7TL [ISSI]
256 Mb Synchronous DRAM; 256 MB同步DRAM
| 型号： | IS42S16160A-7TL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256 Mb Synchronous DRAM |
| 文件： | 总49页 (文件大小：918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
ISSI
256 Mb Synchronous DRAM
November 2005
DESCRIPTIONꢀ
IS42S83200A is a synchronous 256Mb SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A is organized as 4-bank x 4,194,304-word x
16-bit. All inputs and outputs are referenced to the rising
edge of CLK.
IS42S83200A and IS42S16160A achieve very
high speed clock rates up to 166MHz, and are
suitable for main memories or graphic
memories in computer systems.
FEATURES
IS42S83200A/16160A
ITEM
Unit
ns
-75
10
-7
-
-6
-
CL=2
CL=3
tCLK
tRAS
Clock CycleTime
(Min.)
7.5
7
ns
ns
ns
ns
ns
ns
6
45
20
45
Active to Precharge Command Period(Min.)
42
tRCD Row to ColumnDelay
(Min.)
(Max.)
(Min.)
20
-
15
-
CL=2
CL=3
6
tAC
tRC
Access Time from CLK
5.4
67.5
5.4
63
5
Ref /Active Command Period
60
mA
IS42S83200A
-
-
110
Operation Current (SingleBank)
(Max.)
(Max.)
Icc1
mA
mA
IS42S16160A
-6,-7,-75
130
3
-
130
3
Self Refresh Current
Icc6
3
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
-6:166MHz<3-3-3>
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package: 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
- Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
1
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
PIN CONFIGURATION (TOP VIEW)ꢀ
x8
x16
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
Vss
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VddQ
DQ8
Vss
Vss
NC
NC
DQMU DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
BA0
BA1
A10/AP A10/AP
A0
A1
A2
A3
Vdd
A0
A1
A2
A3
Vdd
DQM, DQMU/L : Output Disable / Write Mask
CLK
: Master Clock
A0-12
BA0,1
Vdd
: Address Input
CKE
/CS
: Clock Enable
: Bank Address Input
: Power Supply
: Chip Select
/RAS
/CAS
/WE
: Row Address Strobe
VddQ
Vss
: Power Supply for Output
: Ground
: Column Address Strobe
: Write Enable
VssQ
: Ground for Output
DQ0-15
: Data I/O
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
8192x1024x8
Cell Array
Memory Array
8192x1024x8
Cell Array
Memory Array
Memory Array
8192x1024x8
Cell Array
Bank #2
8192x1024x8
Cell Array
Bank #3
Bank #0
Bank #1
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
/CS
/RAS
/WE
A0-12
CLK
CKE
/CAS
DQM
BA0,1
Note:This figure shows the IS42S83200A
TheꢀIS42S16160Aꢀconfigurationꢀisꢀ8192x512x16ꢀofꢀcellꢀarrayꢀandꢀDQ0-15ꢀ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
3
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
PIN FUNCTIONꢀ
Master Clock:
CLK
CKE
Input
Input
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
/CS
Input
Input
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.
The Column Address is specified by A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
A0-12
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
Input
DQ0-7(x8),
Data In and Data out are referenced to the rising edge of CLK.
Input / Output
DQ0-15(x16)
Din Mask / Output Disable:
DQM(x8),
DQMU/L(x16)
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Input
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply
VddQ,VssQ
VddQ and VssQ are supplied to the Output Buffers only.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
BASIC FUNCTIONSꢀ
The IS42S83200A/16160A provides basic ꢀ
functions, bank (row) activate, burst read / write, bank (row) ꢀ
precharge, and auto / self refresh.ꢀ
/CAS and /WE at CLK rising edge. In addition to 3 signals,ꢀ
/CS, CKE and A10 are used as chip select, refresh opt ion,ꢀ
and precharge option, respectively .ꢀ
Each command is defined by control signals of /RAS,ꢀ
To know the detailed definition of commands,ꢀ
please see the command truth table.ꢀ
CLK
/CS
/RAS
/CAS
/WE
Chip Select : L=select, H=deselect
Command
Command
Command
define basic command
CKE
A10
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.
First output data appears after /CAS latency. When A10 =H at this command,
the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total
data length to be written is set by burst length. When A10 =H at this command,
the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This com
mand also terminates burst read / write operation. When A10 =H at this
command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank
address are generated internally. After this command, the banks are
precharged automatically.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
5
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
COMMAND TRUTH TABLEꢀ
CKE CKE
A10 A0-9,
/AP 11-12
note
COMMAND
MNEMONIC
/CS
/RAS /CAS /WE BA0,1
n-1
n
X
X
Deselect
DESEL
NOP
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
H
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
WRITEA
READ
H
H
X
X
L
L
H
H
L
L
L
V
V
H
L
V
V
Auto-Precharge
Column Address Entry
& Read
H
Column Address Entry
& Read with
READA
H
X
L
H
L
H
V
H
V
Auto-Precharge
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Self-Refresh Entry
L
L
H
H
X
X
X
H
H
L
X
H
H
L
Self-Refresh Exit
REFSX
L
Burst Terminate
TBST
MRS
H
H
1
Mode Register Set
L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode Address
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
FUNCTION TRUTH TABLEꢀ
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
H
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP
NOP
TBST
ILLEGAL*2
L
X
H
L
BA, CA, A10
BA, RA
READ / WRITE ILLEGAL*2
ACT Bank Active, Latch RA
PRE / PREA NOP*4
IDLE
L
H
H
L
L
L
L
BA, A10
L
H
X
REFA
MRS
Auto-Refresh*5
Op-Code,
Mode-Add
L
L
L
L
Mode Register Set*5
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP
NOP
TBST
NOP
Begin Read, Latch CA,
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
Determine Auto-Precharge
ROW
ACTIVE
WRITE /
WRITEA
Begin Write, Latch CA,
L
Determine Auto-Precharge
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Precharge / Precharge All
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
TBST
Terminate Burst, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA Begin New Read, Determine
Auto-Precharge*3
READ
Terminate Burst, Latch CA,
WRITE /
Begin Write, Determine Auto-
WRITEA
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
7
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
Action
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
L
H
H
H
H
H
L
X
X
NOP
NOP (Continue Burst to END)
Terminate Burst
TBST
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine Auto-
Precharge*3
Terminate Burst, Latch CA,
WRITE /
WRITE
L
H
L
L
L
BA, CA, A10
BA, RA
Begin Write, Determine Auto-
WRITEA
Precharge*3
L
H
H
ACT
Bank Active / ILLEGAL*2
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
X
X
TBST
L
H
BA, CA, A10
READ / READA ILLEGAL
READ with
WRITE /
ILLEGAL
AUTO
L
H
L
L
BA, CA, A10
WRITEA
PRECHARGE
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
X
X
TBST
H
BA, CA, A10
READ / READA ILLEGAL
WRITE with
AUTO
WRITE /
ILLEGAL
WRITEA
L
H
L
L
BA, CA, A10
PRECHARGE
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL*2
H
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
TBST
PRE -
L
L
L
L
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA NOP*4 (Idle after tRP)
CHARGING
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL*2
X
X
TBST
ROW
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
ACTIVATING
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
X
TBST
ILLEGAL*2
WRITE RE-
COVERING
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
9
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
H
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
TBST
RE-
L
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
FRESHING
L
H
H
L
L
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
X
X
TBST
MODE
REGISTER
SETTING
L
L
L
L
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
FUNCTION TRUTH TABLE (continued)
CKE CKE
Current State
/CS /RAS /CAS /WE Add
Action
n-1
H
L
n
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
SELF-
REFRESH*1
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Power Down)
Refer to Function Truth Table
Enter Self-Refresh
L
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
ALL BANKS
IDLE*2
L
Enter Power Down
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle*3
Exit CLK Suspend at Next Cycle*3
Maintain CLK Suspend
H
H
L
ANY STATE
other than
H
L
listed above
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronouslyꢀ. A minimum setup time must be
satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
SIMPLIFIED STATE DIAGRAMꢀ
SELF
REFRESH
REFS
REFSX
MODE
MRS
REGISTER
REFA
AUTO
REFRESH
IDLE
SET
CKEL
CLK
SUSPEND
CKEH
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TERM
READ
TERM
WRITE
WRITEA READA
CKEL
CKEH
CKEL
READ
SUSPEND
WRITE
SUSPEND
READ
WRITE
READ
WRITE
CKEH
READA
WRITEA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
PRE
READA
PRE
POWER
APPLIED
PRE
CHARGE
POWER
ON
PRE
Automatic Sequence
Command Sequence
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
MODE REGISTER
POWER ON SEQUENCE
Burst Length, Burst Type and /CAS Latency can
be programmed by setting the mode register
(MRS). The mode register stores these data until
the next MRS command, which may be issued
when all banks are in idle state. After tRSC from a
MRS command, the SDRAM is ready for new
command.
Before starting normal operation, the following
power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain
CKE high, DQM high and NOP condition at the
inputs.
2. Maintain stable power, stable clock, and NOP
input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE
or PREA)
4. After all banks become idle state (after tRP),
issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize
the mode register.
CLK
/CS
After these sequence, the SDRAM is idle state and
ready for normal operation.
/RAS
/CAS
/WE
V
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
SW
0
0
LTMODE
BT
BL
0
1
Burst Write
Single Write
SW
BL
BT=0
BT=1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
2
CL
/CAS LATENCY
4
4
BURST
LENGTH
8
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
R
R
R
R
R
R
R
LATENCY
MODE
3
Full Page
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R: Reserved for Future Use
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
13
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
CLK
Read
Write
Y
Command
Y
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
/CAS Latency
CL= 3
BL= 4
Burst Length
Burst Length
Burst Type
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
OPERATIONAL DESCRIPTION
READ
BANK ACTIVATE
After tRCD from the bank activation, a READ
command can be issued. 1st output data is avail-
able after the /CAS Latency from the READ, fol
lowed by (BL -1) consecutive data when the Burst
Length is BL. The start address is specified by
A0-9(X8), A0-8(X16) , and the address sequence of
burst data is defined by the Burst Type.
The SDRAM has four independent banks. Each bank
is activated by the ACT command with the bank ad-
dresses (BA0,1). A row is indicated by the row ad-
dresses A0-12. The minimum activation interval be-
tween one bank and the other bank is tRRD.Multiple
banks can be active state concurrently by issuing mul
tiple ACT commands.
A READ command may be applied to any
active bank, so the row precharge time (tRP) can be
hidden behind continuous output data by
PRECHARGE
The PRE command deactivates the bank indicated
by BA0,1. When multiple banks are active, the
precharge all command (PREA, PRE + A10=H) is
available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the
same bank can be issued.BA0-1 are “DON’T CARE”
in this case.
interleaving the multiple banks. When A10 is high
at a READ command, the auto-precharge
(READA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is
inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA.
The next ACT command can be issued after (BL
+ tRP) from the previous READA.ꢀ
In any case, tRCD+BL tRASmin must be met.ꢀ
≥
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
ACT
Xa
ACT
Xb
READ
Yb
PRE
ACT
Xa
tRRD
tRCD
tRP
A0-9,11-12
A10
Xa
Xb
0
1
Xa
BA0-1
DQ
00
01
01
00
Qb0
Qb1
Qb2
Qb3
Precharge All
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
15
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Multi Bank Interleaving Read (CL=2, BL=4)
CLK
Command
READ
Ya
ACT
Xa
ACT
Xb
READ PRE
Yb
ACT
Xa
tRCD
tRCD
tRP
A0-9,11-12
A10
0
Xa
Xa
Xb
0
01
0
00
BA0-1
DQ
00
00
00
01
Qa0
Qa1
Qa2
Qa3
Qb1
Qb3
Qb0
Qb2
Read with Auto-Precharge (CL=2, BL=4)
CLK
Command
ACT
Xa
READ
Ya
ACT
tRCD
BL
tRP
A0-9,11-12
A10
Xa
Xa
00
Xa
1
BA0-1
DQ
00
00
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
Command
ACT
READ
ACT
Qa3
tRCD
BL
DQ
DQ
CL=2
Qa0
Qa1
Qa0
Qa2
Qa1
Qa3
Qa2
CL=3
internal precharge starts
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
WRITE
required. When A10 is high at a WRITE command ,
A WRITE command can be issued to any active bank.
The start address is specified by A0-9(x8), A0-8(x16).
1st input data is set at the same cycle as the WRITE.
The consecutive data length to be write is defined
by the Burst Length. The address sequence of
burst data is defined by Burst Type. Minmum delay
time of a WRITE command after an ACT command to
the same bank is tRCD. From the last input data to the
PRE command , the write recovery time (tWR) is
auto-precharge (WRITEA) is performed. Any com
mand (READ,WRITE,PRE,ACT,TBST) to the same
bank is inhibited till the internal precharge is complete.
The internal precharge starts at tWR after the last input
data cycle . The next ACT command can be issued
after (BL+tWR-1+tRP) from the previous WRITEA. In
any case, tRCD+BL+tWR-1 tRASmin must be met.
≥
Write (BL=4)
CLK
ACT
Xa
Write
Ya
PRE
ACT
Xa
Command
BL
tRCD
tRP
A0-9,11-12
A10
Xa
0
0
Xa
BA0-1
DQ
00
00
00
tWR
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK
Command
ACT
Xa
Write
ACT
Xa
tRCD
BL
tRP
A0-9,11-12
A10
Ya
1
Xa
Xa
BA0-1
DQ
00
00
00
tWR
Da0
Da1
Da2
Da3
internal precharge starts
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
17
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed
READ to READ interval is minimum 1 CLK..
Read interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
READ
Yb
READ
Ya
READ
Yc
0
0
0
BA0-1
00
00
10
DQ
Qc0
Qa0
Qa1
Qa2
Qb0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the
DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled
automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
READ
Ya
Write
Ya
0
Xa
0
BA0-1
00
00
00
DQM
DQ
Qa0
Da0
Da1
Da2
Da3
Output disable by DQM
by WRITE
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge
of the same bank . READ to PRE interval is minimum 1
CLK. A PRE command to output disable latency is
equivalent to the /CAS Latency. As a result, READ to
PRE interval determines valid data length to be output.
The figure below shows examples of BL=4.
Read interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
DQ
Q0
Q1
Q2
Command
READ
PRE
CL=2
DQ
Q0
Q0
Q1
Command
READ PRE
DQ
Command
READ
PRE
Q0
DQ
Q1
Q1
Q2
Command
READ
PRE
CL=3
DQ
Q0
Q0
Command
READ PRE
DQ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
19
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[Read Interrupted by Burst Terminate]
Similarly to the precharge, a burst terminate command
can interrupt the burst read operation and disable the
data output. The terminated bank remains active.
READ to TBST interval is minimum 1 CLK. A TBST
command to output disable latency is equivalent to
the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
READ
TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
CL=2
DQ
Q0
Q0
Q1
Command
READ TBST
DQ
Command
TBST
Q0
READ
DQ
Q1
Q1
Q2
Command
TBST
READ
CL=3
DQ
Q0
Q0
Command
READ TBST
DQ
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to
WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
Write
Ya
Write Write
A
0-9,11-12
A10
Yb
0
Yc
0
0
BA0-1
DQ
00
00
10
Da0
Da1
Da2
Db0
Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"don't care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
Write
Ya
READ
Yb
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0 Qb1
Qb2
Qb3
don't care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
21
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
0
Write
Ya
0
PRE
ACT
Xa
0
tRP
0
BA0-1
DQM
00
00
00
00
tWR
DQ
Da0
Da1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not
required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
A0-9,11-12
A10
Write
Ya
ACT
Xa
0
TBST
Write
Yb
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after(BL+tWR-1+ tRP) from the WRITEA. Auto-precharge interruption by a command to the
same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
Command
A0-9,11-12
A10
Write
Ya
Write
BL
ACT
Xa
tRP
Yb
tWR
Db2
1
Xa
0
BA0-1
00
00
10
DQ
Db0
Db1
Da0
Da1
Db3
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Write
Ya
Read
BL
ACT
Xa
tRP
A0-9,11-12
A10
Yb
tWR
Qb0
Xa
1
0
00
BA0-1
DQ
00
10
Da0
Da1
Qb1
Qb2
Qb3
activate
auto-precharge interrupted
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
23
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
Read
Ya
1
Read
BL
ACT
Xa
tRP
Yb
0
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
activate
Qb3
auto-precharge interrupted
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read
or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined
by (A2-0).
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
AUTO REFRESH
concurrently. Before performing an auto-refresh, all
Single cycle of auto-refresh is initiated with a REFA
(/CS= /RAS= /CAS= L, /WE= /CKE= H) command.
The refresh address is generated internally. 8192
REFA cycles within 64ms refresh 256M bit memory
cells. The auto-refresh is performed on 4 banks
banks must be in the idle state. Auto-refresh to auto-
refresh interval is minimum tRFC. Any command must
not be supplied to the device before tRFC from the
REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A
0-12
B
A0-1
Auto Refresh on All Banks
Auto Refresh on All Banks
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
25
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
SELF REFRESH
nous inputs is saved. To exit the self-refresh, supply
ing stable CLK inputs, asserting DESEL or NOP com
mand and then asserting CKE=H. After tRFC from the
1st CLK egde following CKE=H, all banks are in the
idle state and a new command can be issued, but
DESEL or NOP commands must be asserted till then.
Self-refresh mode is entered by issuing a REFS
command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as
long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input .
All other inputs including CLK are disabled and
ignored, so that power consumption due to synchro
Self-Refresh
CLK
/CS
Stable CLK
NOP
/RAS
/CAS
/WE
CKE
A0-12
new command
X
00
B
A0-1
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
CLK SUSPEND
CKE controls the internal CLK at the following cycle.
Figure below shows how CKE works. By negating CKE,
the next internal CLK is suspended. The purpose of
CLK suspend is power down, output suspend or input
suspend. CKE is a synchronous input except during
the self-refresh mode. CLK suspend can be performed
either when the banks are active or idle. A command
at the suspended cycle is ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
CKE
Standby Power Down
Active Power Down
Command
PRE NOP NOP NOP
CKE
Command
ACT NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
Write
Read
D0
D1
D2
D3
DQ
Q0
Q1
Q2
Q3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
27
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
DQM CONTROL
DQM is a dual function signal defined as the data mask
for writes and the output disable for reads. During writes,
DQM(U,L) masks input data word by word. DQM(U,L)
to write mask latency is 0. During reads, DQM(U,L)
forces output to Hi-Z word by word. DQM(U,L) to output
Hi-Z latency is 2.
DQM Function
CLK
Command
Write
Read
DQMU/L
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
28
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
ABSOLUTE MAXIMUM RATINGSꢀ
Symbol
Vdd
Parameter
Conditions
Ratings
Unit
V
Supply Voltage
with respect to Vss
-0.5 - 4.6
-0.5 - 4.6
-0.5 - 4.6
-0.5 - 4.6
Supply Voltage for Output
Input Voltage
VddQ
VI
V
with respect to VssQ
with respect to Vss
with respect to VssQ
V
VO
V
Output Voltage
Output Current
IO
Pd
mA
50
1000
mW
Power Dissipation
Ta = 25˚C
Operating Temperature
Topr
Tstg
˚C
˚C
0 - 70
Storage Temperature
-65 - 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
3.0
0
Max.
Supply Voltage
Vdd
Vss
3.6
V
V
3.3
0
Supply Voltage
0
3.6
0
VddQ
VssQ
Supply Voltage for output
3.0
0
V
V
3.3
0
Supply Voltage for output
High-Level Input Voltage all inputs
VddQ +0.3
0.8
2.0
VIH*1
VIL*2
V
V
Low-level Input Voltage all inputs
-0.3
NOTES:
1. VIH (max) = VDDQ + 2.0V for a pulse width of < 3ns.
2. VIL (min) = -2.0V for a pulse width of < 3ns.
3. All voltages referenced to VSS/VSSQ.
CAPACITANCE
(Ta=0 -70˚C,Vdd=VddQ=3.3± 0.3V,Vss=VssQ=0V,unless otherwise noted)
Limits (max.)
Limits (min.)
Symbol
Test Condition
Parameter
Unit
pF
-6ꢀꢀ/-7
ꢀ-75
3.8
5.0
5.0
4.0
6.5
2.5
2.5
2.5
4.0
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, contorl pin
@ 1MHz
1.4V bias
200mV swing
Vcc=3.3V
pF
pF
pF
3.8
3.5
Input Capacitance, CLK pin
Input Capacitance, I/O pin
6.5
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
29
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits (max.)
Organi-
Symbol
ITEM
Unit
mA
Note
zation
-6
-7
-75
x8
110
-
-
tRC=min, tCLK=min
BL=1,IOL=0mA
Icc1
Operating current
1
130
130
-
x16
mA
mA
mA
mA
mA
CKE=VILmax
tCLK=15ns
Icc2N
Icc2NS
Icc2P
Precharge Standby
current in Non-Power
down mode
Precharge Standby
current in Power down
mode
x8/x16
x8/x16
x8/x16
x8/x16
20
15
2
20
15
2
20
15
2
2,3
2,4
CKE=VIHmin
CLK=VILmax(fixed)
CKE=VIHmin
tCLK=15ns(Note)
2
CKE=VIHmin
tCLK=VILmax(fixed)
Icc2PS
Icc3N
2
2
2
CKE=/CS=VIHmin
tCLK=15ns(Note)
x8/x16
x8/x16
30
30
30
3,5
4,5
mA
mA
Active Standby current
CKE=VIHmin
tCLK=VILmax(fixed)
Icc3NS
20
20
20
x8
-
150
-
mA
mA
All Bank Active
tCLK = min
BL=4, CL=3, IOL=0mA
Burst current
5
Icc4
160
160
x16
-
mA
mA
Auto-refresh current
Self-refresh current
tRC=min, tCLK=min
Icc5
Icc6
160
3
160 160
x8/x16
-6,-7,-75
CKE < 0.2V
x8/x16
3
3
NOTE:
1.address are changed 3 times during tRC , only 1 bank is active & all other banks are idle
2.all banks are idle
3.input signals are changed one time during 3x tCLK
4.input signals are stable
5.all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICSꢀ
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits
Parameter
Test Conditions
unit
V
Symbol
Max.
Min.
VOH (DC)
VOL (DC)
IOZ
High-Level Output Voltage (DC)
Low-level Output Voltage (DC)
Off-state Output Current
Input Current
-
0.4
10
10
IOH=-2mA
2.4
-
IOL= 2mA
V
µA
-10
Q floating VO=0 -- VddQ
µA
II
-10
VIH = 0 -- VddQ +0.3V
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
AC TIMING REQUIREMENTSꢀ
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Limits
-7
Unit
-75
-6
Parameter
Symbol
tCLK
Min.
Min. Max.
Max.
Max.
Min.
10
CL=2
CL=3
ns
ns
-
CLK cycle time
-
7
7.5
6
tCH
tCL
tT
CLK High pulse width
CLK Low pulse width
2.5
2.5
ns
ns
2.5
2.5
2
2
1
10
1
10
ns
ns
1
10
Transition time of CLK
1.8
1.8
tIS
Input Setup time (all inputs)
1.8
1
1
1
tIH
Input Hold time (all inputs)
Row Cycle time
ns
ns
tRC
67.5
75
60
60
15
63
70
20
ns
ns
tRFC Refresh Cycle Time
tRCD Row to Column Delay
20
tRAS
Row Active time
120K
120K
45
20
ns
ns
120K 45
20
42
15
tRP
Row Precharge time
Write Recovery time
Act to Act Delay time
tWR
ns
15
15
15
14
12
12
12
tRRD
tRSC
ns
ns
us
14
Mode Register Set Cycle time
Refresh Interval time
14
7.8
7.8
7.8
tREF
1.4V
CLK
1.4V
DQ
Any AC timing is referenced
to the input signal passing
through 1.4V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
31
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
SWITCHING CHARACTERISTICSꢀ
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits
Symbol
tAC
Parameter
-6
-75
-7
Unit
Note
Max.
5.4
Max.
6
Min. Max. Min.
Min.
CL=2
CL=3
ns
ns
Access time from CLK
5.4
5
CL=2
CL=3
ns
ns
Output Hold time
from CLK
3
3
tOH
*1
2.7
0
2.5
0
Delay time , output low-
impedance from CLK
ns
ns
tOLZ
0
3
Delay time , output high-
impedance from CLK
tOHZ
5.4
2.7
2.5
5.4
5
NOTE:
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
CLK
1.4V
1.4V
VOUT
50pF
DQ
Output Timing Measurement
Reference Point
CLK
DQ
1.4V
1.4V
tOLZ
tAC
tOHZ
tOH
32
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Burst Write (Single Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
A12
0
0
0
0
BA0,1
DQ
D0 D0 D0 D0
D0 D0 D0 D0
ACT#0 WRITE#0
PRE#0 ACT#0 WRITE#0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
33
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Burst Write (Multi Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRAS
tRP
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
X
X
X
0
Y
X
X
X
1
A12
0
1
0
0
0
BA0,1
DQ
D0 D0 D0 D0 D1 D1 D1 D1
D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
PRE#0 ACT#0 WRITE#0
PRE#0
WRITEA#1
(Auto-Precharge)
ACT#1
Italic paramater shows minimum case
34
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Burst Read (Single Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
A12
0
0
0
0
BA0,1
DQ
Q0 Q0 Q0 Q0
Q0 Q0 Q0 Q0
ACT#0 READ#0
PRE#0 ACT#0 READ#0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
35
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Burst Read (Multi Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRRD
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
X
Y
X
X
X
1
X
X
0
A12
0
1
0
0
BA0,1
DQ
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READA#0
ACT#1
ACT#0 READ#0
PRE#0
ACT#1
READA#1
Italic paramater shows minimum case
36
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Write Interrupted by Write [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A12
0
0
1
0
0
BA0,1
DQ
D0 D0 D0 D0 D0 D1 D1 D1 D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
WRITE#0 WRITEA#1
interrupt interrupt
same bank other bank
WRITE#0
interrupt
other bank
PRE#0
ACT#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
37
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Read Interrupted by Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A12
0
1
1
0
BA0,1
DQ
Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READ#0
ACT#1
READ#1 READA#1
interrupt interrupt
other bank same bank other bank
READ#0
interrupt
ACT#1
Italic paramater shows minimum case
38
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
X
Y
Y
Y
X
X
1
A12
0
1
1
1
BA0,1
DQ
D0 D0
Q1 Q1
D1 D1 D1 D1
ACT#0
WRITE#0 READ#1
ACT#1
WRITE#1
PRE#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
39
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Write / Read Terminated by Precharge [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRP
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
X
X
X
0
A12
0
0
0
0
BA0,1
DQ
D0 D0
Q0 Q0
ACT#0 WRITE#0
ACT#0
READ#0 PRE#0
Terminate
ACT#0
PRE#0
Terminate
Italic paramater shows minimum case
40
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
Y
A12
0
0
0
0
BA0,1
DQ
D0 D0
Q0 Q0
D0 D0 D0 D0
ACT#0 WRITE#0
READ#0 TBST
WRITE#0
PRE#0
TBST
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
41
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Single Write Burst Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
A12
0
0
BA0,1
DQ
D0
Q0 Q0 Q0 Q0
ACT#0 WRITE#0 READ#0
Italic paramater shows minimum case
42
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Power-Up Sequence and Intialize
CLK
200µs
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
MA
0
X
X
X
0
A12
0
0
BA0,1
DQ
NOP
Power On
PRE ALL REFA
REFA
REFA
MRS
ACT#0
Minimum 8 REFA cycles
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
43
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
A12
0
BA0,1
DQ
D0 D0 D0 D0
PRE ALL
REFA
ACT#0 WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Self Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
X
X
X
0
A12
BA0,1
DQ
PRE ALL Self Refresh Entry
All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
45
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
CLK Suspension [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
A12
0
0
BA0,1
DQ
D0 D0
D0 D0
Q0 Q0
Q0
Q0
ACT#0 WRITE#0 internal CLK
suspended
READ#0
internal CLK
suspended
Italic paramater shows minimum case
46
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-9,11
A10
X
X
X
0
A12
BA0,1
DQ
PRE ALL
ACT#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
47
11/01/05
IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
166 MHz
143 MHz
133 MHz
Speed(ns)
Order Part No.
Package
6
7
IS42S16160A-6T
IS42S16160A-7T
IS42S83200A-75T
54-pinTSOP-II
54-pinTSOP-II
54-pinTSOP-II
7.5
Commercial Range: 0°C to +70°C, Lead-free
Frequency
166 MHz
143 MHz
133 MHz
Speed(ns)
Order Part No.
Package
6
7
IS42S16160A-6TL
IS42S16160A-7TL
IS42S83200A-75TL
54-pinTSOP-II
54-pinTSOP-II
54-pinTSOP-II
7.5
48
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Plastic TSOP (T - Type II)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Symbol Min
Max
Min
Max
Ref. Std.
Ref. Std.
No. Leads (N)
54
No. Leads (N)
86
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
A
A1
A2
b
C
D
E1
E
e
—
1.20
0.05 0.15
0.95 1.05
0.17 0.27
0.12 0.21
22.02 22.42
10.16 BSC
11.56 11.96
0.50 BSC
—
0.047
0.05 0.15
—
0.002 0.006
—
0.002 0.006
0.037 0.041
0.007 0.011
0.005 0.008
0.867 0.8827
0.400 BSC
—
—
0.30 0.45
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.80 BSC
0.012 0.018
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.031 BSC
0.455 0.471
0.020 BSC
L
0.40 0.60
0.016 0.024
L
0.40 0.60
0.80 REF
0.61 REF
0.016 0.024
0.031 REF
0.024 BSC
L1
ZD
α
—
—
—
—
L1
ZD
α
0.71 REF
0° 8°
0°
8°
0°
8°
0°
8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
1
01/28/02
相关型号：
IS42S16160A1-7T
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
ISSI
IS42S16160A1-7TL
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, PLASTIC, TSOP2-54
ISSI
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