IS42S16800A1-7TL [ISSI]
8Meg x16 128-MBIT SYNCHRONOUS DRAM; 8Meg X16 128兆位同步DRAM
| 型号： | IS42S16800A1-7TL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| 文件： | 总63页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS42S16800A1
ISSI
8Meg x16
128-MBIT SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
MAY 2006
OVERVIEW
FEATURES
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
VDD
VDDQ
IS42S16800A1
2M x16x4 Banks
54-pin TSOPII
IS42S16800A1
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
KEY TIMING PARAMETERS
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
Parameter
-7
Unit
CK Cycle Time
CAS Latency = 3
7
7.5
ns
ns
• Burst read/write and burst read/single write
operations capability
CAS Latency = 2
CK Frequency
CAS Latency = 3
CAS Latency = 2
• Burst termination by burst stop and precharge
command
143
133
Mhz
Mhz
• Lead-free Availability
Access Time from Clock
CAS Latency = 3
5
5.4
ns
ns
CAS Latency = 2
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
DEVICE OVERVIEW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tionenabled. Prechargeonebankwhileaccessingoneofthe
otherthreebankswillhidetheprechargecyclesandprovide
seamless,high-speed,random-accessoperation.
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits.
SDRAMreadandwriteaccessesareburstorientedstartingat
aselectedlocationandcontinuingforaprogrammednum-
ber of locations in a programmed sequence. The registra-
tionofanACTIVEcommandbeginsaccesses, followedby
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
The128MbSDRAMincludesanAUTOREFRESHMODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation,theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableREADorWRITEburstlengthsconsistof1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (2MX16X4 BANKS)
CK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
LDQM
WE
CAS
RAS
CS
NC
UDQM
CK
CKE
NC
A11
A9
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CK
Row Address Input
Column Address Input
Bank Select Address
Data I/O
WE
WriteEnable
LDQM
UDQM
VDD
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
NoConnection
CAS
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3
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
command(row-addressA0-A11)andREAD/WRITEcommand(columnaddressA0-A8
(x16);with A10 defining auto precharge) to select one location out of the memory array
intherespectivebank.A10issampledduringaPRECHARGEcommandtodetermineif
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTERcommand.
BA0, BA1
CAS
Input Pin
Input Pin
Input Pin
BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE, READ, WRITEor
PRECHARGEcommandisbeingapplied.
CAS, inconjunctionwiththeRAS and WE, formsthedevicecommand. Seethe
"CommandTruthTable"fordetailsondevicecommands.
CKE
TheCKEinputdetermineswhethertheCKinputisenabled. Thenextrisingedgeofthe
CKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW. WhenCKEisLOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CK
Input Pin
Input Pin
CK is the master clock input for this device. Except for CKE, all inputs to this device are
acquiredinsynchronizationwiththerisingedgeofthispin.
CS
TheCSinputdetermineswhethercommandinputisenabledwithinthedevice.
Command input is enabled whenCSisLOW, anddisabledwithCS isHIGH. Thedevice
remains in the previous state when CS is HIGH.
LDQM,
UDQM
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
inconventionalDRAMs. Inwritemode, LDQMandUDQMcontroltheinputbuffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
DQ0-DQ7 or
DQ0-DQ15
Input/Output
Input Pin
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS
RAS,inconjunctionwithCASandWE,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
WE
Input Pin
WE,inconjunctionwithRASandCAS,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
VDDQ
VDD
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
VDDQ istheoutputbufferpowersupply.
VDD isthedeviceinternalpowersupply.
VSSQ istheoutputbufferground.
VSSQ
VSS
VSS isthedeviceinternalground.
4
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Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initializa-
tion sequence guarantees the device is preconditioned to each users specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power
on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP”
state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started
at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge
command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to ini-
tialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after
programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be
programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can
be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register
variables, all four variables must be redefined when the Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must
be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The
Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The
address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has elapsed.
CAS Latency
The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock
edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of
clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the
device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed
grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS
latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure
see Programming the Mode Register in the previous section.
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Rev. 00B
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®
IS42S16800A1
ISSI
Mode Register Operation (Address Input For Mode Set)
Address
Bus (Ax)
BA1 BA0
A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Mode
Register(Mx)
Operation Mode
CAS Latency
Burst Length
Burst Type
M3
0
Type
Sequential
Interleave
1
Operation Mode
Burst Length
M14 M13 M12 M11 M10 M9 M8 M7
Mode
Length
0
0
0
0
0
0
0
0
Normal
M2 M1 M0
Sequential Interleave
Multiple Burst
with
Single Write
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
CAS Latency
M6 M5 M4
Latency
Reserved
Reserved
2
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
6
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Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits
A7 - A11, BA0, and BA1.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst
sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a
Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 and full page sequential burst.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the
device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with
single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to
read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
0, 1
Interleave Addressing (decimal)
0, 1
x x 0
x x 1
x 0 0
x 0 1
x 1 0
x 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
4
8
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
256
(Full Page)
n= A0-A7
Cn, Cn1+2, Cn+3, C+4, ...
Not supported
Note: Page length is a function of I/O organization and column addressing.
x16 organization (CA0-CA8); Page Length = 512 bits
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Rev. 00B
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®
IS42S16800A1
ISSI
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank
Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select
address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in
the selected bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the
Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS
delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be
applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands
(Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active
is specified as tRAS(max)
.
Bank Activate Command Cycle
(CAS Latency = 3, tRCD = 3)
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CK
. . . . . . . . . .
Bank A
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
Bank A
Row Addr.
. . . . . . . . . .
ADDRESS
RAS-CAS delay (tRCD
)
RAS - RAS delay time (tRRD
)
Write A
with Auto
Precharge
Bank B
NOP
Bank A
Activate
Bank A
Activate
. . . . . . . . . .
NOP
NOP
NOP
COMMAND
Activate
: “H” or “L”
RAS Cycle time (tRC
)
Bank Select
The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write oper-
ation.
Bank Selection Bits
BA0
0
BA1
0
Bank
Bank 0
Bank 1
Bank 2
Bank 3
1
0
0
1
1
1
8
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Rev. 00B
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®
IS42S16800A1
ISSI
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low
at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine
whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the start-
ing column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write
operation on successive clock cycles up to 133 MHz for PC133 or upto 166MHz for PC166 devices. The number of serial data
bits for each access is equal to the burst length, which is programmed into the Mode Register.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected
row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank.
A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock
cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Com-
mand, the remaining addresses are overridden by the new address.
Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again.
To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Acti-
vate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations
are possible. By using the programmed burst length and alternating the access and precharge operations between multiple
banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are acti-
vated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be
issued to the same bank or between active banks on every clock cycle.
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Rev. 00B
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IS42S16800A1
ISSI
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock.
The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or
interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears
on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
2
3
tCK2, DQs
CAS latency = 3
DOUT A
3
0
1
2
tCK3, DQs
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that
the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain-
ing addresses are overridden by the new address with the burst length. The data from the first Read Command continues to
appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the
interrupting Read Command appears.
Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
0
1
2
tCK2, DQs
CAS latency = 3
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
1
2
tCK3, DQs
10
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Rev. 00B
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®
IS42S16800A1
ISSI
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ
bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
DQM
NOP
READ A
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A
DIN A
DIN A
DIN A
DIN A
DIN A
DIN A
DIN A
0
0
1
1
2
2
3
tCK2, DQs
CAS latency = 3
3
tCK3, DQs
: “H” or “L”
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Rev. 00B
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®
IS42S16800A1
ISSI
Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
DQM
READ A
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CL = 2: DQM needed to mask
first, second bit of READ data.
CAS latency = 2
DIN A
DIN A
DIN A
DIN A
DIN A
0
0
1
2
3
tCK2, DQs
CL = 3: DQM needed to
mask first bit of READ data.
CAS latency = 3
DIN A
DIN A
DIN A
1
2
3
tCK3, DQs
: DQM high for CAS latency = 2
: DQM high for CAS latency = 3
12
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®
IS42S16800A1
ISSI
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the
first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining
data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-
ished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DIN A
0
DIN A
DIN A
DIN A
3
DQs
1
2
: “H” or “L”
The first data element and the Write
are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-
rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-
grammed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
1 CK Interval
DIN A
DIN B
0
DIN B
DIN B
DIN B
3
DQs
0
1
2
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Rev. 00B
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®
IS42S16800A1
ISSI
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs
must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-
sented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
tCK2, DQs
CAS latency = 3
DIN A
0
DOUT B
3
0
1
2
tCK3, DQs
: “H” or “L”
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
14
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ISSI
Non-Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
NOP
READ B
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DIN A
0
DIN A
DIN A
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
1
1
2
3
tCK2, DQs
CAS latency = 3
DIN A
0
DOUT B
3
0
1
2
tCK3, DQs
: “H” or “L”
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
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Rev. 00B
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®
IS42S16800A1
ISSI
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command
or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during
the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst opera-
tion is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write
Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as
normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed.
Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can
also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or
Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or
Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper-
ation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has
been satisfied.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.
Burst Read with Auto-Precharge
(Burst Length = 1, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
RP
CAS latency = 2
*
tCK2, DQs
DOUT A
0
t
‡
RP
CAS latency = 3
*
tCK3, DQs
DOUT A
0
Bank can be reactivated at completion of tRP
.
*
Begin Auto-precharge
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
16
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IS42S16800A1
ISSI
Burst Read with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
RP
CAS latency = 2
*
tCK2, DQs
DOUT A
DOUT A
t
0
1
‡
RP
CAS latency = 3
*
tCK3, DQs
DOUT A
DOUT A
0
1
Begin Auto-precharge
Bank can be reactivated at completion of tRP
.
*
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Burst Read with Auto-Precharge
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tRP‡
CAS latency = 2
*
tCK2, DQs
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
tRP‡
CAS latency = 3
*
tCK3, DQs
DOUT A
DOUT A
0
1
2
3
Bank can be reactivated at completion of tRP
.
*
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Begin Auto-precharge
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Rev. 00B
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®
IS42S16800A1
ISSI
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted
by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge
function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP
.
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3)
T5 T6 T7 T8
T0
T1
T2
T3
T4
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ B
DOUT A
COMMAND
Auto-Precharge
t
‡
RP
CAS latency = 2
*
tCK2, DQs
DOUT A
t
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
1
0
1
0
2
3
‡
RP
CAS latency = 3
*
tCK3, DQs
DOUT A
DOUT A
DOUT B
DOUT B
DOUT B
3
0
1
1
2
Bank can be reactivated at completion of tRP
.
*
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE B
COMMAND
Auto-Precharge
t
‡
RP
*
CAS latency = 2
t
CK2, DQs
DOUT A
DIN B
0
DIN B
DIN B
DIN B
DIN B
4
0
1
2
3
DQM
Bank can be reactivated at completion of tRP
.
*
‡ tRP is a function of clock cycle time and speed sort..
See the Clock Frequency and Latency table.
18
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Rev. 00B
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IS42S16800A1
ISSI
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t ‡
DAL
CAS latency = 2
*
tCK2, DQs
DIN A
DIN A
DIN A
DIN A
0
1
t
‡
DAL
*
CAS latency = 3
tCK3, DQs
0
1
Bank can be reactivated at completion of tDAL
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
.
*
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
WRITE A
NOP
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
‡
DAL
*
CAS latency = 3
t
CK3, DQs
DIN A
DIN A
DIN B
DIN B
DIN B
DIN B
3
0
1
0
1
2
Bank can be reactivated at completion of tDAL
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
.
*
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Rev. 00B
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®
IS42S16800A1
ISSI
Burst Write with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CK
WRITE A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t ‡
DAL
*
CAS latency = 3
tCK3, DQs
DIN A
0
DIN A
DIN A
2
DOUT B
DOUT B
DOUT B
2
1
0
1
Bank A can be reactivated at completion of tDAL
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
.
*
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered
when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-
charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which
bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10
LOW
HIGH
Bank Select
BA0, BA1
Precharged Bank(s)
Single bank defined by BA0, BA1
All Banks
DON’T CARE
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be
executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-
charge time (tRP).
20
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Burst Read Followed by the Precharge Command
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
‡
*
t
RP
CAS latency = 3
DOUT Ax
DOUT Ax
DOUT Ax
2
DOUT Ax
3
0
1
tCK2, DQs
Bank A can be reactivated at completion of tRP
tRP is a function of clock cycle and speed sort.
.
*
‡
Burst Write Followed by the Precharge Command
(Burst Length = 2, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
Activate
Bank Ax
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
WRITE Ax
COMMAND
0
t
‡
t ‡
RP
DPL
*
CAS latency = 2
t
CK2, DQs
DIN Ax
DIN Ax
0
1
Bank can be reactivated at completion of tRP
.
*
‡ tDPL and tRP are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
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Rev. 00B
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IS42S16800A1
ISSI
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command
is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to
appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
t
‡
RP
*
CAS latency = 2
DOUT Ax
DOUT Ax
DOUT Ax
DOUT Ax
3
0
1
2
tCK2, DQs
t
‡
RP
*
DOUT Ax
3
CAS latency = 3
DOUT Ax
DOUT Ax
DOUT Ax
0
1
2
tCK3, DQs
Bank A can be reactivated at completion of tRP
.
‡
tRP is a function of clock cycle time and speed sort.
*
See the Clock Frequency and Latency table.
22
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Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the
device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the
Data-in to Precharge delay, tDPL
.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
WRITE Ax
COMMAND
DQM
0
t
‡
‡
DPL
CAS latency = 2
tCK2, DQs
DIN Ax
DIN Ax
DIN Ax
DIN Ax
DIN Ax
DIN Ax
0
1
2
t
DPL
CAS latency = 3
tCK3, DQs
0
1
2
‡ t
is an asynchronous timing and may be completed in one or two clock cycles
DPL
depending on clock cycle time.
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Rev. 00B
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ISSI
Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic
Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before
the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the
refresh cycle. No control of the external address pins is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto
Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or
equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-
ing CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the
Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self
Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is
cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device
exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus
the Self Refresh exit time (tSREX).
24
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Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down
mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must
occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation,
Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or
Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power
Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does
not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect
Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+ 8
CK
t
CK
CKE
t
CES(min)
NOP
COMMAND
NOP
NOP
NOP
NOP
NOP
COMMAND
: “H” or “L”
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Rev. 00B
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ISSI
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is
activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is
activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent
of CAS latency.
Data Mask Activated during a Read Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DOUT A
DQs
DOUT A
1
0
A two-clock delay before
the DQs become Hi-Z
: “H” or “L”
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No
Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Com-
mand will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is
brought high, the RAS, CAS, and WE signals become don’t cares.
26
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ISSI
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks
is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”
any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and
the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands
that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE
returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto
the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
A one clock delay to exit
the Suspend command
CKE
A one clock delay before
suspend operation starts
NOP
READ A
NOP
NOP
NOP
NOP
COMMAND
DQs
DOUT A
DOUT A
2
DOUT A
0
1
: “H” or “L”
DOUT element at the DQs when the
suspend operation starts is held valid
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-
pend mode is exited.
Clock Suspend during a Write Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
A one clock delay to exit
the Suspend command
CKE
A one clock delay before
suspend operation starts
NOP
WRITE A
NOP
NOP
NOP
NOP
COMMAND
DIN A
DIN A
DIN A
3
DIN A
0
DQs
1
2
: “H” or “L”
DIN is masked during the Clock Suspend Period
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Rev. 00B
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®
IS42S16800A1
ISSI
Command Truth Table (See note 1)
CKE
BA0,
BA1
A11,
A9-A0
Function
Device State
CS
RAS CAS
WE
DQM
A10
Notes
Previous Current
Cycle
Cycle
Mode Register Set
Auto (CBR) Refresh
Entry Self Refresh
Idle
H
H
H
X
H
L
L
L
L
H
L
L
L
L
L
L
H
H
X
H
X
X
X
OP Code
Idle
Idle
X
X
X
X
X
X
L
L
X
H
X
H
Idle (Self-
Refresh)
Exit Self Refresh
L
H
X
X
X
X
See Current
State Table
Single Bank Precharge
Precharge all Banks
H
H
X
X
L
L
L
L
H
H
L
L
X
X
BS
X
L
X
X
2
See Current
State Table
H
Bank Activate
Idle
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
H
X
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
L
BS
BS
BS
BS
BS
X
Row Address
2
2
2
2
2
Write
Active
Active
Active
L
H
L
Column
Write with Auto-Precharge
Read
L
L
L
Column
L
L
H
H
L
Column
Read with Auto-Precharge Active
Reserved
L
L
H
X
X
X
X
X
X
X
Column
L
H
H
X
X
X
X
X
X
H
X
H
X
X
X
X
X
X
X
No Operation
Any
Any
L
H
X
X
X
X
X
X
H
X
H
X
Device Deselect
H
X
X
X
X
H
L
X
Clock Suspend Mode Entry Active
X
4
Clock Suspend Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
Active
H
X
X
X
H
H
X
5
H
X
Power Down Mode Entry
Power Down Mode Exit
Idle/Active
H
L
L
X
X
X
X
X
X
X
X
6, 7
6, 7
H
L
Any (Power
Down)
H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the
Current State Truth Table.
2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1
selects bank 3.
3. Not applicable.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device
state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in
this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Clock Enable (CKE) Truth Table
CKE
Command
Current State
Action
Notes
Previous
Cycle
Current
Cycle
BA0,
BA1
CS
RAS
CAS
WE
A11 - A0
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
1
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
2
2
2
2
2
L
Self Refresh
L
L
L
L
X
X
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
X
X
H
L
ILLEGAL
L
X
X
H
L
X
X
X
X
X
X
H
L
Maintain Self Refresh
INVALID
H
L
X
H
H
L
1
2
2
Power Down mode exit, all banks idle
ILLEGAL
Power Down
L
L
X
H
L
Maintain Power Down Mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
3
3
3
Refer to the Idle State section of the
Current State Truth Table
L
L
L
X
X
CBR Refresh
L
L
L
OP Code
Mode Register Set
4
3
3
3
4
All Banks Idle
H
L
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State section of the
Current State Truth Table
L
L
L
L
L
L
X
X
Entry Self Refresh
Mode Register Set
Power Down
L
L
L
L
OP Code
X
X
X
X
X
X
X
X
X
4
5
Refer to operations in the Current State
Truth Table
H
H
X
X
X
X
Any State
other than
listed above
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE
(tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising
clock after CKE goes high.
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-
tion.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
29
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Current State Truth Table (Part 1 of 3)(See note 1)
Command
Current State
Action
Set the Mode Register
Notes
CS RAS CAS WE BA0,BA1
A11 - A0
Description
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
2
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh Start Auto or Self Refresh
2, 3
L
H
H
L
Precharge
No Operation
L
H
L
Row Address Bank Activate
Activate the specified bank and row
Idle
Row Active
Read
H
H
H
X
L
Column
Write w/o Precharge ILLEGAL
Read w/o Precharge ILLEGAL
4
4
L
H
H
X
L
Column
H
X
L
X
X
No Operation
No Operation
X
Device Deselect
Mode Register Set
No Operation or Power Down
ILLEGAL
5
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
Precharge
6
L
H
L
Row Address Bank Activate
ILLEGAL
4
H
H
H
X
L
Column
Write
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
7, 8
7, 8
L
H
H
X
L
Column
Read
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
Precharge Terminate Burst; Start the Precharge
L
H
H
L
L
H
L
Row Address Bank Activate
ILLEGAL
4
H
H
H
X
L
Column
Write
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Continue the Burst
8, 9
8, 9
L
H
H
X
L
Column
Read
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
X
Continue the Burst
OP Code
ILLEGAL
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
Precharge Terminate Burst; Start the Precharge
L
H
H
L
L
H
L
Row Address Bank Activate
ILLEGAL
4
Write
H
H
H
X
Column
Write
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Continue the Burst
8, 9
8, 9
L
H
H
X
Column
Read
H
X
X
X
No Operation
Device Deselect
X
Continue the Burst
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Current State Truth Table (Part 2 of 3)(See note 1)
Command
Current State
Action
Notes
CS RAS CAS WE BA0,BA1
A11 - A0
Description
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
ILLEGAL
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
4
4
4
4
Read with
Auto Pre-
charge
L
H
L
Row Address Bank Activate
H
H
H
X
L
Column
Write
L
H
H
X
L
Column
Read
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
4
4
4
4
L
H
L
Row Address Bank Activate
ILLEGAL
Writewith Auto
Precharge
H
H
H
X
L
Column
Write
ILLEGAL
L
H
H
X
L
Column
Read
ILLEGAL
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
Precharge No Operation; Bank(s) idle after tRP
L
H
H
L
L
H
L
Row Address Bank Activate
ILLEGAL
4
4
4
Precharging
H
H
H
X
L
Column
Write
ILLEGAL
L
H
H
X
L
Column
Read
ILLEGAL
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
ILLEGAL
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
4
4, 10
4
L
H
L
Row Address Bank Activate
ILLEGAL
Row
Activating
H
H
H
X
Column
Write
ILLEGAL
L
H
H
X
Column
Read
ILLEGAL
4
H
X
X
X
No Operation
Device Deselect
No Operation; Row Active after tRCD
No Operation; Row Active after tRCD
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
31
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Current State Truth Table (Part 3 of 3)(See note 1)
Command
Current State
Action
Notes
CS RAS CAS WE BA0,BA1
A11 - A0
Description
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
ILLEGAL
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
ILLEGAL
4
4
9
9
L
H
L
Row Address Bank Activate
Write
Recovering
H
H
H
X
L
Column
Write
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row Active after tDPL
No Operation; Row Active after tDPL
ILLEGAL
L
H
H
X
L
Column
Read
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
Write
Recovering
with
Auto Pre-
charge
L
H
H
L
Precharge
ILLEGAL
4
4
L
H
L
Row Address Bank Activate
ILLEGAL
H
H
H
X
L
Column
Write
ILLEGAL
4, 9
4, 9
L
H
H
X
L
Column
Read
ILLEGAL
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
ILLEGAL
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
L
H
L
Row Address Bank Activate
ILLEGAL
Refreshing
H
H
H
X
L
Column
Write
ILLEGAL
L
H
H
X
L
Column
Read
ILLEGAL
H
X
L
X
X
No Operation
Device Deselect
Mode Register Set
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
X
OP Code
L
L
H
L
X
BS
BS
BS
BS
X
X
X
Auto or Self Refresh ILLEGAL
L
H
H
L
Precharge
ILLEGAL
Mode
Register
Accessing
L
H
L
Row Address Bank Activate
ILLEGAL
H
H
H
X
Column
Write
ILLEGAL
L
H
H
X
Column
Read
ILLEGAL
H
X
X
X
No Operation
Device Deselect
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN
Parameter
Rating
-1.0 to +4.6
-1.0 to +4.6
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Units
V
Notes
Power Supply Voltage
Power Supply Voltage for Output
Input Voltage
1
1
1
1
1
1
1
1
V
V
VOUT
TA
Output Voltage
V
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
°C
°C
W
TSTG
PD
-55 to +150
1.0
IOUT
Short Circuit Output Current
50
mA
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0°C to 70°C)
Rating
Symbol
Parameter
Units
Notes
Min.
3.0
3.0
2.0
-1.0
2.4
—
Typ.
3.3
3.3
3.0
—
Max.
3.6
VDD
VDDQ
VIH
Supply Voltage
V
V
V
V
V
V
1
1
Supply Voltage for Output
Input High Voltage
3.6
VDD + 0.3
0.8
1, 2
VIL
Input Low Voltage
1, 3
VoH
VIL
Output Logic High Voltage
Output Logic LowVoltage
—
—
IoH = -2mA
IoL = 2mA
—
0.4
1. All voltages referenced to VSS and VSSQ
.
2. VIH (max) = VDD + 2.3V for pulse width ≤ 3ns.
3. VIL (min) = VSS - 2.0V for pulse width ≤ 3ns.
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ± 0.3V)
Symbol
Parameter
Min.
2.5
2.5
4.0
Typ
3.0
2.8
4.5
Max.
Units
Notes
Input Capacitance (A0-A11, BA0, BA1, CS, RAS, CAS, WE, CKE, DQM)
Input Capacitance (CK)
3.8
3.5
6.5
pF
pF
pF
CI
CO
Output Capacitance (DQ0 - DQ15)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
33
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
Symbol
Parameter
Min.
-1
Max.
+1
Units
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V
II(L)
µA
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ
IO(L)
VOH
VOL
-1
2.4
—
+1
—
µA
V
)
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
Output Level (LVTTL)
Output “L” Level Voltage (IOUT = +2.0mA)
0.4
V
DC Output Load Circuit
3.3 V
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
50pF
870Ω
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00B
05/01/06
®
IS42S16800A1
ISSI
dc
Operating, Standby, and Refresh Currents
(TA = 0 to +70°C)
Speed (3.3V)
Parameter
Symbol
ICC1
Test Condition
1 bank operation
tRC = tRC(min), tCK = min
Active-Precharge command cycling without
burst operation
Units
mA
Notes
1, 2, 3
-7
-75
Operating Current
95
85
CKE ≤ VIL(max), tCK = min,
ICC2P
ICC2PS
ICC2N
2.5
2.5
2.5
2.5
mA
mA
1
1
CS = VIH(min)
Precharge Standby Current
in Power Down Mode
CKE ≤ VIL(max), tCK = Infinity,
CS = VIH(min)
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
35
9
45
9
mA
mA
mA
mA
mA
1, 5
1, 7
Precharge Standby Current
in Non-Power Down Mode
ICC2NS CKE ≥ VIH(min), tCK = Infinity,
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
ICC3N
40
9
50
9
1, 5
No Operating Current
(Active state: 4 bank)
ICC3P CKE ≤ VIL(max), tCK = min,
1, 6
Operating Current (Burst
Mode)
tCK = min, Read/ Write command cycling,
Multiple banks active, gapless data, BL = 4
ICC4
90
120
1, 3, 4
tCK = min, tRC = tRC(min)
CBR command cycling
Auto (CBR) Refresh Current
Self Refresh Current
ICC5
ICC6
170
190
3
mA
mA
1
1
CKE ≤ 0.2V
3
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of
tCK and tRC. Input signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
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IS42S16800A1
ISSI
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A: AC measurements assume tT = 1.0ns.
6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
tT
Vtt = 1.4V
VIH
50Ω
Output
1.4V
VIL
tCKL
tCKH
Clock
Input
Zo = 50Ω
50pF
tSETUP
AC Output Load Circuit (A)
tHOLD
1.4V
Output
Zo = 50Ω
tOH
50pF
tAC
tLZ
AC Output Load Circuit (B)
1.4V
Output
36
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IS42S16800A1
ISSI
Clock and Clock Enable Parameters
-7
-75
Symbol
Parameter
Units Notes
Min.
7.0
7.5
—
Max.
1000
1000
—
Min.
7.5
10
Max.
1000
1000
—
tCK3
tCK2
Clock Cycle Time, CAS Latency = 3
Clock Cycle Time, CAS Latency = 2
Clock Access Time, CAS Latency = 3
Clock Access Time, CAS Latency = 2
Clock Access Time, CAS Latency = 3
Clock Access Time, CAS Latency = 2
Clock High Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAC3 (A)
tAC2 (A)
tAC3 (B)
tAC2 (B)
tCKH
—
1
1
2
2
—
—
—
—
—
5
—
5.4
6
—
5.4
—
—
2
2.5
2.5
1.5
0.8
0
—
tCKL
Clock Low Pulse Width
2
—
—
tCES
Clock Enable Set-up Time
1.5
1.0
0
—
—
tCEH
Clock Enable Hold Time
—
—
tSB
Power down mode Entry Time
Transition Time (Rise and Fall)
6
7.5
10
tT
0.3
8
0.5
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
-7
-75
Symbol
Parameter
Units Notes
Min.
1.5
0.8
1.5
0.8
16
Max.
—
Min.
1.5
0.8
1.5
0.8
20
Max.
—
tCS
tCH
Command Setup Time
ns
ns
ns
ns
Command Hold Time
—
—
tAS
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
—
—
tAH
—
—
tRCD
tRC
tRAS
tRP
tRRD
tCCD
—
—
ns
ns
ns
ns
ns
CK
1
1
1
1
1
Bank Cycle Time
54
—
67.5
45
—
Active Command Period
Precharge Time
36
100K
—
100K
—
16
20
Bank to Bank Delay Time
CAS to CAS Delay Time
12
—
15
—
1
—
1
—
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-7
-75
Symbol
tRSC
Parameter
Units
ns
Min.
12
Max.
—
Min.
15
Max.
—
Mode Register Set Cycle Time
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Rev. 00B
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IS42S16800A1
ISSI
Read Cycle
-7
-75
Symbol
Parameter
Units Notes
Min.
—
2.5
0
Max.
—
Min.
—
2.7
0
Max.
—
ns
ns
ns
ns
CK
1
tOH
Data Out Hold Time
Data Out to Low Impedance Time
—
—
2, 4
tLZ
tHZ
—
—
Data Out to High Impedance Time
DQM Data Out Disable Latency
3
6
3
7
3
tDQZ
2
—
2
—
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
-7
-75
Symbol
Parameter
Units Notes
Min.
—
Max.
64
Min.
—
Max.
64
tREF
Refresh Period
ms
CK
1
tSREX
Self Refresh Exit Time
1
—
1
—
1. 4096 auto refresh cycles.
Write Cycle
-7
-75
Symbol
Parameter
Units
Min.
1.5
0.8
12
Max.
—
Min.
1.5
0.8
15
Max.
—
tDS
tDH
tDPL
tWR
Data In Set-up Time
Data In Hold Time
ns
ns
ns
ns
—
—
Data input to Precharge
Write Recovery Time
—
—
12
—
15
—
Data In to Active Delay
CAS Latency = 3
tDAL3
5
—
5
—
CK
Data In to Active Delay
CAS Latency = 2
tDAL2
tDQW
4
0
—
—
4
0
—
—
CK
CK
DQM Write Mask Latency
38
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IS42S16800A1
ISSI
Clock Frequency and Latency
Symbol
fCK
Parameter
-7
143
7.0
3
-75
133
Units
MHz
Clock Frequency
Clock Cycle Time
CAS Latency
tCK
7.5
3
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
tAA
tRP
Precharge Time
RAS to CAS Delay
Bank Cycle Time
3
3
tRCD
tRC
3
3
9
9
tRAS
tDPL
tDAL
tRRD
tCCD
tWL
Minimum Bank Active Time
Data In to Precharge
6
6
2
2
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
5
5
2
2
1
1
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
2
2
1
1
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AC Parameters for Write Timing
\
40
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AC Parameters for Read Timing (3/3/3)
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AC Parameters for Read Timing (2/2/2)
\
42
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AC Parameters for Read Timing (3/2/2)
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AC Parameters for Read Timing (3/3/3)
\
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Mode Register Set
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Power-On Sequence and Auto Refresh (CBR)
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Clock Suspension / DQM During Burst Read
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Clock Suspension / DQM During Burst Write
\
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Power Down Mode and Clock Suspend
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Auto Refresh (CBR)
\
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Self Refresh (Entry and Exit)
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Random Row Read (Interleaving Banks) with Precharge
\
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Random Row Read (Interleaving Banks) with Auto-Precharge
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Random Row Write (Interleaving Banks) with Auto-Precharge
\
54
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Random Row Write (Interleaving Banks) with Precharge
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Read / Write Cycle
\
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Interleaved Column Read Cycle
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Auto Precharge after Read Burst
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Auto Precharge after Write Burst
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Burst Read and Single Write Operation
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CS Function (Only CS signal needs to be asserted at minimum rate)
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ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency
Speed(ns) Order Part No.
IS42S16800A1-7TL
Package
143 MHz
7
54-PinTSOPII,Lead-free
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PACKAGINGINFORMATION
ISSI
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Plastic TSOP (T - Type II)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Symbol Min
Max
Min
Max
Ref. Std.
Ref. Std.
No. Leads (N)
54
No. Leads (N)
86
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
A
A1
A2
b
C
D
E1
E
e
—
1.20
0.05 0.15
0.95 1.05
0.17 0.27
0.12 0.21
22.02 22.42
10.16 BSC
11.56 11.96
0.50 BSC
—
0.047
0.05 0.15
—
0.002 0.006
—
0.002 0.006
0.037 0.041
0.007 0.011
0.005 0.008
0.867 0.8827
0.400 BSC
—
—
0.30 0.45
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.80 BSC
0.012 0.018
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.031 BSC
0.455 0.471
0.020 BSC
L
0.40 0.60
0.016 0.024
L
0.40 0.60
0.80 REF
0.61 REF
0.016 0.024
0.031 REF
0.024 BSC
L1
ZD
α
—
—
—
—
L1
ZD
α
0.71 REF
0° 8°
0°
8°
0°
8°
0°
8°
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1
01/28/02
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