IS42S16800D-7TLI-TR [ISSI]
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, LEAD FREE, PLASTIC, TSOP2-54;
| 型号： | IS42S16800D-7TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, LEAD FREE, PLASTIC, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总62页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S81600D
IS42S16800D
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
JULY 2008
OVERVIEW
FEATURES
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
VDD
3.3V 3.3V
VDDQ
IS42S81600D
4M x8x4 Banks
54-pin TSOPII
IS42S16800D
2M x16x4 Banks
54-pin TSOPII
54-ballBGA
IS42S81600D
IS42S16800D
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
KEY TIMING PARAMETERS
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
Parameter
-6
-7
-75E Unit
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6
8
7
10
—
7.5
ns
ns
• Burst read/write and burst read/single write
operations capability
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166
125
143
100
—
133
Mhz
Mhz
• Burst termination by burst stop and precharge
command
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
• Industrial Temperature Availability
• Lead-freeAvailability
5.4
6.5
5.4
6.5
—
6.5
ns
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. E
07/28/08
IS42S81600D, IS42S16800D
DEVICE OVERVIEW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tionenabled. Prechargeonebankwhileaccessingoneofthe
otherthreebankswillhidetheprechargecyclesandprovide
seamless,high-speed,random-accessoperation.
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nizedas4,096rowsby512columnsby16bitsor4,096rows
by 1,024 columns by 8 bits.
SDRAMreadandwriteaccessesareburstorientedstartingat
aselectedlocationandcontinuingforaprogrammednum-
ber of locations in a programmed sequence. The registra-
tionofanACTIVEcommandbeginsaccesses, followedby
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
The128MbSDRAMincludesanAUTOREFRESHMODE,
and a power-saving, power-down mode. All signals are
registeredonthepositiveedgeoftheclocksignal,CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation,theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableREADorWRITEburstlengthsconsistof1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTIONS
A0-A11
A0-A9
BA0, BA1
DQ0 to DQ7
CLK
Row Address Input
Column Address Input
Bank Select Address
Data I/O
WE
WriteEnable
DQM
VDD
Data Input/Output Mask
Power
Vss
VDDQ
VssQ
NC
Ground
System Clock Input
Clock Enable
Power Supply for I/O Pin
Ground for I/O Pin
NoConnection
CKE
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
CAS
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. E
07/28/08
IS42S81600D, IS42S16800D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
V
DD
VSS
LDQM
WE
CAS
RAS
CS
NC
UDQM
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQML
DQMH
VDD
x16 Lower Byte, Input/Output Mask
x16 Upper Byte, Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
NoConnection
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
CAS
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
PIN CONFIGURATION
54-ball fBGA for x16 (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
PACKAGE CODE:
B
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8 NC VSS
DQMH CLK CKE
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
G
H
J
NC
A8
A11
A7
A9
A6
A4
A0
A3
A1
A10
VSS
A5
A2 VDD
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQML
DQMH
VDD
x16 Lower Byte Input/Output Mask
x16 Upper Byte Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
NoConnection
CAS
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5
Rev. E
07/28/08
IS42S81600D, IS42S16800D
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
command(row-addressA0-A11)andREAD/WRITEcommand(columnaddressA0-A9
(x8), or A0-A8 (x16); with A10 defining auto precharge) to select one location out of the
memoryarrayintherespectivebank. A10issampledduringaPRECHARGEcommand
to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTERcommand.
BA0, BA1
CAS
Input Pin
Input Pin
Input Pin
BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE, READ, WRITEor
PRECHARGEcommandisbeingapplied.
CAS, inconjunctionwiththeRASand WE, formsthedevicecommand. Seethe
"CommandTruthTable"fordetailsondevicecommands.
CKE
TheCKEinputdetermineswhethertheCLKinputisenabled. Thenextrisingedgeofthe
CLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW. WhenCKEisLOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK
Input Pin
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
areacquiredinsynchronizationwiththerisingedgeofthispin.
CS
TheCSinputdetermineswhethercommandinputisenabledwithinthedevice.
Command input is enabled whenCSisLOW, anddisabledwithCSisHIGH. Thedevice
remains in the previous state when CS is HIGH.
DQML,
DQMH
Input Pin
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQMLandDQMHcontroltheoutputbuffer. WhenDQMLorDQMHisLOW, the
correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds toOE
inconventionalDRAMs.Inwritemode,DQMLandDQMHcontroltheinputbuffer.When
DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot
bewrittentothedevice.ForIS42S16800Donly.
DQM
Input Pin
For IS42S81600D only.
DQ0-DQ7 or
DQ0-DQ15
Input/Output
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS
Input Pin
Input Pin
RAS,inconjunctionwithCASandWE,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
WE
WE,inconjunctionwithRASandCAS,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
VDDQ
VDD
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
VDDQ istheoutputbufferpowersupply.
VDD isthedeviceinternalpowersupply.
VSSQ istheoutputbufferground.
VSSQ
VSS
VSS isthedeviceinternalground.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
InputsA0-A9(x8);A0-A8(x16)providesthestartingcolumn
location. WhenA10isHIGH,thiscommandfunctionsasan
AUTOPRECHARGEcommand. Whentheautoprecharge
is selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’sreaddataissubjectto thelogiclevel onthe
DQM inputs two clocks earlier. When a given DQM signal
wasregisteredHIGH,thecorrespondingDQ’swillbeHigh-
Z two clocks later. DQ’s will provide valid data when the
DQM signal was registered LOW.
PRECHARGEfunctioninconjunctionwithaspecificREAD
orWRITEcommand. ForeachindividualREADorWRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burstmode.UponcompletionoftheREADorWRITEburst,
a precharge of the bank/row that is addressed is automati-
callyperformed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(tRC)is
required for a single refresh operation, and no other com-
mandscanbeexecutedduringthisperiod. Thiscommandis
executed at least 4096 times for every 64ms. During an
AUTOREFRESHcommand,addressbitsare“Don’tCare”.
This command corresponds to CBR Auto-refresh.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A9
(x8); A0-A8 (x16). Whether or not AUTO-PRECHARGE is
used is determined by A10.
BURST TERMINATE
TheBURSTTERMINATEcommandforciblyterminatesthe
burst read and write operations by truncating either fixed-
length or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMI-
NATE.
Therowbeingaccessedwillbeprechargedattheendofthe
WRITE burst, if AUTO PRECHARGE is selected. If AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
Amemoryarrayiswrittenwithcorrespondinginputdataon
DQ’sandDQMinputlogiclevelappearingatthesametime.
Data will be written to memory when DQM signal is LOW.
When DQM is HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commandsfrombeingregisteredduringidleorwaitstates.
PRECHARGE
ThePRECHARGEcommandisusedtodeactivatetheopen
row in a particular bank or the open row in all banks. BA0,
BA1canbeusedtoselectwhichbankisprechargedorthey
aretreatedas“Don’tCare”. A10determinedwhetheroneor
all banks are precharged. After executing this command,
thenextcommandfortheselectedbank(s)isexecutedafter
passage of the period tRP, which is the period required for
bankprecharging. Onceabankhasbeenprecharged,itis
intheidlestateandmustbeactivatedpriortoanyREADor
WRITE commands being issued to that bank.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
registerisloadedfromA0-A11. Thiscommandcanonlybe
issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
AUTO PRECHARGE
TheAUTOPRECHARGEfunctionensuresthattheprecharge
is initiated at the earliest valid stage within a burst. This
functionallowsforindividual-bankprechargewithoutrequir-
ing an explicit command. A10 to enable the AUTO
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7
Rev. E
07/28/08
IS42S81600D, IS42S16800D
COMMAND TRUTH TABLE
CKE
A11
Function
n – 1
H
n
×
×
×
×
×
×
×
×
×
×
H
L
×
CS
H
L
RAS
×
CAS
×
WE
×
BA1
×
BA0
×
A10 A9 - A0
Device deselect (DESL)
Nooperation (NOP)
Burst stop (BST)
Read
×
×
×
L
×
×
×
V
V
V
V
V
×
×
×
×
V
H
H
H
H
H
H
H
L
H
H
L
H
L
×
×
H
L
×
×
H
L
H
H
L
V
V
V
V
V
V
×
V
V
V
V
V
V
×
Readwithautoprecharge
Write
H
L
L
H
L
H
L
L
Write with auto precharge
Bank activate (ACT)
H
L
L
L
H
V
L
H
L
H
H
H
L
H
L
Precharge select bank (PRE) H
L
L
Precharge all banks (PALL)
CBRAuto-Refresh(REF)
Self-Refresh(SELF)
H
H
H
H
L
L
L
H
×
×
L
L
L
H
H
L
×
×
L
L
L
×
×
Mode register set (MRS)
L
L
L
L
L
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
DQM TRUTH TABLE
CKE
DQM
Function
n-1
H
n
×
×
×
×
×
×
U
L
L
L
Data write / output enable
Data mask / output disable
H
H
L
H
×
L
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
H
H
×
H
H
×
H
H
×
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CKE TRUTH TABLE
CKE
CurrentState/Function
n – 1 n
CS
×
RAS
CAS WE
Address
Activating Clock suspend mode entry
Any Clock suspend mode
Clock suspend mode exit
Auto refresh command Idle (REF)
Self refresh entry Idle (SELF)
Power down entry Idle
H
L
L
L
×
×
×
L
L
×
×
×
×
×
H
H
×
×
×
×
×
×
×
×
×
×
L
L
×
L
H
H
L
×
H
H
H
L
L
L
×
Self refresh exit
L
L
H
H
L
H
H
×
H
×
H
×
×
×
Power down exit
L
H
×
×
×
×
×
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. E
07/28/08
IS42S81600D, IS42S16800D
FUNCTIONAL TRUTH TABLE
Current State
CS
H
L
RAS CAS WE
Address
Command
DESL
Action
Idle
X
H
H
H
H
L
X
H
H
L
X
H
L
X
Nop or Power Down(2)
Nop or Power Down(2)
Nop or Power Down
ILLEGAL (3)
X
NOP
L
X
BST
L
H
L
BA, CA, A10
A, CA, A10
BA, RA
BA, A10
X
READ/READA
WRIT/WRITA
ACT
L
L
ILLEGAL(3)
L
H
H
L
H
L
Row activating
L
L
PRE/PALL
REF/SELF
MRS
Nop
L
L
H
L
Auto refresh or Self-refresh(4)
Mode register set
Nop
L
L
L
OC, BA1=L
X
Row Active
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
DESL
X
NOP
Nop
L
X
BST
Nop
(5)
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
READ/READA
WRIT/WRITA
ACT
Begin read
(5)
L
L
Begin write
ILLEGAL (3)
L
H
H
H
L
L
L
PRE/PALL
Precharge
Precharge all banks(6)
L
L
L
L
X
L
L
X
H
L
X
REF/SELF
MRS
ILLEGAL
ILLEGAL
OC, BA
X
Read
H
X
DESL
Continue burst to end to
Row active
L
H
H
H
X
NOP
Continue burst to end Row
Row active
L
L
H
H
H
L
L
X
BST
Burst stop, Row active
Terminate burst,
begin new read
H
BA, CA, A10
READ/READA
(7)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst,
begin write
(7,8)
L
L
L
L
H
H
H
L
BA, RA
ACT
ILLEGAL (3)
BA, A10
PRE/PALL
Terminate burst
Precharging
L
L
H
L
L
X
L
L
X
H
L
X
REF/SELF
MRS
ILLEGAL
ILLEGAL
OC, BA
X
Write
X
DESL
Continue burst to end
Write recovering
L
H
H
H
X
NOP
Continue burst to end
Write recovering
L
L
H
H
H
L
L
X
BST
Burst stop, Row active
H
BA, CA, A10
READ/READA
Terminate burst, start read :
Determine AP (7,8)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, new write :
Determine AP (7)
L
L
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
RA ACT
PRE/PALL
REF/SELF
MRS
ILLEGAL (3)
(9)
Terminate burst Precharging
ILLEGAL
H
L
L
OC, BA
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
RAS CAS WE
Address
Command
Action
Read with auto
Precharging
H
×
×
×
×
DESL
Continue burst to end, Precharge
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
H
L
H
L
x
NOP
Continue burst to end, Precharge
ILLEGAL
ILLEGAL (11)
ILLEGAL (11)
ILLEGAL (3)
×
BST
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
L
PRE/PALL
REF/SELF
MRS
ILLEGAL (11)
L
H
L
ILLEGAL
L
L
OC, BA
×
ILLEGAL
Write with Auto
Precharge
×
×
×
DESL
Continue burst to end, Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end, Write
recovering with auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
×
BST
ILLEGAL
ILLEGAL(11)
ILLEGAL (11)
ILLEGAL (3,11)
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL (3,11)
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Precharging
×
H
H
H
H
L
×
H
H
L
×
H
L
×
DESL
Nop, Enter idle after tRP
Nop, Enter idle after tRP
Nop, Enter idle after tRP
ILLEGAL (3)
ILLEGAL (3)
ILLEGAL(3)
×
NOP
×
BST
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
L
PRE/PALL
REF/SELF
MRS
Nop Enter idle after tRP
ILLEGAL
L
H
L
L
L
OC, BA
×
ILLEGAL
Row Activating
×
H
H
H
H
L
×
H
H
L
×
H
L
DESL
Nop, Enter bank active after tRCD
Nop, Enter bank active after tRCD
Nop, Enter bank active after tRCD
ILLEGAL (3)
ILLEGAL (3)
ILLEGAL (3,9)
×
NOP
×
BST
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
READ/READA
WRIT/WRITA
ACT
L
H
H
L
H
L
L
PRE/PALL
REF/SELF
MRS
ILLEGAL (3)
L
H
L
ILLEGAL
L
L
OC, BA
ILLEGAL
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. E
07/28/08
IS42S81600D, IS42S16800D
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
RAS CAS WE
Address
Command
DESL
Action
Write Recovering
×
H
H
H
H
L
×
H
H
L
×
H
L
×
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read (8)
×
NOP
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
Begin new write
ILLEGAL (3)
ILLEGAL (3)
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF/SELF
MRS
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Write Recovering
with Auto
×
×
H
H
L
×
H
L
×
DESL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL(3,8,11)
ILLEGAL (3,11)
ILLEGAL (3,11)
H
H
H
H
L
×
NOP
Precharge
×
BST
H
L
BA, CA, A10
READ/READA
WRIT/WRITA
ACT
L
BA, CA, A10
H
H
L
H
L
BA, RA
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL (3,11)
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Refresh
×
×
H
L
×
×
H
L
×
DESL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
H
H
H
L
×
NOP/BST
READ/READA
WRIT/WRITA
ACT
BA, CA, A10
L
BA, CA, A10
ILLEGAL
H
H
L
H
L
BA, RA
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OC, BA
ILLEGAL
Mode Register
Accessing
×
×
H
H
L
×
H
L
×
DESL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
H
H
H
L
×
NOP
×
BST
×
×
BA, CA, A10
BA, RA
READ/WRITE
ILLEGAL
×
ACT/PRE/PALL ILLEGAL
REF/MRS
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
Current State
Self-Refresh(S.R.)
Operation
n-1
H
L
n
X
H
H
H
H
L
CS
X
H
L
RAS
X
X
H
H
L
CAS
X
X
H
L
WE Address
INVALID,CLK(n-1)wouldexitS.R.
Self-RefreshRecovery(2)
Self-RefreshRecovery(2)
Illegal
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
L
X
L
L
X
Illegal
L
L
X
X
X
H
L
X
MaintainS.R.
L
X
H
L
X
X
H
H
L
X
Self-RefreshRecovery Idle After tRC
H
H
H
H
H
H
H
H
L
H
H
H
H
L
X
Idle After tRC
Illegal
X
L
X
Illegal
L
X
X
H
L
X
Beginclocksuspendnextcycle(5)
H
L
X
H
H
L
X
Beginclocksuspendnextcycle(5)
L
X
Illegal
L
L
X
Illegal
L
L
X
X
X
X
X
X
X
X
H
L
X
Exitclocksuspendnextcycle(2)
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
H
L
X
Maintainclocksuspend
L
X
Power-Down(P.D.)
BothBanksIdle
INVALID,CLK(n-1)wouldexitP.D.
EXITP.D.-->Idle(2)
H
L
X
H
L
—
X
Maintainpowerdownmode
L
X
RefertooperationsinOperativeCommandTable
RefertooperationsinOperativeCommandTable
RefertooperationsinOperativeCommandTable
Auto-Refresh
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
—
—
L
—
L
L
X
RefertooperationsinOperativeCommandTable
RefertooperationsinOperativeCommandTable
RefertooperationsinOperativeCommandTable
RefertooperationsinOperativeCommandTable
Self-Refresh(3)
L
L
L
Op-Code
H
L
X
H
L
X
X
H
L
X
X
X
H
L
—
L
—
L
L
—
L
L
L
X
RefertooperationsinOperativeCommandTable
L
L
L
L
Op-Code
(3)
Power-Down
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Anystate
RefertooperationsinOperativeCommandTable
Beginclocksuspendnextcycle(4)
Exitclocksuspendnextcycle
H
H
L
otherthan
listedabove
H
L
Maintainclocksuspend
L
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSRX is not satisfied.
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. E
07/28/08
IS42S81600D, IS42S16800D
STATE DIAGRAM
Self
Refresh
SELF
SELF exit
REF
Mode
Register
Set
MRS
CBR (Auto)
Refresh
IDLE
CKE
CKE
ACT
Power
Down
CKE
Active
Power
Down
Row
Active
CKE
BST
Write
BST
Read
Write
Read
Read
CKE
CKE
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRITE
Write
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual Input
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
VDD MAX
VDDQMAX
VIN
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
InputVoltage
OutputVoltage
AllowablePowerDissipation
OutputShortedCurrent
–0.5 to +4.6
–0.5 to +4.6
–0.5 to VDD + 0.5
–1.0 to VDDQ + 0.5
1
V
V
V
VOUT
V
PD MAX
ICS
W
mA
°C
50
0 to +70
–40 to +85
TOPR
OperatingTemperature
Com.
Ind.
TSTG
StorageTemperature
–55 to +150
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
DC RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
3.0
3.0
2.0
-0.3
3.3
3.3
—
3.6
3.6
V
V
V
V
VDDQ
I/O Supply Voltage
Input High Voltage
Input Low Voltage
(1)
VIH
VDDQ + 0.3
+0.8
(2)
VIL
—
Note:
1. VIH (max) = VDDQ +2V (PULSE WIDTH < 3NS).
2. VIL (min) = -2V (PULSE WIDTH < 3NS).
3. All voltages are referenced to Vss.
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ = 3.3 0.3V)
Symbol
Parameter
Min.
Max.
-7
Unit
-6
-75E
CIN1
CIN2
CI/O
Input Capacitance: CLK
Input Capacitance:All other input pins
DataInput/OutputCapacitance:I/Os
2.5
2.5
4.0
3.5
3.8
6.5
4.0
5.0
6.5
4.0
5.0
6.5
pF
pF
pF
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15
Rev. E
07/28/08
IS42S81600D, IS42S16800D
DC ELECTRICAL CHARACTERISTICS 1 (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
TestCondition
-6
120
140
2
-7
100
120
2
-75E Unit
mA
I
DD1(1)
OperatingCurrent
Onebankactive,CL=3,BL=1,
x8
x16
tCLK =tCLK (min),tRC =tRC (min)
120 mA
IDD2P
PrechargeStandbyCurrent
(InPower-DownMode)
CKE≤VIL
(MAX),tCK =15ns
x8 / x16
2
mA
I
DD2PS
PrechargeStandbyCurrent
(InPower-DownMode)
CKE≤VIL
(
MAX),CLK≤VIL
(
MAX
)
x8/x16
x8/x16
1
1
1
mA
I
DD2N(2)
PrechargeStandbyCurrent
(InNonPower-DownMode)
PrechargeStandbyCurrent
(InNonPower-DownMode)
ActiveStandbyCurrent
CS ≥Vcc-0.2V,CKE≥ VIH
CK =15ns
CS ≥Vcc-0.2V,CKE≥ VIH
CKE≤VIL
CS ≥Vcc-0.2V,CKE≥ VIH
CK =15ns
CS ≥Vcc-0.2V,CKE≥ VIH
CKE≤VIL
All banksactive,BL=4,CL=3,
(MIN
)
25
25
25 mA
15 mA
30 mA
20 mA
t
IDD2NS
(MIN) or
x8/x16
x8/x16
x8/x16
15
30
20
15
30
20
(MAX),Allinputsstable
I
DD3N(2)
(MIN
)
(InNonPower-DownMode)
ActiveStandbyCurrent
t
IDD3NS
(MIN) or
(InNonPower-DownMode)
OperatingCurrent
(MAX),Allinputsstable
IDD4
x8
x16
170
180
180
2
120
130
160
2
mA
130 mA
mA
tCK =tCK (min)
IDD5
Auto-RefreshCurrent
Self-RefreshCurrent
tRC=tRC (min),tCLK =tCLK (min)
x8
IDD6
CKE≤ 0.2V
x8 / x16
2
mA
Notes:
1. IDD (MAX) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
DC ELECTRICAL CHARACTERISTICS 2 (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
TestCondition
Min
Max
Unit
IIL
InputLeakageCurrent
0V ≤Vin≤Vcc,withpinsotherthan
thetestedpinat0V
-5
5
μA
I
OL
OH
OL
OutputLeakageCurrent
OutputHighVoltageLevel
OutputLowVoltageLevel
Outputisdisabled,0V ≤Vout≤Vcc,
-5
2.4
—
5
μA
V
V
IOH = -2mA
OL = 2mA
—
V
I
0.4
V
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
(1,2,3)
AC ELECTRICAL CHARACTERISTICS
-6
-7
-75E
Min.
Symbol Parameter
Min.
Max.
Min.
Max.
Max.
Units
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
6
8
—
—
7
10
—
—
—
7.5
—
—
ns
ns
tAC3
tAC2
Access Time From CLK
CAS Latency = 3
CAS Latency = 2
—
—
5.4
6.5
—
—
5.4
6.5
—
—
5.4
6.5
ns
ns
tCHI
tCL
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
2.5
2.5
—
—
2.5
2.5
—
—
2.5
2.5
—
—
ns
ns
tOH3
tOH2
CAS Latency = 3
CAS Latency = 2
2.7
2.7
—
—
2.7
2.7
—
—
—
2.7
—
—
ns
ns
tLZ
Output LOW Impedance Time
Output HIGH Impedance Time
Input Data Setup Time(2)
Input Data Hold Time(2)
Address Setup Time(2)
Address Hold Time(2)
CKE Setup Time(2)
CKE Hold Time(2)
Command Setup Time (CS, RAS, CAS, WE, DQM)(2)
Command Hold Time (CS, RAS, CAS, WE, DQM)(2)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
0
—
5.4
—
0
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
67.5
45
—
5.4
—
0
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
67.5
45
—
5.4
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHZ
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
60
tDS
tDH
—
—
—
tAS
—
—
—
tAH
—
—
—
tCKS
tCKH
tCS
—
—
—
—
—
—
—
—
—
tCH
—
—
—
tRC
—
—
—
tRAS
tRP
42
100K
—
100K
—
100K
—
Command Period (PRE to ACT)
18
20
20
tRCD
tRRD
tDPL
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
18
—
20
—
20
—
12
—
14
—
15
—
Input Data To Precharge
Command Delay time
12
—
14
—
15
—
tDAL
Input Data To Active / Refresh
27
—
35
—
35
—
ns
Command Delay time (During Auto-Precharge)
tMRD
tDDE
tSRX
tT
Mode Register Program Time
Power Down Exit Setup Time
Self-Refresh Exit Time
12
6
—
—
—
10
64
15
7.5
7.5
1
—
—
—
10
64
15
7.5
7.5
1
—
—
—
10
64
ns
ns
ns
ns
ms
6
Transition Time
1
tREF
Refresh Cycle Time (4096)
—
—
—
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming. RiseandfalltimesaremeasuredbetweenVIH(min.)andVIL (max).
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. E
07/28/08
IS42S81600D, IS42S16800D
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
UNITS
—
—
Clock Cycle Time
6
7
7.5
ns
Operating Frequency (CAS Latency = 3)
166
143
133
MHz
tCAC
tRCD
tRAC
tRC
CAS Latency
3
3
3
3
3
3
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
Active Command To Read/Write Command Delay Time
RAS Latency (tRCD + tCAC)
CAS Latency = 3
6
6
6
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
10
7
10
7
10
7
tRAS
tRP
3
3
3
tRRD
tCCD
2
2
2
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
1
tDPL
tDAL
Input Data To Precharge Command Delay Time
2
5
2
5
2
5
cycle
cycle
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
tRBD
tWBD
tRQL
tWDL
Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 3
(Read)
3
0
3
0
3
0
3
0
3
0
3
0
cycle
cycle
cycle
cycle
Burst Stop Command To Input in Invalid Delay Time
(Write)
PrechargeCommandToOutputinHIGH-ZDelayTime
(Read)
CAS Latency = 3
Precharge Command To Input in Invalid Delay Time
(Write)
tPQL
tQMD
tDMD
tMRD
LastOutputToAuto-PrechargeStartTime(Read)
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
CAS Latency = 3
-2
2
–2
2
-2
2
cycle
cycle
cycle
cycle
0
0
0
Mode Register Set To Command Delay Time
2
2
2
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
AC TEST CONDITIONS
Input Load
Output Load
t
CK
t
CHI
tCL
3.0V
1.4V
1.4V
CLK
50Ω
0V
Z = 50Ω
t
CS
t
CH
Output
3.0V
1.4V
50 pF
INPUT
0V
t
AC
t
OH
OUTPUT
1.4V
1.4V
AC TEST CONDITIONS
Parameter
Rating
AC Input Levels
Input Rise and Fall Times
0V to 3.0V
1 ns
Input Timing Reference Level
OutputTimingMeasurementReferenceLevel
1.4V
1.4V
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. E
07/28/08
IS42S81600D, IS42S16800D
Initialization
FUNCTIONAL DESCRIPTION
SDRAMs must be powered up and initialized in a
predefinedmanner.
The128MbSDRAMsarequad-bankDRAMswhichoperate
at3.3Vandincludeasynchronousinterface(allsignalsare
registered on the positive edge of the clock signal, CLK).
Each of the 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits or 4,096 rows by 1,024
columns by 8 bits.
The128MSDRAMisinitializedafterthepowerisappliedto
VDD and VDDQ (simultaneously) and the clock is stable with
DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or aNOP. The COMMAND
INHIBITorNOPmaybeappliedduringthe100usperiodand
should continue at least through the end of the period.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVEcommandwhichisthenfollowedbyaREADorWRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
With at least one COMMAND INHIBIT or NOP command
havingbeenapplied,aPRECHARGEcommandshouldbe
appliedoncethe100µsdelayhasbeensatisfied. Allbanks
mustbeprecharged. Thiswillleaveallbanksinanidlestate
after which at least two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is then ready for mode register programming.
beaccessed(BA0andBA1selectthebank,A0-A11selecttherow)
.
TheaddressbitsA0-A9 (x8);A0-A8(x16)registeredcoincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The mode register should be loaded prior to applying any
operational command because it will power up in an un-
known state.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
INITIALIZE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
tCH
To+1
tCL
Tp+1
Tp+2
Tp+3
tCK
CLK
CKE
tCKS tCKH
tCMH tCMS
tCMH tCMS
PRECHARGE
tCMH tCMS
AUTO
AUTO
Load MODE
REGISTER
COMMAND
NOP
NOP
NOP
NOP
ACTIVE
REFRESH
REFRESH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
tAS tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
tAS tAH
BA0, BA1
DQ
CODE
tRP
tRC
tRC
tMRD
T
Power-up: VCC
and CLK stable all banks
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
DON'T CARE
T = 100µs Min.
Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.
Integrated Silicon Solution, Inc. — www.issi.com
21
Rev. E
07/28/08
IS42S81600D, IS42S16800D
AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
t
CK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
tRP
tRC
tRC
DON'T CARE
Notes:
1. CAS latency = 2, 3
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
t
CH
t
CL
CLK
CKE
tCKS
t
CKH
t
CKS
≥ tRAS
tCKS
tCMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
High-Z
tRP
t
SRX
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
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23
Rev. E
07/28/08
IS42S81600D, IS42S16800D
REGISTER DEFINITION
Mode Register
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst(sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operatingmodeandawriteburstmode,asshowninMODE
REGISTERDEFINITION.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiatingthesubsequentoperation.Violatingeitherofthese
requirements will result in unspecified operation.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
All Other States Reserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
1
24
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
BURST LENGTH
ReadandwriteaccessestotheSDRAMareburstoriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burstisavailableforthesequentialtype.Thefull-pageburst
is used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x16)
whentheburstlengthissettotwo;byA2-A8(x16)whenthe
burstlengthissettofour;andbyA3-A8(x16)whentheburst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
withintheblock.Full-pageburstswrapwithinthepageifthe
boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Reservedstatesshouldnotbeused,asunknownoperation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
Theorderingofaccesseswithinaburstisdeterminedbythe
burstlength,thebursttypeandthestartingcolumnaddress,
as shown in BURST DEFINITION table.
BURST DEFINITION
Burst
StartingColumn
Address
OrderofAccessesWithinaBurst
Length
Type=Sequential
Type=Interleaved
A 0
2
4
0
1
0-1
1-0
0-1
1-0
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
A 1
0
A 0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotSupported
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
1
0
1
1
Full
Page
(y)
n=A0-A7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn-1,
(location0-y)
Cn…
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25
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CAS Latency
Operating Mode
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
ThenormaloperatingmodeisselectedbysettingM7andM8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
If a READ command is registered at clock edge n, and the
latencyism clocks, thedatawillbeavailablebyclockedge
n+m.TheDQswillstartdrivingasaresultoftheclockedge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
commandisregisteredatT0andthelatencyisprogrammed
totwoclocks,theDQswillstartdrivingafterT1andthedata
willbevalidbyT2,asshowninCASLatencydiagrams.The
AllowableOperatingFrequencytableindicatestheoperat-
ing frequencies at which each CAS latency setting can be
used.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
appliestobothREADandWRITEbursts;whenM9=1, the
programmedburstlengthappliestoREADbursts,butwrite
accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
Reservedstatesshouldnotbeusedasunknownoperationor
incompatibility with future versions may result.
-6
125
100
133
166
143
—
-7
-75E
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeanyREADorWRITEcommandscanbeissuedtoa
bankwithintheSDRAM,arowinthatbankmustbe“opened.”
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank).
CLK
HIGH
CKE
CS
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. Minimum tRCD should be
dividedbytheclockperiodandroundeduptothenextwhole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a tRCD specification of 18ns
with a 125 MHz clock (8ns period) results in 2.25 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The
sameprocedureisusedtoconvertotherspecificationlimits
from time units to clock cycles).
RAS
CAS
WE
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
A subsequent ACTIVE command to a different row in the
samebankcanonlybeissuedafterthepreviousactiverow
hasbeen“closed”(precharged).Theminimumtimeinterval
betweensuccessiveACTIVEcommandstothesamebank
is defined by tRC.
A subsequent ACTIVE command to another bank can be
issuedwhilethefirstbankisbeingaccessed, whichresults
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by tRRD.
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
tRCD
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
27
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READS
READ COMMAND
READburstsareinitiatedwithaREADcommand,asshown
in the READ COMMAND diagram.
CLK
Thestartingcolumnandbankaddressesareprovidedwiththe
READ command, and auto precharge is either enabled or
disabledforthatburstaccess.Ifautoprechargeisenabled,the
row being accessed is precharged at the completion of the
burst.ForthegenericREADcommandsusedinthefollowing
illustrations, auto precharge is disabled.
HIGH
CKE
CS
RAS
During READ bursts, the valid data-out element from the
startingcolumnaddresswillbeavailablefollowingtheCAS
latencyaftertheREADcommand. Eachsubsequentdata-
outelementwillbevalidbythenextpositiveclockedge.The
CAS Latency diagram shows general timing
for each possible CAS latency setting.
CAS
WE
Upon completion of a burst, assuming no other commands
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
Data from any READ burst may be truncated with a subse-
quentREADcommand, anddatafromafixed-lengthREAD
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained.Thefirstdataelementfromthenewburstfollows
eitherthelastelementofacompletedburstorthelastdesired
data element of a longer burst which is being truncated.
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note: A9 is "Don't Care" for x16.
ThenewREADcommandshouldbeissuedxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Consecutive READ Bursts for CAS latencies of
twoandthree;dataelementn+3iseitherthelastofaburst
of four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architec-
ture. AREADcommandcanbeinitiatedonanyclockcycle
following a previous READ command. Full-speed random
readaccessescanbeperformedtothesamebank,asshown
in Random READ Accesses, or each subsequent READ
may be performed to a different bank.
The DQM input is used to avoid I/O contention, as shown
in Figures RW1 and RW2. The DQM signal must be
asserted (HIGH) at least three clocks prior to the WRITE
command(DQMlatencyistwoclocksforoutputbuffers)to
suppress data-out from the READ. Once the WRITE com-
mandisregistered,theDQswillgoHigh-Z(orremainHigh-
Z), regardless of the state of the DQM signal, provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQMwasLOWduringT4inFigureRW2,thentheWRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediatelyfollowingthelast(orlastdesired)dataelement
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possi-
bility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a
single-cycledelayshouldoccurbetweenthelastreaddata
and the WRITE command.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to
ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby, ortruncated
with, aPRECHARGEcommandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the
samebank.ThePRECHARGEcommandshouldbeissued
xcyclesbeforetheclockedgeatwhichthelastdesireddata
elementisvalid,wherexequalstheCASlatencyminusone.
ThisisshownintheREADtoPRECHARGEdiagramforeach
28
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
possible CAS latency; data elementn + 3 is either the last of
a burst of four or the last desired of a longer burst. Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met. Note that part
of the row precharge time is hidden during the access of the
last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with
auto precharge. The disadvantage of the PRECHARGE
commandisthatitrequiresthatthecommandandaddress
buses be available at the appropriate time to issue the
command;theadvantageofthePRECHARGEcommandis
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
providedthatautoprechargewasnotactivated.TheBURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possibleCASlatency;dataelementn+3isthelastdesired
data element of a longer burst.
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29
Rev. E
07/28/08
IS42S81600D, IS42S16800D
RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
tHZ
DOUT n+1
DOUT n+2
DOUT
n
DIN b
CAS Latency - 2
tDS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
tHZ
DOUT
n
DIN
b
CAS Latency - 3
tDS
DON'T CARE
30
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
CAS Latency - 3
DON'T CARE
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31
Rev. E
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IS42S81600D, IS42S16800D
RANDOM READ ACCESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
D
OUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
32
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
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IS42S81600D, IS42S16800D
READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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33
Rev. E
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IS42S81600D, IS42S16800D
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
tLZ
tOH
tOH
tOH
tOH
t
OH
DQ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
DOUT
b
t
AC
t
AC
t
AC
tAC
t
AC
t
AC
t
t
t
t
RCD - BANK 0
RRD
CAS Latency - BANK 0
t
RP - BANK 0
tRCD - BANK 0
t
RCD - BANK 3
CAS Latency - BANK 3
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
34
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CK
t
CL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
AC
tAC
t
AC
t
AC
tAC
t
AC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
DQ
t
LZ
t
OH
tOH
tOH
tOH
tOH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
35
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
tAC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
tLZ
tLZ
t
HZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
36
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
RQL
High-Z
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
t
RQL
High-Z
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
37
Rev. E
07/28/08
IS42S81600D, IS42S16800D
An example is shown in WRITE to WRITE diagram. Data n
+ 1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITEcommand.Full-speedrandomwriteaccesseswithin
a page can be performed to the same bank, as shown in
Random WRITE Cycles, or each subsequent WRITE may
be performed to a different bank.
WRITES
WRITE bursts are initiated with a WRITE command, as
showninWRITECommanddiagram.
WRITE COMMAND
CLK
HIGH
CKE
Data for any WRITE burst may be truncated with a subse-
quentREADcommand, anddataforafixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ com mand is registered, the
data inputs will be ignored, and WRITEs will not be ex-
ecuted. An example is shown in WRITE to READ. Data n +
1 is either the last of a burst of two or the last desired of a
longerburst.
CS
RAS
CAS
WE
Dataforafixed-lengthWRITEburstmaybefollowed by,or
truncatedwith,aPRECHARGEcommandtothesamebank
(providedthatautoprechargewasnotactivated),andafull-
page WRITE burst may be truncated with a PRECHARGE
commandtothesamebank.ThePRECHARGEcommand
should be issued tDPL after the clock edge at which the last
desiredinputdataelementisregistered.Theautoprecharge
mode requires a tDPL of at least one clock plus time,
regardless of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask input
datafortheclockedgepriorto,andtheclockedgecoincident
with,thePRECHARGEcommand.Anexampleisshowninthe
WRITEtoPRECHARGEdiagram.Datan+1iseitherthelast
ofaburstoftwoorthelastdesiredofalongerburst.Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note: A9 is "Don't Care" for x16.
The starting column and bank addresses are provided with
theWRITEcommand,andautoprechargeiseitherenabled
ordisabledforthataccess. Ifautoprechargeisenabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
In the case of a fixed-length burst being executed to comple-
tion,aPRECHARGEcommandissuedattheoptimumtime(as
describedabove)providesthesameoperationthatwouldresult
from the same fixed-length burst with auto precharge. The
disadvantageofthePRECHARGEcommandisthatitrequires
that the command and address buses be available at the
appropriatetimetoissuethecommand;theadvantageofthe
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
During WRITE bursts, the first valid data-in element will be
registeredcoincidentwiththeWRITEcommand. Subsequent
dataelementswillberegisteredoneachsuccessivepositive
clockedge.Uponcompletionofafixed-lengthburst,assum-
ing no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored
(see WRITE Burst). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0
andcontinue.)
Fixed-length or full-page WRITE bursts can be truncated
withtheBURSTTERMINATEcommand.Whentruncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
datawritten(providedthatDQMisLOWatthattime)willbe
the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data n is the last desired data element
of a longer burst.
Data for any WRITE burst may be truncated with a subse-
quent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
providedcoincidentwiththenewcommandappliestothenew
command.
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE CYCLES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
Integrated Silicon Solution, Inc. — www.issi.com
39
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
DPL
DIN
n
D
IN n+1
DIN n+2
DON'T CARE
40
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
DPL
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
41
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
NOP
Tn+2
t
CK
tCL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
D
IN
m
D
IN m+
1
DIN m+
2
D
IN m+
3
DIN m-1
DQ
tRCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
42
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
tCMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
tDS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
2
D
IN m+3
DQ
tRCD
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
43
Rev. E
07/28/08
IS42S81600D, IS42S16800D
ALTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
D
IN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
DPL - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tDPL - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
44
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CLOCK SUSPEND
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
presentontheDQpinsremainsdriven;andburstcounters
are not incremented, as long as the clock is suspended.
(Seefollowingexamples.)
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
ClocksuspendmodeisexitedbyregisteringCKEHIGH;the
internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
D
OUT n+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
45
Rev. E
07/28/08
IS42S81600D, IS42S16800D
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
t
CL
tCH
CLK
CKE
tCKS
tCKH
t
CKS CKH
t
t
CMS
tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
tAS
t
AH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS
t
AH
tAS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
tAC
t
AC
tHZ
DQ
D
OUT
m
D
OUT m+1
DIN
e
D
IN e+1
t
LZ
t
OH
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
46
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
PRECHARGE
PRECHARGE Command
The PRECHARGE command (see figure) is used to deac-
tivatetheopenrowinaparticularbankortheopenrowinall
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged,itisintheidlestateandmustbeactivatedprior
to any READ or WRITE commands being issued to that
bank.
CLK
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
thismodeisreferredtoasprechargepower-down;ifpower-
down occurs when there is a row active in either bank, this
modeisreferredtoasactivepower-down.Enteringpower-
down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
devicemaynotremaininthepower-downstatelongerthan
the refresh period (64ms) since no refresh operations are
performed in this mode.
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See figure below.
POWER-DOWN
CLK
tCKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
t
t
t
RCD
RAS
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
47
Rev. E
07/28/08
IS42S81600D, IS42S16800D
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
tCK
t
CL
tCH
CLK
CKE
tCKS
tCKH
t
CKS
tCKS
tCMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
tAS
t
AH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
BURST READ/SINGLE WRITE
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaREADonbankn, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
CONCURRENT AUTO PRECHARGE
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
AWRITEtobankmwillinterruptaREADonbanknwhen
registered.DQMshouldbeusedthreeclockspriortothe
WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
tRP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
t
RP - BANK n
tDPL - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
49
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE with Auto Precharge
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
WRITE to bank m will interrupt a WRITE on bank n when
3. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaWRITEonbanknwhen
registered,withthedata-outappearing(CASlatency) later.
The PRECHARGE to bank n will begin after tDPL is met,
wheretDPL beginswhentheREADtobankmisregistered.
ThelastvalidWRITEtobanknwillbedata-inregisteredone
clock prior to the READ to bank m.
A
registered. The PRECHARGE to bank n will begin after
tDPL ismet,wheretDPL beginswhentheWRITEtobankm
is registered. The last valid data WRITE to bank n will be
data registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
IN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
IN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tOH
t
AC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
51
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCMS
tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
DQ
BANK
BANK
tAC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
tOH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
UNDEFINED
tRP
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
52
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/DQML
DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
t
AC
D
OUT
m
t
LZ
t
HZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com
53
Rev. E
07/28/08
IS42S81600D, IS42S16800D
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
tAC
tAC
tHZ
DOUT
m
DOUT m+1
DOUT m+2
DOUT m+3
t
LZ
t
OH
tOH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
UNDEFINED
tRP
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
SINGLE WRITE WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
AS
t
AH
BA0, BA1
BANK
BANK
BANK
BANK
tDS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
3) tRAS must not be violated.
Integrated Silicon Solution, Inc. — www.issi.com
55
Rev. E
07/28/08
IS42S81600D, IS42S16800D
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
ROW
SINGLE BANK
AS
t
AH
BA0, BA1
BANK
BANK
BANK
BANK
t
DS
t
DH
DQ
DIN
m
tRCD
tRAS
t
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
3) tRAS must not be violated.
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
ACTIVE
COMMAND
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
tAS tAH
ALL BANKS
ROW
tAS tAH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS tDH
tDS tDH
tDS tDH
DIN m+3
tDS tDH
DIN m+2
DQ
DIN m
DIN m+1
tRCD
tRAS
tRC
tDPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
3) tRAS must not be violated.
Integrated Silicon Solution, Inc. — www.issi.com
57
Rev. E
07/28/08
IS42S81600D, IS42S16800D
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/DQML
DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
tDS
tDH
t
DS
tDH
DQ
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
t
t
t
RCD
RAS
RC
tDPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X8: A11 = "Don't Care"
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
IS42S81600D, IS42S16800D
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency
166 MHz
143 MHz
Speed(ns) Order Part No.
Package
6
7
IS42S81600D-6T
IS42S81600D-7T
54-Pin TSOPII
54-Pin TSOPII
Frequency
166 MHz
166 MHz
143 MHz
143 MHz
Speed(ns) Order Part No.
Package
6
6
7
7
IS42S16800D-6T
IS42S16800D-6B
IS42S16800D-7T
IS42S16800D-7B
54-Pin TSOPII
54-ballBGA
54-Pin TSOPII
54-ballBGA
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40°C to 85°C
Frequency
Speed(ns) Order Part No.
IS42S81600D-7TI
Package
143 MHz
7
54-Pin TSOPII
Frequency
143 MHz
143 MHz
Speed(ns) Order Part No.
Package
54-Pin TSOPII
54-ballBGA
7
7
IS42S16800D-7TI
IS42S16800D-7BI
Integrated Silicon Solution, Inc. — www.issi.com
59
Rev. E
07/28/08
IS42S81600D, IS42S16800D
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency
166 MHz
143 MHz
Speed(ns) Order Part No.
Package
6
7
IS42S81600D-6TL
IS42S81600D-7TL
54-PinTSOPII,Lead-free
54-PinTSOPII,Lead-free
Frequency
166 MHz
166 MHz
143 MHz
143 MHz
143 MHz
133 MHz
133 MHz
Speed(ns) Order Part No.
Package
6
6
IS42S16800D-6TL
IS42S16800D-6BL
IS42S16800D-7TL
IC42S16800D-7TL
IS42S16800D-7BL
54-PinTSOPII,Lead-free
54-ballBGA,Lead-free
54-PinTSOPII,Lead-free
54-PinTSOPII,Lead-free
54-ballBGA,Lead-free
7
7
7
7.5
7.5
IS42S16800D-75ETL 54-PinTSOPII,Lead-free
IS42S16800D-75EBL 54-ballBGA,Lead-free
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40°C to 85°C
Frequency
Speed(ns) Order Part No.
IS42S81600D-7TLI
Package
143 MHz
7
54-PinTSOPII,Lead-free
Frequency
166 MHz
143 MHz
143 MHz
133 MHz
133 MHz
Speed(ns) Order Part No.
Package
6
7
IS42S16800D-6TLI
IS42S16800D-7TLI
IS42S16800D-7BLI
54-PinTSOPII,Lead-free
54-PinTSOPII,Lead-free
54-ballBGA,Lead-free
7
7.5
7.5
IS42S16800D-75ETLI 54-PinTSOPII,Lead-free
IS42S16800D-75EBLI 54-ballBGA,Lead-free
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (54-Ball)
ø 0.45 +/−0.05 (54X)
4
1
2
3
4
5
6
7
8
9
9
8
7
6
5
3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
J
G
H
J
e
E1
E
A1
A
SEATING PLANE
Notes:
1. Controlling dimensions are in millimeters.
2. 0.8 mm Ball Pitch
mBGA - 8mm x 13mm
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
Leads
54
A
—
—
1.00
—
—
0.039
A1
D
0.30
0.35 0.40
0.012 0.014 0.016
0.508 0.512 0.516
12.90 13.00 13.10
D1
E
—
7.90
—
6.40
—
—
0.252
—
8.00 8.10
0.311 0.315 0.319
E1
e
6.40
0.80
—
—
—
—
0.252
0.031
—
—
—
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/28/06
PACKAGING INFORMATION
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Plastic TSOP (T - Type II)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Symbol Min
Max
Min
Max
Ref. Std.
Ref. Std.
No. Leads (N)
54
No. Leads (N)
86
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
A
A1
A2
b
C
D
E1
E
e
—
1.20
0.05 0.15
0.95 1.05
0.17 0.27
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.50 BSC
—
0.047
0.05 0.15
—
0.002 0.006
—
0.002 0.006
0.037 0.041
0.007 0.011
0.005 0.008
0.867 0.8827
0.395 0.405
0.455 0.471
0.020 BSC
—
—
0.30 0.45
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.80 BSC
0.012 0.018
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.031 BSC
L
0.40 0.60
0.016 0.024
L
0.40 0.60
0.80 REF
0.61 REF
0.016 0.024
0.031 REF
0.024 BSC
L1
ZD
α
—
—
—
—
L1
ZD
α
0.71 REF
0° 8°
0°
8°
0°
8°
0°
8°
Integrated Silicon Solution, Inc.
1
Rev. D
03/13/07
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