IS42SM32400E-6TLI [ISSI]
Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86;
| 型号： | IS42SM32400E-6TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 动态存储器 光电二极管 |
| 文件： | 总25页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
16Mx8, 8Mx16, 4Mx32
128Mb Mobile Synchronous DRAM
APRIL 2011
DESCRIPTION
FEATURES
ISSI'sꢀ128MbꢀMobileꢀSynchronousꢀDRAMꢀachievesꢀhigh-
speedꢀdataꢀtransferꢀusingꢀpipelineꢀarchitecture.ꢀAllꢀinputꢀ
andꢀoutputꢀsignalsꢀreferꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀ
input.ꢀBothꢀwriteꢀandꢀreadꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀ
burstꢀoriented.ꢀTheꢀ128MbꢀMobileꢀSynchronousꢀDRAMꢀ
isꢀdesignedꢀtoꢀminimizeꢀcurrentꢀconsumptionꢀmakingꢀitꢀ
idealꢀforꢀlow-powerꢀapplications.ꢀꢀꢀBothꢀTSOPꢀandꢀBGAꢀ
packagesꢀareꢀoffered,ꢀincludingꢀindustrialꢀgradeꢀproducts.
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀpositiveꢀ
clockꢀedge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccessꢀandꢀprecharge
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ3
•ꢀ ProgrammableꢀBurstꢀLength:ꢀ1,ꢀ2,ꢀ4,ꢀ8,ꢀandꢀFullꢀPage
•ꢀ ProgrammableꢀBurstꢀSequence:
•ꢀ SequentialꢀandꢀInterleave
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ TCSRꢀ(TemperatureꢀCompensatedꢀSelfꢀRefresh)ꢀ
KEY TIMING PARAMETERS
•ꢀ PASRꢀ(PartialꢀArraysꢀSelfꢀRefresh):ꢀ1/16,ꢀ1/8,ꢀ1/4,ꢀ1/2,ꢀ
andꢀFullꢀ
Parameter
-6
-7
-75E
Unit
CLKꢀCycleꢀTime
CASꢀLatencyꢀ=ꢀ3
CASꢀLatencyꢀ=ꢀ2
CLKꢀFrequency
CASꢀLatencyꢀ=ꢀ3
CASꢀLatencyꢀ=ꢀ2
AccessꢀTimeꢀfromꢀCLK
CASꢀLatencyꢀ=ꢀ3
CASꢀLatencyꢀ=ꢀ2
•ꢀ DeepꢀPowerꢀDownꢀModeꢀ(DPD)
6
7
ns
ns
–
•ꢀ DriverꢀStrengthꢀControlꢀ(DS):ꢀ1/4,ꢀ1/2,ꢀandꢀFull
10
10
7.5
OPTIONS
•ꢀ Configurations:ꢀ
-ꢀ16Mꢀxꢀ8ꢀꢀ
166
100
143
100
Mhz
Mhz
–
133
-ꢀ8Mꢀxꢀ16ꢀ
-ꢀ4Mꢀxꢀ32ꢀꢀ
5.4
8
5.4
8
ns
ns
–
•ꢀ PowerꢀSupplyꢀꢀ
5.4
IS42SMxxxꢀ–ꢀVdd/Vddqꢀ=ꢀ3.3ꢀVꢀ
IS42RMxxxꢀ –ꢀVdd/Vddqꢀ=ꢀ2.5ꢀVꢀ
•ꢀ Packages:ꢀ
x8ꢀ/ꢀx16ꢀ–TSOPꢀIIꢀ(54),ꢀBGAꢀ(54)ꢀ[x16ꢀonly]ꢀ
x32ꢀ–ꢀTSOPꢀIIꢀ(86),ꢀꢀBGAꢀ(90)
•ꢀ TemperatureꢀRange:ꢀꢀ
Commercialꢀ(0°Cꢀtoꢀ+70°C)ꢀꢀ
Industrialꢀ(–40ꢀºCꢀtoꢀ85ꢀºC)
ADDRESSING TABLE
Parameter
16M x 8
4Mꢀxꢀ8ꢀxꢀ4ꢀbanks
4K/64ms
A0-A11
8M x 16
2Mꢀxꢀ16ꢀxꢀ4ꢀbanks
4K/64ms
A0-A11
4M x 32
Configuration
1Mꢀxꢀ32ꢀxꢀ4ꢀbanks
4K/64ms
A0-A11
RefreshꢀCount
RowꢀꢀAddressing
ColumnꢀAddressing
BankꢀAddressing
PrechargeꢀAddressing
A0-A9
A0-A8
A0-A7
BA0,ꢀBA1
A10
BA0,ꢀBA1
A10
BA0,ꢀBA1
A10
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀex-
pectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀ
Solution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. - www.issi.comꢀ
1
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
General Description
ISSI’sꢀ128MbꢀSDRAMꢀisꢀaꢀhighꢀspeedꢀCMOS,ꢀdynamicꢀrandom-accessꢀmemoryꢀdesignedꢀtoꢀoperateꢀinꢀ3.3Vꢀ–ꢀ2.5Vꢀ
VDDꢀꢀandꢀ3.3Vꢀ–ꢀ2.5VꢀVDDQꢀmemoryꢀsystemsꢀcontainingꢀ134,271,728ꢀbits.ꢀInternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀ
DRAMꢀwithꢀaꢀsynchronousꢀinterface.ꢀTheꢀ128MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀandꢀaꢀpower-saving,ꢀ
power-downꢀmode.ꢀAllꢀsignalsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀAllꢀinputsꢀandꢀoutputsꢀareꢀ
LVTTLꢀ(VDDꢀ=ꢀ3.3V)ꢀorꢀLVCMOSꢀ(VDDꢀ=ꢀ2.5V)ꢀꢀcompatible.ꢀTheꢀ128MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀ
burstꢀdataꢀatꢀaꢀhighꢀdataꢀrateꢀwithꢀautomaticꢀcolumn-addressꢀgeneration,ꢀtheꢀabilityꢀtoꢀinterleaveꢀbetweenꢀinternalꢀ
banksꢀtoꢀhideꢀprechargeꢀtimeꢀandꢀtheꢀcapabilityꢀtoꢀrandomlyꢀchangeꢀcolumnꢀaddressesꢀonꢀeachꢀclockꢀcycleꢀduringꢀ
burstꢀaccess.
Aꢀself-timedꢀrowꢀprechargeꢀinitiatedꢀatꢀtheꢀendꢀofꢀtheꢀburstꢀsequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀ
functionꢀenabled.ꢀPrechargeꢀoneꢀbankꢀwhileꢀaccessingꢀoneꢀofꢀtheꢀotherꢀthreeꢀbanksꢀwillꢀhideꢀtheꢀprechargeꢀcyclesꢀ
andꢀprovideꢀseamless,ꢀhigh-speed,ꢀrandom-accessꢀoperation.ꢀSDRAMꢀreadꢀandꢀwriteꢀaccessesꢀareꢀburstꢀorientedꢀ
startingꢀatꢀaꢀselectedꢀlocationꢀandꢀcontinuingꢀforꢀaꢀprogrammedꢀnumberꢀofꢀlocationsꢀinꢀaꢀprogrammedꢀsequence.ꢀTheꢀ
registrationꢀofꢀanꢀActiveꢀcommandꢀbeginsꢀaccesses,ꢀfollowedꢀbyꢀaꢀReadꢀorꢀWriteꢀcommand.ꢀTheꢀACTIVEꢀcommandꢀ
inꢀconjunctionꢀwithꢀaddressꢀbitsꢀregisteredꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀBA1ꢀselectꢀtheꢀ
bank;ꢀA0-A11ꢀ(x8,ꢀx16ꢀandꢀx32)ꢀselectꢀtheꢀrow).ꢀTheꢀREADꢀorꢀWRITEꢀcommandsꢀinꢀconjunctionꢀwithꢀaddressꢀbitsꢀ
registeredꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀcolumnꢀlocationꢀforꢀtheꢀburstꢀaccess.ꢀProgrammableꢀREADꢀorꢀWRITEꢀburstꢀ
lengthsꢀconsistꢀofꢀ1,ꢀ2,ꢀ4ꢀandꢀ8ꢀlocations,ꢀorꢀfullꢀpage,ꢀwithꢀaꢀburstꢀterminateꢀoption.
Functional Block Diagram (8Mx16)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
12
VDD/VDDQ
Vss/VssQ
SELF
DATA OUT
BUFFER
REFRESH
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
NC
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS: 16Mx8
A0-A11ꢀ ꢀ
A0-A9ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WEꢀ
WriteꢀEnable
ꢀ
DQMꢀ
Vddꢀ
DataꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ7ꢀ
Vssꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Vddqꢀ
Vssqꢀ
NCꢀ
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. - www.issi.comꢀ
3
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS: 8Mx16
A0-A11ꢀ ꢀ
A0-A8ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WEꢀ
WriteꢀEnable
ꢀ
DQMLꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
4ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
PIN CONFIGURATION
54-ball fBGA for x16ꢀ(TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ8.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
PACKAGEꢀCODE:ꢀBꢀꢀ
1 2 3 4 5 6 7 8 9
A
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
B
C
D
E
F
DQ8 NC
VSS
DQMH CLK CKE
G
H
J
NC
A8
A11
A7
A9
A6
A4
A0
A3
A1
A10
VSS
A5
A2 VDD
PIN DESCRIPTIONS: 8Mx16
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
A0-A8ꢀ
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DQMLꢀ x16ꢀLowerꢀByteꢀInput/OutputꢀMask
DQMHꢀ x16ꢀUpperꢀByteꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. - www.issi.comꢀ
5
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD
DQ0
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
2
DQ15
VDDQ
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SSQ
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
VDDQ
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ10
DQ9
V
SSQ
VDDQ
DQ7
NC
DQ8
NC
VDD
VSS
DQM0
WE
DQM1
NC
NC
CAS
RAS
CS
CLK
CKE
A9
A11
BA0
BA1
A10
A0
A8
A7
A6
A5
A1
A2
A4
A3
DQM2
DQM3
VDD
VSS
NC
DQ16
NC
DQ31
V
SSQ
VDDQ
DQ17
DQ18
DQ30
DQ29
VDDQ
VSSQ
DQ19
DQ20
DQ28
DQ27
V
SSQ
VDDQ
DQ21
DQ22
DQ26
DQ25
VDDQ
VSSQ
DQ23
DQ24
VDD
VSS
PIN DESCRIPTIONS: 4Mx32
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
ꢀ
WriteꢀEnable
A0-A7ꢀ
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DQM0-DQM3ꢀ
x32ꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DQ0ꢀtoꢀDQ31ꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
6ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
PIN CONFIGURATION
PACKAGEꢀCODE:ꢀBꢀꢀ90ꢀBALLꢀFBGAꢀ(TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ13.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
B
C
D
E
F
G
H
J
A4
A7
A5
A8
A6
NC
A9
NC
A10
NC
A0
A1
BA1 A11
CLK CKE
DQM1 NC
BA0
CS RAS
K
L
CAS WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
M
N
P
R
PIN DESCRIPTIONS: 4Mx32
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
ꢀ
WriteꢀEnable
A0-A7ꢀ
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
DQM0-DQM3ꢀ
x32ꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DQ0ꢀtoꢀDQ31ꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. - www.issi.comꢀ
7
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Mobile SDRAM Functionality
ISSI’sꢀ128MbꢀMobileꢀSDRAMsꢀareꢀpinꢀcompatibleꢀandꢀhaveꢀsimilarꢀfunctionalityꢀwithꢀISSI’sꢀstandardꢀSDRAMs,ꢀbutꢀ
offerꢀlowerꢀoperatingꢀvoltagesꢀandꢀpowerꢀsavingꢀfeatures.ꢀForꢀdetailedꢀdescriptionsꢀofꢀpinꢀfunctions,ꢀcommandꢀtruthꢀ
tables,ꢀfunctionalꢀtruthꢀtables,ꢀdeviceꢀoperationꢀasꢀwellꢀasꢀtimingꢀdiagramsꢀpleaseꢀreferꢀtoꢀISSIꢀdocumentꢀ“Mobileꢀ
SynchronousꢀDRAMꢀDeviceꢀOperationsꢀ&ꢀTimingꢀDiagrams”ꢀlistedꢀatꢀwww.issi.comꢀ
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
ThereꢀareꢀtwoꢀmodeꢀregistersꢀinꢀtheꢀMobileꢀSDRAM;ꢀModeꢀRegisterꢀ(MR)ꢀandꢀExtendedꢀModeꢀRegisterꢀ(EMR).ꢀTheꢀ
ModeꢀRegisterꢀisꢀdiscussedꢀbelow,ꢀfollowedꢀbyꢀtheꢀExtendedꢀModeꢀRegister.ꢀTheꢀModeꢀRegisterꢀisꢀusedꢀtoꢀdefineꢀ
theꢀspecificꢀmodeꢀofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀselectionꢀofꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀCASꢀ
Latency,ꢀoperatingꢀmode,ꢀandꢀaꢀwriteꢀburstꢀmode.ꢀTheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀREGISTERꢀ
commandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀ
TheꢀEMRꢀcontrolsꢀtheꢀfunctionsꢀbeyondꢀthoseꢀcontrolledꢀbyꢀtheꢀMR.ꢀTheseꢀadditionalꢀfunctionsꢀareꢀspecialꢀfeaturesꢀ
ofꢀtheꢀMobileꢀSDRAM.ꢀTheyꢀincludeꢀtemperature-compensatedꢀselfꢀrefreshꢀ(TCSR)ꢀcontrol,ꢀpartial-arrayꢀselfꢀrefreshꢀ
(PASR),ꢀandꢀoutputꢀdriveꢀstrength.ꢀTheꢀEMRꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀwithꢀBA1ꢀ
=ꢀ1ꢀandꢀBA0ꢀ=ꢀ0ꢀandꢀretainsꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀNotꢀ
programmingꢀtheꢀextendedꢀmodeꢀregisterꢀuponꢀinitializationꢀwillꢀresultꢀinꢀdefaultꢀsettingsꢀforꢀtheꢀlow-powerꢀfeatures.ꢀ
Theꢀextendedꢀmodeꢀwillꢀdefaultꢀwithꢀtheꢀtemperatureꢀsensorꢀenabled,ꢀfullꢀdriveꢀstrength,ꢀandꢀfullꢀarrayꢀ(allꢀ4ꢀbanks)ꢀ
refresh.ꢀ
Mode Register Definition
TheꢀMRꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀselectionꢀofꢀaꢀ
burstꢀlength,ꢀaꢀburstꢀtype,ꢀaꢀCASꢀlatency,ꢀanꢀoperatingꢀmodeꢀandꢀaꢀwriteꢀburstꢀmode,ꢀasꢀshownꢀinꢀꢀFigureꢀMODEꢀ
REGISTERꢀDEFINITION.ꢀTheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀwillꢀ
retainꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.
ModeꢀregisterꢀbitsꢀM0ꢀ-ꢀM2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀspecifiesꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀꢀinterleaved),ꢀM4ꢀ-ꢀ
M6ꢀspecifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀmode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10,ꢀ
M11,ꢀandꢀM12ꢀareꢀreservedꢀforꢀfutureꢀuse.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀidle,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀbeforeꢀ
initiatingꢀtheꢀsubsequentꢀoperation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.
8ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
AllOtherStatesReserved
—
Write Burst Mode
BA1
BA0
Mode Register Definition
M9
0
Mode
To ensure compatibility with future devices,
should program A11, A10 = "0"
0
0
0
1
Program Mode Register
Reserved
Programmed Burst Length
Single Location Access
1
1
1
0
1
Program Extended Mode Register
Reserved
Burst Length
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀwithꢀtheꢀburstꢀlengthꢀbeingꢀprogrammable,ꢀasꢀshownꢀinꢀ
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeterminesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀ
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀlengthsꢀofꢀ1,ꢀ2,ꢀ4ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ
sequentialꢀandꢀtheꢀinterleavedꢀburstꢀtypes,ꢀandꢀaꢀfull-pageꢀburstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀburstꢀ
isꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀcommandꢀtoꢀgenerateꢀarbitraryꢀburstꢀlengths.ꢀReservedꢀstatesꢀ
shouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀcolumnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accessesꢀforꢀthatꢀburstꢀtakeꢀplaceꢀwithinꢀthisꢀblock,ꢀmeaningꢀthatꢀtheꢀburstꢀwillꢀwrapꢀwithinꢀtheꢀblockꢀifꢀaꢀboundaryꢀisꢀ
reached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A7ꢀ(x32),ꢀA1-A8ꢀ(x16)ꢀorꢀA1-A9ꢀ(x8)ꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀ
byꢀꢀA2-A7ꢀ(x32),ꢀꢀA2-A8ꢀ(x16)ꢀorꢀA2-A9ꢀ(x8)ꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A7ꢀ(x32),ꢀꢀA3-A8ꢀ(x16)ꢀorꢀ
A3-A9ꢀ(x8)ꢀwhenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀaddressꢀbit(s)ꢀareꢀusedꢀtoꢀselectꢀtheꢀ
startingꢀlocationꢀwithinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀtheꢀboundaryꢀisꢀreached.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
9
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Burst Type
Accessesꢀwithinꢀaꢀgivenꢀburstꢀmayꢀbeꢀprogrammedꢀtoꢀbeꢀeitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀtheꢀburstꢀlength,ꢀtheꢀburstꢀtypeꢀandꢀtheꢀstartingꢀcolumnꢀ
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Length
A 0
ꢀ
ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
ꢀ
0-1ꢀ
1-0ꢀ
ꢀ
ꢀ
0-1
1-0
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
A 2
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
ꢀ2-3-4-5-6-7-0-1ꢀ
ꢀ3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
ꢀ0ꢀ
1ꢀ
8ꢀ
ꢀ
ꢀ1ꢀ
0ꢀ
0ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
1ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fullꢀ ꢀꢀꢀnꢀ=ꢀA0-A7ꢀ(x32)ꢀ
Pageꢀ nꢀ=ꢀA0-A8ꢀ(x16)ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cnꢀ-ꢀ1,
(y)ꢀ
ꢀ
nꢀ=ꢀA0-A9ꢀ(x8)ꢀ ꢀ
(locationꢀ0-y)ꢀ
ꢀ
Cn…
CAS Latency
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀtheꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀtheꢀ
firstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀthreeꢀclocks.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀtheꢀlatencyꢀisꢀmꢀclocks,ꢀtheꢀdataꢀwillꢀbeꢀavailableꢀbyꢀclockꢀ
edgeꢀnꢀ+ꢀm.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀclockꢀedgeꢀoneꢀcycleꢀearlierꢀ(nꢀ+ꢀmꢀ-ꢀ1),ꢀandꢀprovidedꢀthatꢀ
theꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀclockꢀedgeꢀnꢀ+ꢀm.ꢀForꢀꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycleꢀtimeꢀisꢀsuchꢀthatꢀallꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀafterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀ
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
Operating Mode
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀtoꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀ
areꢀreservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
10ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbecauseꢀunknownꢀoperationꢀorꢀincompatibilityꢀwithꢀfutureꢀ
versionsꢀmayꢀresult.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀtheꢀ
programmedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀwriteꢀaccessesꢀareꢀsingle-locationꢀ(nonburst)ꢀaccesses.
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. - www.issi.comꢀ
11
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
EꢀTENDED MODE REGISTER DEFINITION
AddressꢀBusꢀ(Ax)
BA1ꢀ BA0ꢀ
A11ꢀ
A10ꢀ
A9ꢀ
A8ꢀ
A7ꢀ
A6ꢀ
A5ꢀ
A4ꢀ
A3ꢀ
A2ꢀ
A1ꢀ
A0
Ext.ꢀModeꢀReg.ꢀ(Ex)
PASRꢀ
E2 E1 E0 PartialꢀArrayꢀSelfꢀRefreshꢀꢀ
Coverage
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fully array (4 banks) - (Default)
Half array (banks 0, 1)
Quarter array (bank 0)
Reserved
Reserved
One-eighth array (1/2 bank 0)
One-sixteenth array (1/4 bank 0)
Reserved
TCSRꢀ
E4 E3 Max.ꢀCaseꢀTemp.
0
0
1
1
0
1
0
1
70oC
45oC
15oC
85oC (Default)
DSꢀ
E6 E5 DriverꢀStrength
0
0
1
1
0
1
0
1
Full strength driver (Default)
Half strength driver
Quarter strength driver
Reserved
setꢀtoꢀ"0"ꢀ
E11 E10 E9 E8 E7 E6-E0
0
–
0
–
0
–
0
–
0
–
Valid Normal operation
All other states reserved
–
ꢀ
BA1 BA0 ModeꢀRegisterꢀDefinition
0
0
1
1
0
1
0
1
Program Mode Register
Reserved
Program Extended mode Register
Reserved
TheꢀextendedꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(BA1ꢀ=ꢀ1,ꢀBA0ꢀ=ꢀ0)ꢀandꢀ
retainsꢀtheꢀstoredꢀinformationꢀuntilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.ꢀTheꢀextendedꢀmodeꢀregisterꢀ
mustꢀbeꢀprogrammedꢀwithꢀE7ꢀthroughꢀE11ꢀsetꢀtoꢀ“0.”ꢀTheꢀextendedꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idleꢀandꢀnoꢀburstsꢀareꢀinꢀprogress,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀbeforeꢀinitiatingꢀanyꢀsubsequentꢀ
operation.ꢀViolatingꢀeitherꢀofꢀtheseꢀrequirementsꢀresultsꢀinꢀunspecifiedꢀoperation.ꢀTheꢀextendedꢀmodeꢀregisterꢀmustꢀbeꢀ
programmedꢀtoꢀensureꢀproperꢀoperation.
Temperature-Compensated Self Refresh (TCSR)
TCSRꢀallowsꢀtheꢀcontrollerꢀtoꢀprogramꢀtheꢀrefreshꢀintervalꢀduringꢀselfꢀrefreshꢀmode,ꢀaccordingꢀtoꢀtheꢀcaseꢀtemperatureꢀ
ofꢀtheꢀmobileꢀdevice.ꢀThisꢀallowsꢀgreatꢀpowerꢀsavingsꢀduringꢀselfꢀrefreshꢀduringꢀmostꢀoperatingꢀtemperatureꢀranges.ꢀ
OnlyꢀduringꢀextremeꢀtemperaturesꢀwouldꢀtheꢀcontrollerꢀhaveꢀtoꢀselectꢀaꢀhigherꢀTCSRꢀlevelꢀthatꢀwillꢀguaranteeꢀdataꢀ
duringꢀselfꢀrefresh.
12ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
EveryꢀcellꢀinꢀtheꢀDRAMꢀrequiresꢀrefreshingꢀdueꢀtoꢀtheꢀcapacitorꢀlosingꢀitsꢀchargeꢀoverꢀtime.ꢀTheꢀrefreshꢀrateꢀisꢀ
dependentꢀonꢀtemperature.ꢀAtꢀhigherꢀtemperaturesꢀaꢀcapacitorꢀlosesꢀchargeꢀquickerꢀthanꢀatꢀlowerꢀtemperatures,ꢀ
requiringꢀtheꢀcellsꢀtoꢀbeꢀrefreshedꢀmoreꢀoften.ꢀHistorically,ꢀduringꢀselfꢀrefresh,ꢀtheꢀrefreshꢀrateꢀhasꢀbeenꢀsetꢀtoꢀ
accommodateꢀtheꢀworstꢀcase,ꢀorꢀhighestꢀtemperatureꢀrange,ꢀexpected.ꢀꢀThus,ꢀduringꢀambientꢀtemperatures,ꢀtheꢀ
powerꢀconsumedꢀduringꢀrefreshꢀwasꢀunnecessarilyꢀhighꢀbecauseꢀtheꢀrefreshꢀrateꢀwasꢀsetꢀtoꢀaccommodateꢀtheꢀhigherꢀ
temperatures.ꢀSettingꢀE4ꢀandꢀE3ꢀallowsꢀtheꢀDRAMꢀtoꢀaccommodateꢀmoreꢀspecificꢀtemperatureꢀregionsꢀduringꢀselfꢀ
refresh.ꢀTheꢀdefaultꢀforꢀISSIꢀ128MbꢀMobileꢀSDRAMꢀisꢀTCSRꢀ=ꢀ85°Cꢀtoꢀguaranteeꢀrefreshꢀoperation.ꢀThisꢀmodeꢀofꢀ
operationꢀhasꢀaꢀhigherꢀcurrentꢀconsumptionꢀbecauseꢀtheꢀselfꢀrefreshꢀoscillatorꢀisꢀsetꢀtoꢀrefreshꢀtheꢀSDRAMꢀcellsꢀ
moreꢀoftenꢀthanꢀneeded.ꢀByꢀusingꢀanꢀexternalꢀtemperatureꢀsensorꢀtoꢀdetermineꢀtheꢀoperatingꢀtemperatureꢀtheꢀMobileꢀ
SDRAMꢀcanꢀbeꢀprogrammedꢀforꢀlowerꢀtemperatureꢀandꢀrefreshꢀrates,ꢀeffectivelyꢀreducingꢀcurrentꢀconsumptionꢀbyꢀ
aꢀsignificantꢀamount.ꢀThereꢀareꢀfourꢀtemperatureꢀsettings,ꢀwhichꢀwillꢀvaryꢀtheꢀselfꢀrefreshꢀcurrentꢀaccordingꢀtoꢀtheꢀ
selectedꢀtemperature.ꢀThisꢀselectableꢀrefreshꢀrateꢀwillꢀsaveꢀpowerꢀwhenꢀtheꢀMobileꢀDRAMꢀisꢀoperatingꢀatꢀnormalꢀ
temperatures.
Partial-Array Self Refresh (PASR)
Forꢀfurtherꢀpowerꢀsavingsꢀduringꢀselfꢀrefresh,ꢀtheꢀPASRꢀfeatureꢀallowsꢀtheꢀcontrollerꢀtoꢀselectꢀtheꢀamountꢀofꢀmemoryꢀ
thatꢀwillꢀbeꢀrefreshedꢀduringꢀselfꢀrefresh.ꢀTheꢀrefreshꢀoptionsꢀareꢀallꢀbanksꢀ(banksꢀ0,ꢀ1,ꢀ2,ꢀandꢀ3);ꢀtwoꢀbanksꢀ(banksꢀ
0ꢀandꢀ1);ꢀandꢀoneꢀbankꢀ(bankꢀ0).ꢀInꢀadditionꢀpartialꢀamountsꢀofꢀbankꢀ0ꢀꢀ(halfꢀorꢀquarterꢀofꢀtheꢀbank)ꢀmayꢀbeꢀselected.ꢀꢀ
WRITEꢀandꢀREADꢀcommandsꢀoccurꢀtoꢀanyꢀbankꢀselectedꢀduringꢀstandardꢀoperation,ꢀbutꢀonlyꢀtheꢀselectedꢀbanksꢀinꢀ
PASRꢀwillꢀbeꢀrefreshedꢀduringꢀselfꢀrefresh.ꢀIt’sꢀimportantꢀtoꢀnoteꢀthatꢀdataꢀinꢀbanksꢀ2ꢀandꢀ3ꢀwillꢀbeꢀlostꢀwhenꢀtheꢀtwo-
bankꢀoptionꢀisꢀused.ꢀDataꢀwillꢀbeꢀlostꢀinꢀbanksꢀ1,ꢀ2,ꢀandꢀ3ꢀwhenꢀtheꢀone-bankꢀoptionꢀisꢀused.
Driver Strength (DS)
BitsꢀE5ꢀandꢀE6ꢀofꢀtheꢀEMRꢀcanꢀbeꢀusedꢀtoꢀselectꢀtheꢀdriverꢀstrengthꢀofꢀtheꢀDQꢀoutputs.ꢀThisꢀvalueꢀshouldꢀbeꢀsetꢀ
accordingꢀtoꢀtheꢀapplication’sꢀrequirements.ꢀTheꢀdefaultꢀisꢀFullꢀDriverꢀStrength.
Deep Power Down (DPD)
Deepꢀpowerꢀdownꢀmodeꢀisꢀforꢀmaximumꢀpowerꢀsavingsꢀandꢀisꢀachievedꢀbyꢀshuttingꢀdownꢀpowerꢀtoꢀtheꢀentireꢀmemoryꢀ
arrayꢀofꢀtheꢀmobileꢀdevice.ꢀDataꢀwillꢀbeꢀlostꢀonceꢀdeepꢀpowerꢀdownꢀmodeꢀisꢀexecuted.
DPDꢀmodeꢀisꢀenteredꢀbyꢀhavingꢀallꢀbanksꢀidle,ꢀCSꢀandꢀWEꢀheldꢀlow,ꢀwithꢀRASꢀandꢀCASꢀHIGHꢀatꢀtheꢀrisingꢀedgeꢀofꢀ
theꢀclock,ꢀwhileꢀCKEꢀisꢀLOW.ꢀCKEꢀmustꢀbeꢀheldꢀLOWꢀduringꢀDPDꢀmode.ꢀꢀToꢀexitꢀDPDꢀmode,ꢀCKEꢀmustꢀbeꢀassertedꢀ
HIGH.ꢀUponꢀexitꢀfromꢀDPDꢀmode,ꢀatꢀleastꢀ200msꢀofꢀvalidꢀclocksꢀwithꢀeitherꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀcommandsꢀ
areꢀappliedꢀtoꢀtheꢀcommandꢀbus,ꢀfollowedꢀbyꢀaꢀfullꢀMobileꢀSDRAMꢀinitializationꢀsequence,ꢀisꢀrequired.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
13
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAꢀIMUM RATINGS(1)
Symbol
Parameters
Rating
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀ+4.6ꢀ
–0.5ꢀtoꢀVddqꢀ+ꢀ0.5ꢀ
–1.0ꢀtoꢀVddqꢀ+ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vdd maxꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
outputꢀShortedꢀCurrentꢀ
ꢀ
Vddq max
ꢀ
Vinꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Voutꢀ
Pd max
Ics
W
mA
50ꢀ
ꢀ
ꢀ
Topr
ꢀ
operatingꢀTemperatureꢀ
ꢀ
Com.ꢀ
Ind.ꢀ
0ꢀtoꢀ+70ꢀ
–40ꢀtoꢀ+85ꢀ
°C
°C
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–65ꢀtoꢀ+150ꢀ
°C
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
CAPACITANCE CꢁARACTERISTICS - x8, x16
Symbol
Cin1
Parameters
InputꢀCapacitance:ꢀCLK
Min.
2.5
Max.
3.5
Unit
pF
Cin2
Ci/o
InputꢀCapacitance:ꢀAllꢀOtherꢀInputꢀPins
DataꢀInput/OutputꢀCapacitance:ꢀI/Os
2.5
4.0
3.8
6.5
pF
pF
CAPACITANCE CꢁARACTERISTICS - x32
Symbol
Cin1
Parameters
InputꢀCapacitance:ꢀCLK
Min.
2.5
Max.
3.5
Unit
pF
Cin2
Ci/o
InputꢀCapacitance:ꢀAllꢀOtherꢀInputꢀPins
DataꢀInput/OutputꢀCapacitance:ꢀI/Os
2.5
4.0
3.8
6.5
pF
pF
14ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
DC RECOMMENDED OPERATING CONDITIONS
IS42SMxxx - 3.3V Operation
Symbol Parameters
Min.
3.0
3.0
2.0
-0.3
-5
-5
2.4
–
Typ.
3.3
3.3
–
–
–
–
–
–
Max.
3.6
3.6
Vddq+0.3ꢀ
Unit
V
V
V
V
µAꢀ
µA
V
Vdd
SupplyꢀVoltage
Vddq
I/OꢀSupplyꢀVoltage
InputꢀHighꢀVoltage
InputꢀLowꢀVoltage
(1)
Vih
(2)
Vil
0.8
+5
+5
–
Iil
InputꢀLeakageꢀCurrentꢀ(0Vꢀ≤ Vinꢀ≤ꢀVdd)
OutputꢀLeakageꢀCurrentꢀ(Outputꢀdisabled,ꢀ0Vꢀ≤ Voutꢀ≤ Vdd)
OutputꢀHighꢀVoltageꢀCurrentꢀ(Iohꢀ=ꢀ-2mA)
OutputꢀLowꢀVoltageꢀCurrentꢀ(Iolꢀ=ꢀ2mA)
Iol
Voh
Vol
0.4
V
IS42RMxxx - 2.5V Operation
Symbol
Vdd
Vddq
Parameters
SupplyꢀVoltage
I/OꢀSupplyꢀVoltage
InputꢀHighꢀVoltage
Min.
2.3
2.3
2.0
-0.3
-5
-5
Vdd-0.2
-
Typ.
Max.
2.7
2.7
Vdd+0.3ꢀ
0.55
+5
Unit
V
V
V
V
µAꢀ
µA
V
2.5
2.5
-
-
–
–
–
–
(1)
Vih
Vil
(2)
InputꢀLowꢀVoltage
Iil
InputꢀLeakageꢀCurrentꢀ(0Vꢀ≤ Vinꢀ≤ꢀVdd)
OutputꢀLeakageꢀCurrentꢀ(Outputꢀdisabled,ꢀ0Vꢀ≤ Voutꢀ≤ Vdd)
OutputꢀHighꢀVoltageꢀCurrentꢀ(Iohꢀ=ꢀ-2mA)
OutputꢀLowꢀVoltageꢀCurrentꢀ(Iolꢀ=ꢀ2mA)
Iol
Voh
Vol
+5
-
0.2
V
Notes:
1.ꢀ Vihꢀ(overshoot):ꢀVihꢀ(max)ꢀ=ꢀVddqꢀ+1.2Vꢀ(pulseꢀwidthꢀ<ꢀ3ns).
2.ꢀ Vilꢀ(undershoot):ꢀVihꢀ(min)ꢀ=ꢀ-1.2Vꢀ(pulseꢀwidthꢀ<ꢀ3ns).
3.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
ContactꢀProductꢀMarketingꢀforꢀ3.0Vꢀ+ꢀ10%ꢀsupport.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
15
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
DC ELECTRICAL CꢁARACTERISTICS VDD = 3.3V/2.5V, x8 and x16
Symbol
Parameter
Test Condition
–6
–7
–75E Unit
Idd1(1)
OperatingꢀCurrent
OneꢀBankꢀActive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,
90
85
90
mA
tclKꢀ=ꢀtCLK(min),ꢀtRCꢀ=ꢀtRC(min)
(4)
Idd2p
PrechargeꢀStandbyꢀCurrent
(InꢀPower-DownꢀMode)
CKEꢀ≤ꢀVil (max),ꢀtCKꢀ=ꢀ15ns
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
1
1
1
1
1
1
mA
mA
(4)
Idd2ps
PrechargeꢀStandbyꢀCurrentꢀꢀꢀꢀꢀꢀ
WithꢀClockꢀStop
CKEꢀ≤ꢀVil (max),ꢀCLKꢀ≤ꢀVil (max)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
(InꢀPower-DownꢀMode)
(2)
Idd2n
PrechargeꢀStandbyꢀCurrent
(InꢀNonꢀPower-DownꢀMode)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
tCKꢀ=ꢀ15ꢀns
35
20
35
20
35
20
mA
mA
Idd2ns
PrechargeꢀStandbyꢀCurrentꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
WithꢀClockꢀStop
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
AllꢀInputsꢀStable
(InꢀNon-PowerꢀDownꢀMode)
(2)
Idd3p
ActiveꢀStandbyꢀCurrent
(InꢀPower-DownꢀMode)
CKEꢀ≤ꢀVil (max),ꢀCSꢀ≥ꢀVddꢀ-ꢀ0.2V
tCKꢀ=ꢀ15ꢀns
2
2
2
2
2
2
mA
mA
Idd3ps
ActiveꢀStandbyꢀCurrent
WithꢀClockꢀStop
CKEꢀ≤ꢀVil (max),ꢀCLKꢀ≤ꢀVil (max)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
(InꢀPower-DownꢀMode)
(2)
Idd3n
ActiveꢀStandbyꢀCurrent
(InꢀNonꢀPower-DownꢀMode)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
tCKꢀ=ꢀ15ꢀns
40
25
40
25
40
25
mA
mA
Idd3ns
ActiveꢀStandbyꢀCurrent
WithꢀClockꢀStop
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
AllꢀInputsꢀStable
(InꢀNonꢀPower-DownꢀMode)
Idd4
OperatingꢀCurrent
AllꢀBanksꢀActive,ꢀBLꢀ=4,ꢀCLꢀ=ꢀ3
tCKꢀ=ꢀtCK(min)
120
110
120
mA
Idd5
Idd6
Idd7
Auto-RefreshꢀCurrent
Self-RefreshꢀCurrent
tRCꢀ=ꢀtRC(min),ꢀtCLKꢀ=ꢀtCLK(min)
180
1.2
140
1.2
180
1.2
mA
mA
mA
CKEꢀ≤ꢀ0.2V
Self-Refresh:ꢀCKEꢀ=ꢀLOW;ꢀtCKꢀ=ꢀtCKꢀ(MIN); FullꢀArray,ꢀ85oC
1200
900
1000
750
900
675
850
640
800
600
Address,ꢀControl,ꢀandꢀDataꢀbusꢀinputsꢀareꢀ FullꢀArray,ꢀ45oC
stable
HalfꢀArray,ꢀ85oC
HalfꢀArray,ꢀ45oC
1/4thꢀArray,ꢀ85oC
1/4thꢀArray,ꢀ45oC
1/8thꢀArray,ꢀ85oC
1/8thꢀArray,ꢀ45oC
1/16thꢀArray,ꢀ85oC
1/16thꢀArray,ꢀ45oC
(3,4)
Izz
DeepꢀPowerꢀDownꢀCurrent
CKEꢀ≤ꢀ0.2V
15
15
15
mA
Notes:
1.ꢀ Iddꢀ(max)ꢀisꢀspecifiedꢀatꢀtheꢀoutputꢀopenꢀcondition.
2.ꢀ Inputꢀsignalsꢀareꢀchangedꢀoneꢀtimeꢀduringꢀ30ns.
3.ꢀꢀIzzꢀvaluesꢀshownꢀareꢀnominalꢀatꢀ25oC.ꢀꢀIzzꢀisꢀnotꢀtested.
4.ꢀꢀTestedꢀafterꢀ500msꢀdelay.
16ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
DC ELECTRICAL CꢁARACTERISTICS VDD = 3.3V/2.5V, x32
Symbol
Parameter
Test Condition
–65
–7
Unit
Idd1(1)
OperatingꢀCurrent
OneꢀBankꢀActive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,
140
135
mA
tclKꢀ=ꢀtCLK(min),ꢀtRCꢀ=ꢀtRC(min)
(4)
Idd2p
PrechargeꢀStandbyꢀCurrent
(InꢀPower-DownꢀMode)
CKEꢀ≤ꢀVil (max),ꢀtCKꢀ=ꢀ15ns
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
1
1
1
1
mA
mA
(4)
Idd2ps
PrechargeꢀStandbyꢀCurrentꢀꢀꢀꢀꢀꢀ
WithꢀClockꢀStop
CKEꢀ≤ꢀVil (max),ꢀCLKꢀ≤ꢀVil (max)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
(InꢀPower-DownꢀMode)
(2)
Idd2n
PrechargeꢀStandbyꢀCurrent
(InꢀNonꢀPower-DownꢀMode)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
tCKꢀ=ꢀ15ꢀns
45
30
45
30
mA
mA
Idd2ns
PrechargeꢀStandbyꢀCurrentꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
WithꢀClockꢀStop
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
AllꢀInputsꢀStable
(InꢀNon-PowerꢀDownꢀMode)
(2)
Idd3p
ActiveꢀStandbyꢀCurrent
(InꢀPower-DownꢀMode)
CKEꢀ≤ꢀVil (max),ꢀCSꢀ≥ꢀVddꢀ-ꢀ0.2V
tCKꢀ=ꢀ15ꢀns
4
3
4
3
mA
mA
Idd3ps
ActiveꢀStandbyꢀCurrent
WithꢀClockꢀStop
CKEꢀ≤ꢀVil (max),ꢀCLKꢀ≤ꢀVil (max)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V
(InꢀPower-DownꢀMode)
(2)
Idd3n
ActiveꢀStandbyꢀCurrent
(InꢀNonꢀPower-DownꢀMode)
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
tCKꢀ=ꢀ15ꢀns
55
30
55
30
mA
mA
Idd3ns
ActiveꢀStandbyꢀCurrent
WithꢀClockꢀStop
CSꢀ≥ꢀVddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ꢀVih (min)
AllꢀInputsꢀStable
(InꢀNonꢀPower-DownꢀMode)
Idd4
OperatingꢀCurrent
AllꢀBanksꢀActive,ꢀBLꢀ=4,ꢀCLꢀ=ꢀ3
tCKꢀ=ꢀtCK(min)
180
170
mA
Idd5
Idd6
Idd7
Auto-RefreshꢀCurrent
Self-RefreshꢀCurrent
tRCꢀ=ꢀtRC(min),ꢀtCLKꢀ=ꢀtCLK(min)
180
1.2
170
1.2
mA
mA
mA
CKEꢀ≤ꢀ0.2V
Self-Refresh:ꢀCKEꢀ=ꢀLOW;ꢀtCKꢀ=ꢀtCKꢀ(MIN); FullꢀArray,ꢀ85oC
1200
Address,ꢀControl,ꢀandꢀDataꢀbusꢀinputsꢀareꢀ FullꢀArray,ꢀ45oC
900
1000
750
900
675
850
640
800
600
stable
HalfꢀArray,ꢀ85oC
HalfꢀArray,ꢀ45oC
1/4thꢀArray,ꢀ85oC
1/4thꢀArray,ꢀ45oC
1/8thꢀArray,ꢀ85oC
1/8thꢀArray,ꢀ45oC
1/16thꢀArray,ꢀ85oC
1/16thꢀArray,ꢀ45oC
(3,4)
Izz
DeepꢀPowerꢀDownꢀCurrent
CKEꢀ≤ꢀ0.2V
15
15
mA
Notes:
1.ꢀ Iddꢀ(max)ꢀisꢀspecifiedꢀatꢀtheꢀoutputꢀopenꢀcondition.
2.ꢀ Inputꢀsignalsꢀareꢀchangedꢀoneꢀtimeꢀduringꢀ30ns.
3.ꢀꢀIzzꢀvaluesꢀshownꢀareꢀnominalꢀatꢀ25oC.ꢀꢀIzzꢀisꢀnotꢀtested.
4.ꢀꢀTestedꢀafterꢀ500msꢀdelay.
5.ꢀꢀNotꢀavailableꢀforꢀ2.5V,ꢀx32ꢀoption
Integrated Silicon Solution, Inc. - www.issi.comꢀ
17
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
AC ELECTRICAL CꢁARACTERISTICS(1, 2, 3)
-64
Min. Max.
-7
-75E
Symbol Parameter
Min.
Max. Min. Max. Unit
tCK3
ClockꢀCycleꢀTime
CASꢀLatencyꢀ=ꢀ3
6
–
7
–
–
–
ns
tCK2
tAC3
CASꢀLatencyꢀ=ꢀ2
CASꢀLatencyꢀ=ꢀ3
10
–
–
10
–
–
7.5
–
–
–
ns
ns
AccessꢀTimeꢀFromꢀCLK
5.4
5.4
tAC2
tCHI
tCL
CASꢀLatencyꢀ=ꢀ2
–
8
–
–
–
–
8
–
–
–
–
5.5
–
ns
ns
ns
ns
CLKꢀHIGHꢀLevelꢀWidth
CLKꢀLOWꢀLevelꢀWidth
OutputꢀDataꢀHoldꢀTime
2.5
2.5
2.7
2.5
2.5
2.7
2.5
2.5
2.7
–
tOH3
CASꢀLatencyꢀ=ꢀ3
CASꢀLatencyꢀ=ꢀ2
–
tOH2
tLZ
2.7
0
–
–
2.7
0
–
–
2.7
0
–
–
–
ns
ns
ns
OutputꢀLOWꢀImpedanceꢀTime
tHZ
OutputꢀHIGHꢀImpedanceꢀTime CASꢀLatencyꢀ=ꢀ3
2.7
5.4
2.7
5.4
2.7
CASꢀLatencyꢀ=ꢀ2
InputꢀDataꢀSetupꢀTimeꢀ(2)
InputꢀDataꢀHoldꢀTimeꢀ(2)
AddressꢀSetupꢀTimeꢀ(2)
AddressꢀHoldꢀTimeꢀ(2)
CKEꢀSetupꢀTimeꢀ(2)
CKEꢀHoldꢀTimeꢀ(2)
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
8
–
–
–
–
–
–
–
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
8
–
–
–
–
–
–
–
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
5.5
–
tDS
ns
ns
ns
ns
ns
ns
ns
tDH
tAS
–
–
tAH
–
tCKS
tCKH
tCS
–
–
CommandꢀSetupꢀTimeꢀ(CS,ꢀ
RAS,ꢀCAS,ꢀWE,ꢀDQM)(2)
CommandꢀHoldꢀTimeꢀ(CS,ꢀ
RAS,ꢀCAS,ꢀWE,ꢀDQM)(2)
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ
/ꢀACTꢀtoꢀACT)
–
tCH
1.0
60
42
18
18
12
12
–
1.0
67.5
45
–
1.0
–
–
ns
ns
tRC
–
–
67.5
tRAS
tRP
CommandꢀPeriodꢀ(ACTꢀtoꢀ
PRE)
100K
100K
45 100K ns
CommandꢀPeriodꢀ(PREꢀtoꢀ
ACT)
–
–
–
–
20
–
–
–
–
15
15
15
15
–
–
–
–
ns
ns
ns
ns
tRCD
tRRD
tDPL
tDAL
ActiveꢀCommandꢀtoꢀRead/
WriteꢀCommandꢀDelayꢀTime
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀ
ACTꢀ[1])
20
14
InputꢀDataꢀtoꢀPrecharge
CommandꢀDelayꢀTime
InputꢀDataꢀtoꢀActive/Refresh
CommandꢀDelayꢀTimeꢀ(Duringꢀ
Auto-Precharge)
14
30
–
35
–
30
–
ns
tMRD
tDDE
tSRX
tT
ModeꢀRegisterꢀProgramꢀTime
PowerꢀDownꢀExitꢀSetupꢀTime
Self-RefreshꢀExitꢀTime
TransitionꢀTime
12
6
–
–
14
7
–
–
15
7.5
70
0.3
–
–
–
ns
ns
ns
ns
ms
70
0.3
–
–
70
0.3
–
–
–
1.2
64
1.2
64
1.2
64
tREF
RefreshꢀCycleꢀTimeꢀ(4096)
Notes:
1.ꢀ Theꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2.ꢀ MeasuredꢀwithꢀtTꢀ=ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tRꢀ/2ꢀ-ꢀ0.5)ꢀnsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.
3.ꢀ Theꢀreferenceꢀlevelꢀisꢀ1.4Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀ
Vih(min.)ꢀandꢀVilꢀ(max).
4.ꢀꢀNotꢀavailableꢀforꢀ2.5V,ꢀx32ꢀoption.ꢀ
18ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
OPERATING FREQUENCY/LATENCY RELATIONSꢁIPS
SYMBOL PARAMETER
-6
6
-7
7
-75E
UNITS
ns
—
ClockꢀCycleꢀTime
7.5
133
2
—
OperatingꢀFrequency
166
3
143
3
MHz
tcac
trcd
trac
trc
CASꢀꢀLatency
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycleꢀ
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTime
RASꢀLatencyꢀ(trcdꢀ+ꢀtcac)
3
3
2
6
6
4
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)
CommandꢀPeriodꢀ(PREꢀtoꢀACT)
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])
ColumnꢀCommandꢀDelayꢀTime
10
7
10
7
9
tras
trp
6
3
3
2
trrd
tccd
2
2
2
1
1
1
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
tdpl
tdal
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTime
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTime
2
5
2
5
2
4
cycle
cycleꢀ
(DuringꢀAuto-Precharge)
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime
trbd
twbd
trql
twdl
3
0
3
0
3
0
3
0
2
0
2
0
cycleꢀ
cycleꢀ
cycleꢀ
cycleꢀ
(Read)
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTime
(Write)
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime
(Read)
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTime
(Write)
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)
tpql
tqmd
tdmd
tmrd
–2
2
–2
2
–2
2
cycle
cycle
cycle
cycle
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)
0
0
0
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTime
2
2
2
Integrated Silicon Solution, Inc. - www.issi.comꢀ
19
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Ordering Information – Vdd = 3.3V
Commercial Range: (0°C to +70°C)
Configuration
16Mx8
Frequency (Mꢁz) Speed (ns) Order Part No.
Package
143
166
7
6
IS42SM81600E-7TL
IS42SM16800E-6TL
IS42SM16800E-6BL
IS42SM16800E-7TL
IS42SM16800E-7BL
IS42SM32400E-6TL
IS42SM32400E-6BL
IS42SM32400E-7TL
IS42SM32400E-7BL
54-pinꢀTSOPꢀII,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA,ꢀLead-free
8Mx16
143
166
143
7
6
7
4Mx32
Industrial Range: (–40ºC to 85ºC)
Configuration
16Mx8
Frequency (Mꢁz) Speed (ns) Order Part No.
Package
143
166
7
6
IS42SM81600E-7TLI
IS42SM16800E-6TLI
IS42SM16800E-6BLI
IS42SM16800E-7TLI
IS42SM16800E-7BI
IS42SM16800E-7BLI
IS42SM16800E-75EBLI
IS42SM32400E-6TLI
IS42SM32400E-6BLI
IS42SM32400E-7TLI
IS42SM32400E-7BI
IS42SM32400E-7BLI
54-pinꢀTSOPꢀII,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA
8Mx16
143
7
54-BallꢀBGA,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA
133
166
7.5
6
4Mx32
143
7
90-BallꢀBGA,ꢀLead-free
*ContactꢀISSIꢀforꢀLeadedꢀPartsꢀSupport.
20ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Ordering Information – Vdd = 2.5V
Commercial Range: (0°C to +70°C)
Configuration
16Mx8
Frequency (Mꢁz) Speed (ns) Order Part No.
Package
143
166
7
6
IS42RM81600E-7TL
IS42RM16800E-6TL
IS42RM16800E-6BL
IS42RM16800E-7TL
IS42RM16800E-7BL
IS42RM32400E-7TL
IS42RM32400E-7BL
54-pinꢀTSOPꢀII,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA,ꢀLead-free
8Mx16
143
143
7
7
4Mx32
Industrial Range: (–40ºC to 85ºC)
Configuration
16Mx8
Frequency (Mꢁz) Speed (ns) Order Part No.
Package
143
166
7
6
IS42RM81600E-7TLI
IS42RM16800E-6TLI
IS42RM16800E-6BLI
IS42RM16800E-7TLI
IS42RM16800E-7BI
IS42RM16800E-7BLI
IS42RM32400E-7TLI
IS42RM32400E-7BI
IS42RM32400E-7BLI
54-pinꢀTSOPꢀII,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA,ꢀLead-free
54-pinꢀTSOPꢀII,ꢀLead-free
54-BallꢀBGA
8Mx16
143
143
7
7
54-BallꢀBGA,ꢀLead-free
86-pinꢀTSOPꢀII,ꢀLead-free
90-BallꢀBGA
4Mx32
90-BallꢀBGA,ꢀLead-free
*ContactꢀProductꢀMarketingꢀforꢀLeadedꢀPartsꢀSupport.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
21
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
22ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Integrated Silicon Solution, Inc. - www.issi.comꢀ
23
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
24ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. B
04/15/2011
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
D1
Integrated Silicon Solution, Inc. - www.issi.comꢀ
25
Rev. B
04/15/2011
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