IS42VM32160C-10BI [ISSI]
512Mb Mobile Synchronous DRAM;
| 型号： | IS42VM32160C-10BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512Mb Mobile Synchronous DRAM 动态存储器 |
| 文件： | 总17页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42VM32160C
16Mx32
Preliminary Information
JULY 2010
512Mb Mobile Synchronous DRAM
FEATURES:
DESCRIPTION:
ISSI's IS42VM32160C is a 512Mb Mobile Synchronous
DRAM configured as a quad 4M x32 DRAM. It achieves
high-speed data transfer using a pipeline architecture
with a synchronous interface. All inputs and outputs sig-
nals are registered on the rising edge of the clock input,
CLK. The 512Mb SDRAM is internally configured by
stacking two 256Mb, 16Mx16 devices. Each of the 4M
x32ꢀbanksꢀisꢀorganizedꢀasꢀ8192ꢀrowsꢀbyꢀ512ꢀcolumnsꢀ
by 32 bits.
•ꢀ Fully synchronous; all signals referenced to a
positive clock edge
•ꢀ Internal bank for hiding row access and pre-
charge
•ꢀ Programmable CAS latency: 2, 3
•ꢀ Programmable Burst Length: 1, 2, 4, 8, and Full
Page
•ꢀ Programmable Burst Sequence:
•ꢀ Sequential and Interleave
•ꢀ Auto Refresh (CBR)
•ꢀ TCSR (Temperature Compensated Self Refresh)
KEY TIMING PARAMETERS
Parameter
-10
Unit
•ꢀ PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
•ꢀ Deep Power Down Mode (DPD)
•ꢀ Driver Strength Control (DS): 1/4, 1/2, and Full
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from CLK
CAS Latency = 3
CAS Latency = 2
10
12
ns
ns
OPTIONS:
•ꢀ Configuration:ꢀ16Mx32
•ꢀ PowerꢀSupply:
Vd d /Vd d q = 1.8V
•ꢀ Package:ꢀ90ꢀBallꢀBGAꢀ(8mmx13mm)
•ꢀ TemperatureꢀRange:ꢀ
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
100
83
Mhz
Mhz
8.0
ns
ns
9.0
•ꢀ Dieꢀrevision:ꢀC
ADDRESS TABLE
Parameter
16Mx32
Configuration
4M x 32 x 4 banks
BA0, BA1
A10/AP
A0 – A12
A0 – A8
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
8K / 64ms
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. 00B
07/21/2010
IS42VM32160C
FUNCTIONAL BLOCK DIAGRAM (16Mx16)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
2
DQ 0-15
13
V
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
A10
A12
A11
A9
Q
CONTROLLER
16
16
A8
A7
REFRESH
COUNTER
A6
A5
8192
A4
A3
A2
A1
A0
BA0
BA1
8192
MEMORY CELL
ARRAY
8192
8192
13
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
13
13
SENSEꢀAMPꢀI/OꢀGATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROLꢀLOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
FUNCTIONAL BLOCK DIAGRAM (16Mx32)
CS
CLK
CKE
Die 01
Die 02
Command
Addresses
DQ0 –DQ31
2
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
PIN DESCRIPTIONS
Symbol
CLK
Type
Input
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
ClockꢀEnable:ꢀCKEꢀactivatesꢀ(HIGH)ꢀandꢀdeactivatesꢀ(LOW)ꢀtheꢀCLKꢀsignal.ꢀIfꢀCKEꢀgoesꢀlowꢀsynchronouslyꢀ
with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE
becomes asynchronous until exiting the same mode.The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
BA0, BA1
A0-A12
Input
Input
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respectivebank.DuringaPrechargecommand,A10issampledtodetermineifallbanksaretobeprecharged
(A10ꢀ=HIGH).
The address inputs also provide the op-code during a Mode Register Set .
CS
Input
Input
ChipSelect:CSꢀenablesꢀ(sampledꢀLOW)ꢀandꢀdisablesꢀ(sampledꢀHIGH)ꢀtheꢀcommandꢀdecoder.Allꢀcommandsꢀ
are masked when CSꢀisꢀsampledꢀHIGH.ꢀCS provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
RAS
Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and
WE signals and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS
isꢀassertedꢀ“HIGH,”ꢀeitherꢀtheꢀBankActivateꢀcommandꢀorꢀtheꢀPrechargeꢀcommandꢀisꢀselectedꢀbyꢀtheꢀWE
signal. When the WEꢀisꢀassertedꢀ“HIGH,”ꢀtheꢀBankActivateꢀcommandꢀisꢀselectedꢀandꢀtheꢀbankꢀdesignatedꢀ
by BA is turned on to the active state.When the WE is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
CAS
Input
Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS
and WE signals and is latched at the positive edges of CLK. When RASꢀisꢀheldꢀ“HIGH”ꢀandꢀCS is asserted
“LOW,”the column access is started by asserting CAS ”LOW.”Then, the Read orWrite command is selected
by asserting WEꢀ“LOW”ꢀorꢀ“HIGH.”
WE
Input
Input
Write Enable:The WE signal defines the operation commands in conjunction with the RAS and CAS signals
and is latched at the positive edges of CLK.The WE input is used to select the BankActivate or Precharge
command and Read or Write command.
DQM0-3
Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
areꢀplacedꢀinꢀaꢀhigh-zꢀstateꢀwhenꢀDQMꢀisꢀsampledꢀHIGH.ꢀInputꢀdataꢀisꢀmaskedꢀwhenꢀDQMꢀisꢀsampledꢀ
HIGHꢀduringꢀaꢀwriteꢀcycle.ꢀOutputꢀdataꢀisꢀmaskedꢀ(two-clockꢀlatency)ꢀwhenꢀDQMꢀisꢀsampledꢀHIGHꢀduringꢀ
a read cycle.DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
DQ0-31
Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edge of CLK. The I/Os are
Output byte-maskable during Reads and Writes.
Integrated Silicon Solution, Inc.
3
Rev. 00B
07/21/2010
IS42VM32160C
PIN CONFIGURATION
PACKAGEꢀCODE:ꢀBꢀ90ꢀBALLꢀFBGAꢀ(TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ13.00ꢀmmꢀBody,ꢀ0.8ꢀmꢀBallꢀPitch)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
B
C
D
E
F
G
H
J
A4
A7
A5
A8
A6
A10
NC
A0
A1
A12
BA1 A11
CLK CKE A9
DQM1 NC NC
BA0
CS RAS
K
L
CAS WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
M
N
P
R
PIN DESCRIPTIONS
A0-A12
A0-A8
Row Address Input
Column Address Input
Bank Select Address
WE
Write Enable
DQM0-DQM3 x32 Input/Output Mask
BA0, BA1
Vd d
Vss
Vd d q
Vs s q
NC
Power
DQ0 to DQ31 Data I/O
Ground
CLK
CKE
CS
System Clock Input
Power Supply for I/O Pin
GroundꢀforꢀI/OꢀPin
No Connect
Clock Enable
Chip Select
RAS
CAS
Row Address Strobe Command
Column Address Strobe Command
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Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
Mobile SDRAM Functionality
ISSI’s 512Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but
offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth
tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile
Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The
Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define
the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS
Latency,ꢀoperatingꢀmode,ꢀandꢀaꢀwriteꢀburstꢀmode.ꢀTheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀREGISTERꢀ
command and will retain the stored information until it is programmed again or the device loses power.
The EMR controls the functions beyond those controlled by the MR. These additional functions are special features
of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR),ꢀandꢀoutputꢀdriveꢀstrength.ꢀTheꢀEMRꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀwithꢀBA1ꢀ
= 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not
programming the extended mode register upon initialization will result in default settings for the low-power features.
The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks)
refresh.
Mode Register Definition
The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE
REGISTERꢀDEFINITION.ꢀTheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀwillꢀ
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 -
M6ꢀspecifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀmode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10,ꢀ
M11, and M12 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Integrated Silicon Solution, Inc.
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Rev. 00B
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IS42VM32160C
MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
M9 Mode
BA1
BA0
Mode Register Definition
Program Mode Register
Reserved
To ensure compatibility with future devices,
should program A12, A11, A10 = "0"
0
0
0
1
0
1
Programmed Burst Length
Single Location Access
1
1
0
1
Program Extended Mode Register
Reserved
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeterminesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀ
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x32) when the burst length is set to two; by A2-A8 (x32) when the
burst length is set to four; and by A3-A8 (x32) when the burst length is set to eight. The remaining (least significant)
address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached.
6
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Length
A 0
2
4
0
1
0-1
1-0
0-1
1-0
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ꢀ
Fullꢀ ꢀꢀꢀnꢀ=ꢀA0-A9ꢀ(x8)ꢀꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cn + 3, Cn + 4...
…Cn - 1,
ꢀ
Page
(y)
(location 0-y)
Cn…
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8
are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.
Integrated Silicon Solution, Inc.
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IS42VM32160C
Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀtheꢀ
programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
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Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
EꢀTENDED MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Ext. Mode Reg. (Ex)
PASR
E2 E1 E0 Partial Array Self Refresh
Coverage
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fully array (4 banks) - (Default)
Half array (banks 0, 1)
Quarter array (bank 0)
Reserved
Reserved
One-eighth array (1/2 bank 0)
One-sixteenth array (1/4 bank 0)
Reserved
TCSR
E4 E3 Max. Case Temp.
0
0
1
1
0
1
0
1
70oC
45oC
15oC
85oC (Default)
DS
E6 E5 Driver Strength
0
0
1
1
0
1
0
1
Full strength driver (Default)
Half strength driver
Quarter strength driver
Reserved
set to "0"
E12 E11 E10 E9 E8 E7 E6-E0
0
–
0
–
0
–
0
–
0
–
0
–
Valid Normal operation
All other states reserved
–
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Reserved
Program Extended mode Register
Reserved
TheꢀextendedꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀMODEꢀREGISTERꢀSETꢀcommandꢀ(BA1ꢀ=ꢀ1,ꢀBA0ꢀ=ꢀ0)ꢀandꢀ
retains the stored information until it is programmed again or the device loses power. The extended mode register
must be programmed with E7 through E12 set to “0.” The extended mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation. The extended mode register must be
programmed to ensure proper operation.
Temperature-Compensated Self Refresh (TCSR)
TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature
of the mobile device. This allows great power savings during self refresh during most operating temperature ranges.
Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data
during self refresh.
Integrated Silicon Solution, Inc. ꢀ
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IS42VM32160C
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures,
requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to
accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the
power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher
temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self
refresh. The default for ISSI 512Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of
operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells
more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile
SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by
a significant amount. There are four temperature settings, which will vary the self refresh current according to the
selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal
temperatures.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory
that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks
0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected.
WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in
PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the two-
bank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
Driver Strength (DS)
Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set
according to the application’s requirements. The default is Full Driver Strength.
Deep Power Down (DPD)
Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory
array of the mobile device. Data will be lost once deep power down mode is executed.
DPDꢀmodeꢀisꢀenteredꢀbyꢀhavingꢀallꢀbanksꢀidle,ꢀCSꢀandꢀWEꢀheldꢀlow,ꢀwithꢀRASꢀandꢀCASꢀHIGHꢀatꢀtheꢀrisingꢀedgeꢀofꢀ
the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted
HIGH.ꢀUponꢀexitꢀfromꢀDPDꢀmode,ꢀatꢀleastꢀ200ms of valid clocks with either NOP or COMMAND INHIBIT commands
are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required.
10
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAꢀIMUM RATINGS(1)
Symbol Parameters
Rating
-0.35 to +2.8
-0.35 to +2.8
-0.35 to Vd d +0.5
-0.35 to Vd d +0.5
50
Unit
V
V
V
V
Vd d
Vd d q
Vin
Supply Voltage (with respect to Vss)
Supply Voltage for Output (with respect to Vs s q )
Input Voltage (with respect to Vss)
Output Voltage (with respect to Vs s q )
Short circuit output current
Vo u t
Ic s
mA
W
Pd
Power Dissipation (Ta = 25oC)
1
To p t
Operating Temperature
Com.
Ind.
0 to +70
-40 to +85
°C
°C
Ts t g
Storage Temperature
–65 to +150
°C
Note:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀ
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All voltages are reference to Vss.
CAPACITANCE
Symbol
Parameter
Min.
5.0
5.0
4
Max.
7.0
Unit
pF
Cin
Input Capacitance, address and control pin
Input Capacitance, CLK pin
Data Input/Output Capacitance
Cc l k
Cio
7.6
pF
6.5
pF
Integrated Silicon Solution, Inc.
11
Rev. 00B
07/21/2010
IS42VM32160C
DC RECOMMENDED OPERATING CONDITIONS
IS42VMxxx - 1.8V Operation
Symbol Parameters
Min.
1.7
1.7
Typ.
1.8
1.8
–
Max.
1.95
1.95
Vd d q +0.3
0.2
Unit
V
V
V
V
Vd d
Supply Voltage
Vd d q
I/O Supply Voltage
Input High Voltage
Input Low Voltage
(1)
Vih
0.8xVd d q
-0.3
(2)
Vil
–
Iil
Input Leakage Current (0V ≤ Vin ≤ Vd d )
Output Leakage Current (Output disabled, 0V ≤ Vo u t ≤ Vd d )
Output High Voltage Current (Io h = -100mA)
Output Low Voltage Current (Io l = 100mA)
-1
-1.5
0.9xVd d q
–
–
–
–
–
+1
+1.5
–
µA
µA
V
Io l
Vo h
Vo l
0.2
V
Notes:
1. Vih (overshoot): Vih (max) = Vd d q +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
12
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
DC ELECTRICAL CHARACTERISTICS VDD = 1.8V
Symbol
Parameter
Test Condition
–10
Unit
Id d 1(1)
Operating Current
One Bank Active, CL = 3, BL = 1,
120
mA
tclk = tCLK(min), tRC = tRC(min)
CKE ≤ Vil (max), tCK = 15ns
(4)
Id d 2p
Precharge Standby Current
2
2
mA
mA
(In Power-Down Mode)
CS ≥ Vd d - 0.2V
(4)
Id d 2p s
Precharge Standby Current
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
(2)
Id d 2n
Precharge Standby Current
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
30
14
mA
mA
(In Non Power-Down Mode)
Precharge Standby Current
tCK = 15 ns
Id d 2n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non-Power Down Mode)
Active Standby Current
(2)
Id d 3p
CKE ≤ Vil (max), CS ≥ Vd d - 0.2V
4
2
mA
mA
(In Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3p s
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
Active Standby Current
(2)
Id d 3n
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
40
20
mA
mA
(In Non Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non Power-Down Mode)
Operating Current
Id d 4
All Banks Active, BL =4, CL = 3
150
mA
tCK = tCK(min)
Id d 5
Id d 6
Id d 7
Auto-Refresh Current
Self-Refresh Current
Self-Refresh: CKE = LOW; tc k = tc k (MIN); Full Array, 85oC
Address, Control, and Data bus inputs are Full Array, 45oC
tRC = tRC(min), tCLK = tCLK(min)
220
2.4
mA
mA
mA
CKE ≤ 0.2V
2400
1600
2000
1340
1600
1080
1400
940
stable
Half Array, 85oC
Half Array, 45oC
1/4th Array, 85oC
1/4th Array, 45oC
1/8th Array, 85oC
1/8th Array, 45oC
1/16th Array, 85oC
1/16th Array, 45oC
1200
800
(3,4)
Iz z
Deep Power Down Current
CKE ≤ 0.2V
40
mA
Notes:
1. Id d (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25oC. Izz is not tested.
4. Tested after 500ms delay
Integrated Silicon Solution, Inc.
13
Rev. 00B
07/21/2010
IS42VM32160C
AC ELECTRICAL CHARACTERISTICS(1, 2, 3)
-10
Symbol Parameter
Min.
Max. Unit
tCK3
Clock Cycle Time
CAS Latency = 3
10
–
ns
tCK2
tAC3
CAS Latency = 2
CAS Latency = 3
12
–
–
8
ns
ns
Access Time From CLK
tAC2
tCHI
tCL
CAS Latency = 2
–
9
–
–
–
ns
ns
ns
ns
CLKꢀHIGHꢀLevelꢀWidth
CLK LOW Level Width
Output Data Hold Time
2.5
2.5
2.7
tOH3
CAS Latency = 3
CAS Latency = 2
tOH2
tLZ
2.7
0
–
–
ns
ns
ns
Output LOW Impedance Time
tHZ
OutputꢀHIGHꢀImpedanceꢀTime CAS Latency = 3
2.7
8.0
CAS Latency = 2
Input Data Setup Time (2)
Input Data Hold Time (2)
Address Setup Time (2)
Address Hold Time (2)
CKE Setup Time (2)
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
9.0
–
tDS
ns
ns
ns
ns
ns
ns
ns
tDH
tAS
–
–
tAH
–
tCKS
tCKH
tCS
–
CKE Hold Time (2)
–
Command Setup Time (CS,
RAS, CAS, WE, DQM)(2)
Command Hold Time (CS,
RAS, CAS, WE, DQM)(2)
Command Period (REF to REF
/ ACT to ACT)
–
tCH
1.0
90
60
24
24
20
20
–
ns
ns
ns
ns
ns
ns
ns
tRC
–
tRAS
tRP
Command Period (ACT to
PRE)
100K
Command Period (PRE to
ACT)
–
–
–
–
tRCD
tRRD
tDPL
tDAL
Active Command to Read/
Write Command Delay Time
Command Period (ACT [0] to
ACT [1])
Input Data to Precharge
Command Delay Time
Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
48
–
ns
tMRD
tDDE
tSRX
tT
Mode Register Program Time
Power Down Exit Setup Time
Self-Refresh Exit Time
Transition Time
20
10
80
0.3
–
–
–
ns
ns
ns
ns
ms
–
1.2
64
tREF
RefreshꢀCycleꢀTimeꢀ(8192)
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
Vih(min.) and Vil (max).
14
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-10
10
100
3
UNITS
ns
—
Clock Cycle Time
—
Operating Frequency
MHz
tc a c
tr c d
tr a c
tr c
CAS Latency
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
Active Command To Read/Write Command Delay Time
RAS Latency (tr c d + tc a c )
3
CAS Latency = 3
6
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
9
tr a s
tr p
6
3
tr r d
tc c d
2
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
td p l
td a l
Input Data To Precharge Command Delay Time
2
5
cycle
cycle
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
tr b d
tw b d
tr q l
tw d l
CAS Latency = 3
CAS Latency = 3
CAS Latency = 3
3
0
3
0
cycle
cycle
cycle
cycle
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
tp q l
tq m d
td m d
tm r d
-2
2
cycle
cycle
cycle
cycle
DQM To Input Delay Time (Write)
0
Mode Register Set To Command Delay Time
2
Integrated Silicon Solution, Inc.
15
Rev. 00B
07/21/2010
IS42VM32160C
Ordering Information – Vd d = 1.8V
Commercial Range: (0°C to +70°C)
Frequency
Speed (ns) Order Part No.
10 IS42VM32160C-10BL
Package
100 MHz
8x13mmꢀBGA,ꢀLead-free
Industrial Range: (-40°C to +85°C)
Frequency
Speed (ns) Order Part No.
10 IS42VM32160C-10BLI
IS42VM32160C-10BI
Package
100 MHz
8x13mmꢀBGA,ꢀLead-free
8x13mmꢀBGA
*Contact ISSI for leaded parts support.
16
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
Integrated Silicon Solution, Inc.
17
Rev. 00B
07/21/2010
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