IS42VM32800D-75TLI [ISSI]
Synchronous DRAM, 8MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86;
| 型号： | IS42VM32800D-75TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 8MX32, 5.4ns, CMOS, PDSO86, 0.400 INCH, LEAD FREE, TSOP2-86 动态存储器 光电二极管 |
| 文件： | 总23页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42VM83200D / IS42VM16160D / IS42VM32800D
32Mx8, 16Mx16, 8Mx32
256Mb Mobile Synchronous DRAM
Preliminary Information
AUGUST 2010
DESCRIPTION
FEATURES
ISSI's 256Mb Mobile Synchronous DRAM achieves high-
speed data transfer using pipeline architecture. All input
and output signals refer to the rising edge of the clock
input. Both write and read accesses to the SDRAM are
burst oriented. The 256Mb Mobile Synchronous DRAM
is designed to minimize current consumption making it
ideal for low-power applications. Both TSOP and BGA
packages are offered, including industrial grade products.
•ꢀ Fully synchronous; all signals referenced to a
positive clock edge
•ꢀ Internal bank for hiding row access and pre-
charge
•ꢀ Programmable CAS latency: 2, 3
•ꢀ Programmable Burst Length: 1, 2, 4, 8, and Full
Page
•ꢀ Programmable Burst Sequence:
•ꢀ Sequential and Interleave
•ꢀ Auto Refresh (CBR)
KEY TIMING PARAMETERS
-8(1)
-10(2)
Unit
•ꢀ TCSR (Temperature Compensated Self Refresh)
Parameter
•ꢀ PASR (Partial Arrays Self Refresh): 1/16, 1/8,
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from CLK
CAS Latency = 3
CAS Latency = 2
1/4, 1/2, and Full
8
10
12
ns
ns
•ꢀ Deep Power Down Mode (DPD)
•ꢀ Driver Strength Control (DS): 1/4, 1/2, and Full
10
125
100
100
83
Mhz
Mhz
OPTIONS
•ꢀ Configurations:
- 32M x 8
- 16M x 16
- 8M x 32
•ꢀ Power Supply
6
9
8
ns
ns
10
IS42VMxxx – Vd d /Vd d q = 1.8V
•ꢀ Packages:
Notes:
1. Available for x8/x16 only
2. Available for x32 only
x8 / x16 –TSOP II (54), BGA (54) [x16 only]
x32 – TSOP II (86), BGA (90)
•ꢀ Temperature Range:
Commercial (0°C to +70°C)
Industrial (–40 ºC to 85 ºC)
ADDRESSING TABLE
Parameter
32M x 8
16M x 16
8M x 32
Configuration
8M x 8 x 4 banks
8K/64ms
A0-A12
4M x 16 x 4 banks
8K/64ms
A0-A12
2M x 32 x 4 banks
4K/64ms
A0-A11
Refresh Count
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
A0-A9
A0-A8
A0-A8
BA0, BA1
A10
BA0, BA1
A10
BA0, BA1
A10
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated
Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
1
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
General Description
ISSI’s 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V Vd d /
Vd d q memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous
interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All
signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (VDD =
1.8V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave between internal banks to hide precharge time and the capability
to randomly change column addresses on each clock cycle during burst access.
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented
starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The
registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command
in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with
address bits registered are used to select the starting column location for the burst access. Programmable READ or
WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM (FOR 16Mx16 BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
13
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
A10
A12
A11
A9
V
Q
CONTROLLER
16
16
A8
A7
REFRESH
COUNTER
A6
A5
8192
A4
A3
A2
A1
A0
BA0
BA1
8192
MEMORY CELL
ARRAY
8192
8192
13
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
13
13
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
PIN CONFIGURATIONS
54 pin TSOP – Type II for x8
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VDDQ
NC
NC
V
DD
NC
WE
VSS
NC
DQM
CLK
CKE
A12
A11
A9
CAS
RAS
CS
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
32M x 8
CAS
Pin Name
32M x 8
A0–A12
A0–A9
BA0, BA1
DQ0–DQ7
CLK
Pin Name
Column Address Strobe Command
Write Enable
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
WE
DQM
VDD
VSS
Data Input/Output Mask
Power
Ground
VDDQ
VSSQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CKE
CS
Chip Select
RAS
Row Address Strobe Command
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
3
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
PIN CONFIGURATIONS
54 pin TSOP – Type II for x16
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
DQ8
VDD
VSS
DQML
WE
CAS
RAS
CS
NC
DQMH
CLK
CKE
A12
A11
A9
BA0
BA1
A10
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
V
SS
PIN DESCRIPTIONS
16M x16
A0–A12
A0–A8
BA0, BA1
DQ0–DQ15
CLK
Pin Name
16M x16
Pin Name
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
WE
Write Enable
DQML / DQMH Data Input/Output Mask
VDD
VSS
Power
Ground
VDDQ
VSSQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CKE
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
4
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
PIN CONFIGURATIONS
54-ball FBGA for x16 (Top View) (8.00mm x 13.00mm Body, 0.8mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8 NC VSS
DQMH CLK CKE
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
B
C
D
E
F
G
H
J
A12 A11
A9
A6
A4
A8
A7
A5
A0
A3
A1
A10
VSS
A2 VDD
PIN DESCRIPTIONS
16M x16
CAS
Pin Name
16M x16
A0–A12
A0–A8
BA0, BA1
DQ0–DQ15
CLK
Pin Name
Column Address Strobe Command
Write Enable
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
WE
DQML /
DQMH
Data Input/Output Mask
VDD
VSS
Power
Ground
CKE
VDDQ
VSSQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CS
Chip Select
RAS
Row Address Strobe Command
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
5
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
PIN CONFIGURATIONS
86 pin TSOP – Type II for x32
VDD
DQ0
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
2
DQ15
VDDQ
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SSQ
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
VDDQ
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ10
DQ9
V
SSQ
VDDQ
DQ7
NC
DQ8
NC
VDD
VSS
DQM0
WE
DQM1
NC
NC
CAS
RAS
CS
CLK
CKE
A9
A11
BA0
BA1
A10
A0
A8
A7
A6
A5
A1
A2
A4
A3
DQM2
DQM3
VDD
VSS
NC
DQ16
NC
DQ31
V
SSQ
VDDQ
DQ17
DQ18
DQ30
DQ29
VDDQ
VSSQ
DQ19
DQ20
DQ28
DQ27
V
SSQ
VDDQ
DQ21
DQ22
DQ26
DQ25
VDDQ
VSSQ
DQ23
DQ24
VDD
VSS
PIN DESCRIPTIONS
8M x32
A0–A11
A0–A8
BA0, BA1
DQ0–DQ31
CLK
Pin Name
8M x32
Pin Name
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
Write Enable
WE
DQM0 - DQM3 Data Input/Output Mask
VDD
VSS
Power
Ground
VDDQ
VSSQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CKE
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
6
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
PIN CONFIGURATIONS
90-ball FBGA for x32 (Top View) (8.00mm x 13.00mm Body, 0.8mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
B
C
D
E
F
G
H
J
A4
A7
A5
A8
A6
NC
A9
NC
A10
NC
A0
A1
BA1 A11
CLK CKE
DQM1 NC
BA0
CS RAS
K
L
CAS WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
M
N
P
R
PIN DESCRIPTIONS
8M x32
A0–A11
A0–A8
BA0, BA1
DQ0–DQ31
CLK
Pin Name
8M x32
WE
Pin Name
Row Address Input
Write Enable
Column Address Input
Bank Select Address
Data Input/Output
DQM0 - DQM3
VDD
Data Input/Output Mask
Power
VSS
Ground
System Clock Input
VDDQ
VSSQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
Column Address Strobe Command
CAS
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
7
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Mobile SDRAM Functionality
ISSI’s 256Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but
offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth
tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile
Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The
Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define
the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS
Latency, operating mode, and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it is programmed again or the device loses power.
The EMR controls the functions beyond those controlled by the MR. These additional functions are special features
of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command with BA1
= 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not
programming the extended mode register upon initialization will result in default settings for the low-power features.
The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks)
refresh.
Mode Register Definition
The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE
REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 -
M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10,
M11, and M12 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
8
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
BA1
BA0
Mode Register Definition
M9
0
Mode
1. Note: A12 x8 and x16, A11 x32
2. To ensure compatibility with future devices,
should program A12, A11, A10 = "0"
0
0
0
1
Program Mode Register
Reserved
Programmed Burst Length
Single Location Access
1
1
1
0
1
Program Extended Mode Register
Reserved
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x32), A1-A8 (x16) or A1-A9 (x8) when the burst length is set to two;
by A2-A8 (x32), A2-A8 (x16) or A2-A9 (x8) when the burst length is set to four; and by A3-A8 (x32), A3-A8 (x16) or
A3-A9 (x8) when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the
starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
9
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Length
A 0
2
4
0
1
0-1
1-0
0-1
1-0
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Full n = A0-A8 (x16, x32)
Page n = A0-A9 (x8)
Cn, Cn + 1, Cn + 2
Not Supported
Cn + 3, Cn + 4...
…Cn - 1,
(y)
(location 0-y)
Cn…
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8
are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.
10
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
11
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
EꢀTENDED MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Ext. Mode Reg. (Ex)
PASR
E2 E1 E0 Partial Array Self Refresh
Coverage
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fully array (4 banks) - (Default)
Half array (banks 0, 1)
Quarter array (bank 0)
Reserved
Reserved
One-eighth array (1/2 bank 0)
One-sixteenth array (1/4 bank 0)
Reserved
TCSR
E4 E3 Max. Case Temp.
0
0
1
1
0
1
0
1
70oC
45oC
15oC
85oC (Default)
DS
E6 E5 Driver Strength
0
0
1
1
0
1
0
1
Full strength driver (Default)
Half strength driver
Quarter strength driver
Reserved
set to "0"
E12 E11 E10 E9 E8 E7 E6-E0
0
–
0
–
0
–
0
–
0
–
0
–
Valid Normal operation
All other states reserved
–
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Reserved
Program Extended mode Register
Reserved
The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and retains
the stored information until it is programmed again or the device loses power. The extended mode register must be
programmed with E7 through E11 (or E12 for x8 & x16) set to “0.” The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation. The extended mode
register must be programmed to ensure proper operation.
Temperature-Compensated Self Refresh (TCSR)
TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature
of the mobile device. This allows great power savings during self refresh during most operating temperature ranges.
Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data
during self refresh.
12
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Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is
dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures,
requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to
accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the
power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher
temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self
refresh. The default for ISSI 256Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of
operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells
more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile
SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by
a significant amount. There are four temperature settings, which will vary the self refresh current according to the
selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal
temperatures.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory
that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks
0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected.
WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in
PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the two-
bank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
Driver Strength (DS)
Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set
according to the application’s requirements. The default is Full Driver Strength.
Deep Power Down (DPD)
Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory
array of the mobile device. Data will be lost once deep power down mode is executed.
DPD mode is entered by having all banks idle, CS and WE held low, with RAS and CAS HIGH at the rising edge of
the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted
HIGH. Upon exit from DPD mode, at least 200ms of valid clocks with either NOP or COMMAND INHIBIT commands
are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
13
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAꢀIMUM RATINGS(1)
Symbol
Vd d m a x
Vd d q m a x
Vin
Parameters
Rating
–0.35 to +2.8
–0.35 to +2.8
–0.35 to Vd d q + 0.5
–0.35 to Vd d q + 0.5
1
Unit
V
V
V
V
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
output Shorted Current
Vo u t
Pd m a x
Ic s
W
mA
50
To p r
operating Temperature
Com.
Ind.
0 to +70
–40 to +85
°C
°C
Ts t g
Storage Temperature
–65 to +150
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
CAPACITANCE CHARACTERISTICS - x8, x16
Symbol
Cin1
Parameters
Input Capacitance: CLK
Min.
2.5
Max.
3.5
Unit
pF
Cin2
Ci/o
Input Capacitance: All Other Input Pins
Data Input/Output Capacitance: I/Os
2.5
4.0
3.8
6.0
pF
pF
CAPACITANCE CHARACTERISTICS - x32
Symbol
Cin1
Parameters
Input Capacitance: CLK
Min.
2.5
Max.
3.5
Unit
pF
Cin2
Ci/o
Input Capacitance: All Other Input Pins
Data Input/Output Capacitance: I/Os
2.5
4.0
3.8
6.5
pF
pF
DC RECOMMENDED OPERATING CONDITIONS
IS42VMxxx - 1.8V Operation
Symbol Parameters
Min.
1.7
1.7
Typ.
1.8
1.8
–
Max.
1.95
1.95
Vd d q +0.3
0.8
Unit
V
V
V
V
Vd d
Supply Voltage
Vd d q
I/O Supply Voltage
Input High Voltage
Input Low Voltage
(1)
Vih
0.8xVd d q
-0.3
(2)
Vil
–
Iil
Input Leakage Current (0V ≤ Vin ≤ Vd d )
Output Leakage Current (Output disabled, 0V ≤ Vo u t ≤ Vd d )
Output High Voltage Current (Io h = -100mA)
-1
-1.5
0.9xVd d q
–
–
–
–
–
+1
+1.5
–
µA
µA
V
Io l
Vo h
Vo l
Output Low Voltage Current (Io l = 100mA)
0.2
V
Notes:
1. Vih (overshoot): Vih (max) = Vd d q +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
14
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
DC ELECTRICAL CHARACTERISTICS VDD = 1.8V (x8 and x16)
Symbol
Parameter
Test Condition
–8
–10
Unit
Id d 1(1)
Operating Current
One Bank Active, CL = 3, BL = 1,
90
80
mA
tclK = tCLK(min), tRC = tRC(min)
CKE ≤ Vil (max), tCK = 15ns
(4)
Id d 2p
Precharge Standby Current
1
1
1
1
mA
mA
(In Power-Down Mode)
CS ≥ Vd d - 0.2V
(4)
Id d 2p s
Precharge Standby Current
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
(2)
Id d 2n
Precharge Standby Current
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
20
7
20
7
mA
mA
(In Non Power-Down Mode)
Precharge Standby Current
tCK = 15 ns
Id d 2n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non-Power Down Mode)
Active Standby Current
(2)
Id d 3p
CKE ≤ Vil (max), CS ≥ Vd d - 0.2V
3
3
3
3
mA
mA
(In Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3p s
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
Active Standby Current
(2)
Id d 3n
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
25
10
25
10
mA
mA
(In Non Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non Power-Down Mode)
Operating Current
Id d 4
All Banks Active, BL = Full, CL = 3
115
100
mA
tCK = tCK(min)
Id d 5
Id d 6
Id d 7
Auto-Refresh Current
Self-Refresh Current
tRC = tRC(min), tCLK = tCLK(min)
130
1.2
110
1.2
mA
mA
mA
CKE ≤ 0.2V
Full Array, 85oC
Full Array, 45oC
Self-Refresh: CKE = LOW;
tc K = tc K (MIN); Address,
Control, and Data bus inputs Half Array, 85oC
1200
800
1000
670
800
540
700
470
600
400
are stable
Half Array, 45oC
1/4th Array, 85oC
1/4th Array, 45oC
1/8th Array, 85oC
1/8th Array, 45oC
1/16th Array, 85oC
1/16th Array, 45oC
(3,4)
Iz z
Deep Power Down Current
CKE ≤ 0.2V
20
20
mA
Notes:
1. Id d (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25oC. Izz is not tested.
4. Tested after 500ms delay
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
15
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
DC ELECTRICAL CHARACTERISTICS VDD = 1.8V (x32)
Symbol
Parameter
Test Condition
–8
–10
Unit
Id d 1(1)
Operating Current
One Bank Active, CL = 3, BL = 1,
110
90
mA
tclK = tCLK(min), tRC = tRC(min)
CKE ≤ Vil (max), tCK = 15ns
(4)
Id d 2p
Precharge Standby Current
1
1
1
1
mA
mA
(In Power-Down Mode)
CS ≥ Vd d - 0.2V
(4)
Id d 2p s
Precharge Standby Current
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
(2)
Id d 2n
Precharge Standby Current
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
20
7
20
7
mA
mA
(In Non Power-Down Mode)
Precharge Standby Current
tCK = 15 ns
Id d 2n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non-Power Down Mode)
Active Standby Current
(2)
Id d 3p
CKE ≤ Vil (max), CS ≥ Vd d - 0.2V
3
3
3
3
mA
mA
(In Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3p s
CKE ≤ Vil (max), CLK ≤ Vil (max)
With Clock Stop
CS ≥ Vd d - 0.2V
(In Power-Down Mode)
Active Standby Current
(2)
Id d 3n
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
25
10
25
10
mA
mA
(In Non Power-Down Mode)
Active Standby Current
tCK = 15 ns
Id d 3n s
CS ≥ Vd d - 0.2V, CKE ≥ Vih (min)
With Clock Stop
All Inputs Stable
(In Non Power-Down Mode)
Operating Current
Id d 4
All Banks Active, BL = Full, CL = 3
120
90
mA
tCK = tCK(min)
Id d 5
Id d 6
Id d 7
Auto-Refresh Current
Self-Refresh Current
tRC = tRC(min), tCLK = tCLK(min)
220
1.2
165
1.2
mA
mA
mA
CKE ≤ 0.2V
Full Array, 85oC
Full Array, 45oC
Self-Refresh: CKE = LOW;
tc K = tc K (MIN); Address,
Control, and Data bus inputs Half Array, 85oC
1200
800
1000
670
800
540
700
470
600
400
are stable
Half Array, 45oC
1/4th Array, 85oC
1/4th Array, 45oC
1/8th Array, 85oC
1/8th Array, 45oC
1/16th Array, 85oC
1/16th Array, 45oC
(3,4)
Iz z
Deep Power Down Current
CKE ≤ 0.2V
20
20
mA
Notes:
1. Id d (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Izz values shown are nominal at 25oC. Izz is not tested.
4. Tested after 500ms delay
16
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Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
AC ELECTRICAL CHARACTERISTICS(1, 2, 3)
-8
Min. Max. Min.
-10
Max. Unit
Symbol Parameter
tCK3
Clock Cycle Time
CAS Latency = 3
8
–
10
–
ns
tCK2
tAC3
CAS Latency = 2
CAS Latency = 3
10
–
–
6
12
–
–
ns
ns
Access Time From CLK
8.0
tAC2
tCHI
tCL
CAS Latency = 2
–
9
–
–
–
–
10
–
ns
ns
ns
ns
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
2.5
2.5
2.7
2.5
2.5
2.7
–
tOH3
CAS Latency = 3
CAS Latency = 2
–
tOH2
tLZ
2.7
0
–
–
6
2.7
0
–
–
ns
ns
ns
Output LOW Impedance Time
tHZ3
tHZ2
Output HIGH Impedance Time CAS Latency = 3
2.7
2.7
8.0
CAS Latency = 2
Input Data Setup Time (2)
Input Data Hold Time (2)
Address Setup Time (2)
Address Hold Time (2)
CKE Setup Time (2)
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
9
–
–
–
–
–
–
–
2.7
1.5
1.0
1.5
1.0
1.5
1.0
1.5
10
–
tDS
ns
ns
ns
ns
ns
ns
ns
tDH
tAS
–
–
tAH
–
tCKS
tCKH
tCS
–
CKE Hold Time (2)
–
Command Setup Time (CS,
RAS, CAS, WE, DQM)(2)
Command Hold Time (CS,
RAS, CAS, WE, DQM)(2)
Command Period (REF to REF
/ ACT to ACT)
–
tCH
1.0
72
48
19
20
16
16
–
1.0
90
60
30
24
20
20
–
–
ns
ns
ns
ns
ns
ns
ns
tRC
–
tRAS
tRP
Command Period (ACT to
PRE)
100K
100K
Command Period (PRE to
ACT)
–
–
–
–
–
–
–
–
tRCD
tRRD
tDPL
tDAL
Active Command to Read/
Write Command Delay Time
Command Period (ACT [0] to
ACT [1])
Input Data to Precharge
Command Delay Time
Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
40
–
50
–
ns
tMRD
tDDE
tXSR
Mode Register Program Time
Power Down Exit Setup Time
Exit Self-Refresh to Active
Time
15
8
–
–
–
20
10
–
–
–
ns
ns
ns
80
100
tT
Transition Time
0.3
–
1.2
–
0.3
–
1.2
64
64
ns
ms
ms
8K times (x8/x16)
Refresh Cycle Time
tREF
4K times (x32)
–
64
–
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
Vih(min.) and Vil (max).
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
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08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-8
8
-10 UNITS
—
Clock Cycle Time
Operating Frequency
CAS Latency
10
100
3
ns
—
125
3
MHz
cycle
cycle
tc a c
tr c d
Active Command To Read/Write
Command Delay Time
3
3
tr a c
tr c
RAS Latency (tr c d + tc a c )
CAS Latency = 3
6
9
6
9
cycle
cycle
Command Period (REF to REF / ACT to
ACT)
tr a s
tr p
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
6
3
2
1
6
3
2
1
cycle
cycle
cycle
cycle
tr r d
tc c d
Column Command Delay Time
(READ, READA, WRIT, WRITA)
td p l
Input Data To Precharge Command Delay
Time
2
5
2
5
cycle
cycle
td a l
Input Data To Active/Refresh Command
Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z
Delay Time
(Write)
tr b d
CAS Latency = 3
CAS Latency = 3
CAS Latency = 3
3
0
3
0
cycle
cycle
tw b d
Burst Stop Command To Input in Invalid
Delay Time
(Write)
Precharge Command To Output in HIGH-Z
Delay Time
(Read)
tr q l
3
0
3
0
cycle
cycle
tw d l
Precharge Command To Input in Invalid
Delay Time
(Write)
Last Output To Auto-Precharge Start
Time (Read)
tp q l
-2
-2
cycle
tq m d
td m d
tm r d
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
2
0
2
2
0
2
cycle
cycle
cycle
Mode Register Set To Command Delay
Time
18
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Ordering Information – VD D = 1.8V
Commercial Range: (0°C to +70°C)
Configuration
16Mx16
Frequency (MHz) Speed (ns) Order Part No.
Package
125
100
8
IS42VM16160D-8BL
IS42VM32800D-10BL
54-Ball BGA, Lead-free
90-Ball BGA, Lead-free
8Mx32
10
Industrial Range: (–40ºC to 85ºC)
Configuration
32Mx8
Frequency (MHz) Speed (ns) Order Part No.
Package
125
125
8
8
IS42VM83200D-8TLI
IS42VM16160D-8TLI
IS42VM16160D-8BLI
IS42VM32800D-10TLI
IS42VM32800D-10BLI
54-pin TSOP II, Lead-free
54-pin TSOP II, Lead-free
54-Ball BGA, Lead-free
86-pin TSOP II, Lead-free
90-Ball BGA, Lead-free
16Mx16
8Mx32
100
10
Note: Contact ISSI for leaded parts support.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
19
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
20
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Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00D
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IS42VM83200D / IS42VM16160D / IS42VM32800D
22
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Rev. 00D
08/06/2010
IS42VM83200D / IS42VM16160D / IS42VM32800D
1 D
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Rev. 00D
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相关型号：
IS42VM83200D-8TLI
Synchronous DRAM, 32MX8, 6ns, CMOS, PBGA54, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-54
ISSI
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