IS42VS16100E [ISSI]
2048 refresh cycles every 32 ms;
| 型号： | IS42VS16100E |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 2048 refresh cycles every 32 ms |
| 文件： | 总81页 (文件大小：1180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42VS16100E
ꢀ
512KꢀWordsꢀxꢀ16ꢀBitsꢀxꢀ2ꢀBanksꢀ
PRELIMINARYꢀINFORMATION
FEBRUARYꢀ2011
16MbꢀSYNCHRONOUSꢀDYNAMICꢀRAMꢀ
DESCRIPTION
FEATURES
•ꢀ Clockꢀfrequency:ꢀ133,ꢀ100,ꢀ83ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positiveꢀclockꢀedge
•ꢀ Twoꢀbanksꢀcanꢀbeꢀoperatedꢀsimultaneouslyꢀandꢀ
independently
ISSI’sꢀ16MbꢀSynchronousꢀDRAMꢀIS42VS16100Eꢀisꢀ
organizedꢀasꢀaꢀ524,288-wordꢀxꢀ16-bitꢀxꢀ2-bankꢀforꢀ
improvedꢀperformance.ꢀTheꢀsynchronousꢀDRAMsꢀ
achieveꢀhigh-speedꢀdataꢀtransferꢀusingꢀpipelineꢀ
architecture.ꢀAllꢀinputsꢀandꢀoutputsꢀsignalsꢀreferꢀtoꢀtheꢀ
risingꢀedgeꢀofꢀtheꢀclockꢀinput.
•ꢀ DualꢀinternalꢀbankꢀcontrolledꢀbyꢀA11ꢀꢀ
(bankꢀselect)
•ꢀ Singleꢀ1.8Vꢀpowerꢀsupply
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ
Sequential/Interleave
•ꢀ 2048ꢀrefreshꢀcyclesꢀeveryꢀ32ꢀms
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ
operationsꢀcapability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀꢀ
prechargeꢀcommand
PIN CONFIGURATIONS
50-PinꢀTSOPꢀ(TypeꢀII)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CAS
RAS
CS
A11
A10
A0
A1
•ꢀ ByteꢀcontrolledꢀbyꢀLDQMꢀandꢀUDQM
•ꢀ Packageꢀ400-milꢀ50-pinꢀTSOPꢀIIꢀandꢀ60-ballꢀ
BGA
A7
A6
A5
A4
A2
A3
VDD
VSS
•ꢀ Lead-freeꢀpackageꢀoption
•ꢀ Autoꢀrefreshꢀandꢀself-refreshꢀmodes
•ꢀ Powerꢀdownꢀandꢀdeepꢀpowerꢀdown
RASꢀ
CAS ꢀ
WEꢀ
ꢀ
ꢀ
ꢀ
ꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
PINꢀDESCRIPTIONS
A0-A11ꢀ ꢀ
AddressꢀInput
A0-A10ꢀ ꢀ
RowꢀAddressꢀInput
BankꢀSelectꢀAddress
ColumnꢀAddressꢀInput
DataꢀDQ
LDQMꢀ
LowerꢀBye,ꢀInput/OutputꢀMask
UpperꢀBye,ꢀInput/OutputꢀMask
Power
A11ꢀꢀ
ꢀ
ꢀ
UDQMꢀ ꢀ
A0-A7ꢀ
VDDꢀ
VSSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
VDDQꢀ
VSSQꢀ
NCꢀ
PowerꢀSupplyꢀforꢀDQꢀPin
GroundꢀforꢀDQꢀPin
ChipꢀSelect
NoꢀConnection
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
1
Rev.ꢀ00E
01/21/2011
IS42VS16100Eꢀ
PIN CONFIGURATION
package code: B 60 BaLL fBga (Tꢀꢁ Viꢂw) (10.1 mm x 6.4 mm Bꢀꢃy, 0.65 mm Bꢄll pitꢅh)
1 2 3 4 5 6 7
A
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8 NC
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ DQ6
B
C
D
E
F
G
H
J
NC
DQ7
NC
NC
NC UDQM
NC CLK
CKE NC
NC
VDD
LDQM WE
K
L
CAS
CS
RAS
NC
NC
A0
M
N
P
R
A11
A8
A9
A7
A5
A4
NC
A10
A1
A6
A2
VSS
VDD
A3
PIN DESCRIPTIONS
a0-a10
a0-a7
a11
Rꢀw aꢃꢃrꢂss Inꢁut
cꢀlumn aꢃꢃrꢂss Inꢁut
Bꢄnꢆ Sꢂlꢂꢅt aꢃꢃrꢂss
dꢄtꢄ I/o
WE
Writꢂ enꢄblꢂ
LdQM, UdQM
x16 Inꢁut/outꢁut Mꢄsꢆ
pꢀwꢂr
Vdd
Vss
dQ0 tꢀ dQ15
cLk
grꢀunꢃ
Systꢂm clꢀꢅꢆ Inꢁut
clꢀꢅꢆ enꢄblꢂ
Vddq
Vssq
Nc
pꢀwꢂr Suꢁꢁly ꢇꢀr I/o pin
grꢀunꢃ ꢇꢀr I/o pin
Nꢀ cꢀnnꢂꢅtiꢀn
cke
CS
chiꢁ Sꢂlꢂꢅt
RAS
Rꢀw aꢃꢃrꢂss Strꢀbꢂ cꢀmmꢄnꢃ
CAS
cꢀlumn aꢃꢃrꢂss Strꢀbꢂ cꢀmmꢄnꢃ
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
PINꢀFUNCTIONS
ꢀ
PinꢀNo.ꢀ
Symbolꢀ
Typeꢀ
Functionꢀ(InꢀDetail)
ꢀ
ꢀ
20ꢀtoꢀ24ꢀ
27ꢀtoꢀ32ꢀ
A0-A10ꢀ
ꢀ
InputꢀPinꢀ
ꢀ
A0ꢀtoꢀA10ꢀareꢀaddressꢀinputs.ꢀA0-A10ꢀareꢀusedꢀasꢀrowꢀaddressꢀinputsꢀduringꢀactive
commandꢀinputꢀandꢀA0-A7ꢀasꢀcolumnꢀaddressꢀinputsꢀduringꢀreadꢀorꢀwriteꢀcommandꢀinput.ꢀ
A10ꢀisꢀalsoꢀusedꢀtoꢀdetermineꢀtheꢀprechargeꢀmodeꢀduringꢀotherꢀcommands.ꢀIfꢀA10ꢀisꢀ
LOWꢀduringꢀprechargeꢀcommand,ꢀtheꢀbankꢀselectedꢀbyꢀA11ꢀisꢀprecharged,ꢀbutꢀifꢀA10ꢀisꢀ
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprecharged.ꢀ
WhenꢀA10ꢀisꢀHIGHꢀinꢀreadꢀorꢀwriteꢀcommandꢀcycle,ꢀtheꢀprechargeꢀstartsꢀautomaticallyꢀ
afterꢀtheꢀburstꢀaccess.ꢀ
TheseꢀsignalsꢀbecomeꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀcommandꢀinput.
ꢀ
19ꢀ
A11ꢀ
InputꢀPinꢀ
A11ꢀisꢀtheꢀbankꢀselectionꢀsignal.ꢀWhenꢀA11ꢀisꢀLOW,ꢀbankꢀ0ꢀisꢀselectedꢀandꢀwhenꢀhigh,ꢀ
bankꢀ1ꢀisꢀselected.ꢀThisꢀsignalꢀbecomesꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀ
commandꢀinput.
ꢀ
ꢀ
16ꢀ
34ꢀ
CASꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CAS,ꢀinꢀconjunctionꢀwithꢀtheꢀRASꢀandꢀꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ
“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
CKEꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀWhenꢀisꢀ
CKEꢀHIGH,ꢀtheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalid,ꢀandꢀwhenꢀLOW,ꢀinvalid.ꢀ
WhenꢀCKEꢀisꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀtheꢀpower-downꢀmode,ꢀtheꢀclockꢀsuspendꢀ
mode,ꢀorꢀtheꢀselfꢀrefreshꢀmode.ꢀTheꢀCKEꢀisꢀanꢀasynchronousꢀinput.
ꢀ
ꢀ
35ꢀ
18ꢀ
CLKꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀ
acquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.
CSꢀ
TheꢀCSꢀinputꢀdeterminesꢀwhetherꢀcommandꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀꢀ
ꢀ
CommandꢀinputꢀisꢀenabledꢀwhenꢀCSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀdeviceꢀ
remainsꢀinꢀtheꢀpreviousꢀstateꢀwhenꢀCSꢀisꢀHIGH.
ꢀ
2,ꢀ3,ꢀ5,ꢀ6,ꢀ8,ꢀ9,ꢀ11ꢀ DQ0ꢀtoꢀ
DQꢀPinꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀDQꢀpins.ꢀDQꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
ꢀ 12,ꢀ39,ꢀ40,ꢀ42,ꢀ43,ꢀ
DQ15ꢀ
ꢀ
45,ꢀ46,ꢀ48,ꢀ49
ꢀ
ꢀ
14,ꢀ36ꢀ
ꢀ
LDQM,ꢀ
UDQMꢀ
InputꢀPinꢀ
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀDQꢀbuffers.ꢀInꢀread
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀꢀ
toꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀOEꢀ
inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀ
LDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀcanꢀbeꢀ
writtenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀandꢀcannotꢀbeꢀ
writtenꢀtoꢀtheꢀdevice.
ꢀ
ꢀ
17ꢀ
15ꢀ
RASꢀ
ꢀWEꢀ
InputꢀPinꢀ
InputꢀPinꢀ
RAS,ꢀinꢀconjunctionꢀwithꢀCASꢀandꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ“Commandꢀ
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀWE,ꢀinꢀconjunctionꢀwithꢀRASꢀandꢀCAS,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ“Commandꢀ
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7,ꢀ13,ꢀ38,ꢀ44ꢀ
1,ꢀ25ꢀ
VDDQꢀ
VDDꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
VDDQꢀisꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
VDDꢀisꢀtheꢀdeviceꢀinternalꢀpowerꢀsupply.
VSSQꢀisꢀtheꢀoutputꢀbufferꢀground.
VSSꢀisꢀtheꢀdeviceꢀinternalꢀground.
4,ꢀ10,ꢀ41,ꢀ47ꢀ
26,ꢀ50ꢀ
VSSQꢀ
VSSꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
3
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
MEMORY CELL
ARRAY
ROW
ADDRESS
BUFFER
2048
CLOCK
MODE
REGISTER
BANK 0
11
GENERATOR
11
A11
LDQM,
UDQM
DATA IN
BUFFER
11
SENSE AMP I/O GATE
256
16
16
A10
8
SELF
DQ 0-15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
COLUMN DECODER
REFRESH
8
CONTROLLER
256
DATA OUT
BUFFER
SENSE AMP I/O GATE
REFRESH
COUNTER
16
16
MEMORY CELL
ARRAY
VDD/VDDQ
VSS/VSSQ
2048
ROW
ADDRESS
BUFFER
BANK 1
ROW
ADDRESS
LATCH
11
11
11
S16BLK.eps
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
(1)
ABSOLUTEꢀMAXIMUMꢀRATINGS
ꢀ Symbolꢀ
ꢀ VDD maxꢀ
ꢀ VDDqꢀꢀmax
ꢀ Vinꢀ
Parametersꢀ
ꢀ
Ratingꢀ
–0.5ꢀtoꢀ+2.6ꢀ
–0.5ꢀtoꢀ+2.6ꢀ
–0.5ꢀtoꢀ+2.6ꢀ
1ꢀ
Unitꢀ
V
MaximumꢀSupplyꢀVoltageꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
V
InputꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
V
ꢀ PD max
ꢀ Ics
AllowableꢀPowerꢀDissipationꢀ
OutputꢀShortedꢀCurrentꢀ
W
50ꢀ
mA
ꢀ TOpr
ꢀ ꢀ
OperatingꢀTemperatureꢀ
ꢀ
Comꢀ
Ind.ꢀ
0ꢀtoꢀ+70ꢀ
-40ꢀtoꢀ+85ꢀ
°Cꢀ
°C
ꢀ
ꢀ
ꢀ Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–55ꢀtoꢀ+150ꢀ
°C
(2)
DCꢀRECOMMENDEDꢀOPERATINGꢀCONDITIONS ꢀꢀ
Commercialꢀ(Taꢀ=ꢀ0°Cꢀtoꢀ+70°C),ꢀIndustrialꢀ(Taꢀ=ꢀ-40°Cꢀtoꢀ+85°C)
ꢀ Symbolꢀ
Parameterꢀ
Min.ꢀ
1.7ꢀ
0.8ꢀxꢀVDDqꢀ
-0.3ꢀ
Typ.ꢀ
1.8ꢀ
—ꢀ
Max.ꢀ
Unit
V
V
ꢀ VDD, VDDqꢀ SupplyꢀVoltageꢀ
1.9ꢀ
VDDq +ꢀ0.3ꢀ
+0.3ꢀ
ꢀ Vihꢀ
ꢀ Vilꢀ
InputꢀHighꢀVoltage(3)ꢀ
InputꢀLowꢀVoltage(4)ꢀ
—ꢀ
V
(1,2)
CAPACITANCEꢀCHARACTERISTICS ꢀ(VDDꢀ=ꢀ1.8V,ꢀTaꢀ=ꢀ+25°C,ꢀfꢀ=ꢀ1ꢀMHz)
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ
Cin1ꢀ
Parameterꢀ
Min.ꢀ
2.5ꢀ
Max.ꢀ
4.0ꢀ
Unit
pF
InputꢀCapacitance:ꢀCLKꢀ
Cin2ꢀ
InputꢀCapacitance:ꢀ(A0-A11,ꢀCKE, CS, RAS,ꢀCAS,ꢀWE,ꢀLDQM,ꢀUDQM)ꢀ 2.5ꢀ
DataꢀInput/OutputꢀCapacitance:ꢀDQ0-DQ15ꢀ 4.0ꢀ
5.0ꢀ
pF
CI/Oꢀ
6.5ꢀ
pF
Notes:
1.ꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀ
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreli-
ability.
2.ꢀAllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
3.ꢀVihꢀ(max)ꢀ=ꢀ2.2Vꢀwithꢀaꢀpulseꢀwidthꢀ≤ꢀ3ꢀns.
4.ꢀVilꢀ(min)ꢀ=ꢀ-1.0Vꢀwithꢀaꢀpulseꢀwidthꢀ≤ꢀ3ꢀns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
5
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
DCꢀELECTRICALꢀCHARACTERISTICSꢀ(RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)ꢀ
Continuedꢀonꢀnextꢀpage.
ꢀSymbolꢀ Parameterꢀ
TestꢀConditionꢀ
ꢀ
ꢀ
Min.ꢀ
Max.ꢀ
Unit
ꢀiilꢀ
ꢀꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀ≤ꢀVinꢀ≤ꢀVDD,ꢀwithꢀpinsꢀotherꢀthanꢀ
theꢀtestedꢀpinꢀatꢀ0V
ꢀ
–1.0ꢀ
1.0ꢀ
µA
ꢀiOlꢀ
OutputꢀLeakageꢀCurrentꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀ≤ꢀVOutꢀ≤ꢀVDDꢀ
ꢀ
ꢀ
ꢀ
–1.5ꢀ
0.9ꢀxꢀVDDqꢀ
—ꢀ
1.5ꢀ
—ꢀ
0.2ꢀ
µAꢀ
Vꢀ
V
ꢀVOhꢀ
ꢀVOlꢀ
OutputꢀHighꢀVoltageꢀLevel(1)ꢀ iOhꢀ=ꢀ–0.1ꢀmAꢀ
ꢀ
ꢀ
OutputꢀLowꢀVoltageꢀLevel(1)ꢀ
iOlꢀ=ꢀ0.1ꢀmAꢀ
DCꢀELECTRICALꢀCHARACTERISTICS(4)ꢀ(RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
ꢀSymbolꢀ Parameterꢀ TestꢀConditionꢀ ꢀ Speedꢀ Min.ꢀ Max.ꢀ Unit
OneꢀBankꢀOperation,ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ
ꢀicc1ꢀ
ꢀꢀ
OperatingꢀCurrent(1,2)
ꢀ
ꢀ
ꢀ
ꢀ
-7.5ꢀ
-10ꢀ
—ꢀ
—ꢀ
45ꢀ
35ꢀ
mA
mA
BurstꢀLength=1ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
trcꢀ≥ꢀtrcꢀ(min.)ꢀ
IOutꢀ=ꢀ0mAꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
-7.5ꢀ
-10ꢀ
—ꢀ
—ꢀ
50ꢀ
40
mA
ꢀicc2pꢀ
ꢀꢀ
PrechargeꢀStandbyꢀCurrentꢀCKEꢀ≤ꢀVilꢀꢀ(max)ꢀ
(InꢀPower-DownꢀMode)
tckꢀ=ꢀ10ꢀnsꢀ
tck = ∞ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
0.3ꢀ
0.3ꢀ
6ꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
ꢀIcc2ps
ꢀꢀ
PrechargeꢀStandbyꢀCurrentCKEꢀ≤ꢀVilꢀꢀ(max)
ꢀ
(InꢀPower-DownꢀMode)ꢀ
CLKꢀ≤ꢀVilꢀꢀ(max)
icc2nꢀ
ꢀꢀ
ActiveꢀStandbyꢀCurrent(3)ꢀ CKEꢀ≥ꢀVihꢀ(min)ꢀ
tckꢀ=ꢀ10ꢀnsꢀ
CSꢀ≥ꢀVihꢀ(min),ꢀ
tck = ∞ꢀ
Inputsꢀareꢀstableꢀ
ꢀ
ꢀ
ꢀ
ꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
ꢀIcc2ns
ꢀꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
CKEꢀ≥ꢀVihꢀ(min)ꢀ
CKEꢀ≤ꢀVilꢀꢀ(max)ꢀ
CKEꢀ≤ꢀVilꢀꢀ(max)ꢀ
—ꢀ
ꢀ
2ꢀ
icc3Pꢀ
ꢀꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
tckꢀ=ꢀ10ꢀnsꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
ꢀ
6ꢀ
ꢀIcc3Ps
ꢀꢀ
ActiveꢀStandbyꢀCurrent
tck = ∞ꢀ
CLKꢀ≤ꢀVilꢀꢀ(max)ꢀ
ꢀ
ꢀ
—ꢀ
ꢀ
5ꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
ActiveꢀStandbyꢀCurrent(3)ꢀ CKEꢀ≥ꢀVihꢀ(min)ꢀ
icc3nꢀ
tckꢀ=ꢀ10ꢀnsꢀ
ꢀ
—ꢀ
12ꢀ
ꢀꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
CSꢀ≥ꢀVihꢀ(min)
ꢀIcc3ns
ꢀꢀ
ꢀꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀNonꢀPower-DownꢀMode)ꢀ
ꢀ
CKEꢀ≥ꢀVihꢀ(min)ꢀ
tck = ∞ꢀ
CLKꢀ≤ꢀVilꢀ(max)ꢀ
Inputsꢀareꢀstable
ꢀ
ꢀ
—ꢀ
ꢀ
—ꢀ
ꢀ
10ꢀ
ꢀ
mAꢀ
ꢀ
ꢀ
ꢀicc4ꢀ
ꢀꢀ
OperatingꢀCurrentꢀ
(InꢀBurstꢀMode)(1,3)ꢀ
tckꢀ=ꢀtckꢀ(min)ꢀ
IOut =ꢀ0mAꢀ
CASꢀlatencyꢀ=ꢀ2,ꢀ3ꢀ
ꢀ
ꢀ
ꢀ
-7.5ꢀ
-10ꢀ
—ꢀ
—ꢀ
60ꢀ
50ꢀ
mA
mA
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
PageꢀBurstꢀ
BothꢀBanksꢀactivatedꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀicc5ꢀ
Auto-RefreshꢀCurrentꢀ
trcꢀ=ꢀtrc (min)ꢀ
CASꢀlatencyꢀ=ꢀ2,ꢀ3
ꢀ
ꢀ
-7.5ꢀ
-10ꢀ
—ꢀ
—ꢀ
40ꢀ
40ꢀ
mA
mA
ꢀicc6ꢀ
icc7ꢀ
Self-RefreshꢀCurrentꢀ
DeepꢀPowerꢀDownꢀCurrentꢀ CKEꢀ≤ꢀ0.2Vꢀ
CKEꢀ≤ꢀ0.2Vꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
180ꢀ
10ꢀ
µA
µA
Notes:
1.ꢀTheseꢀareꢀtheꢀvaluesꢀatꢀtheꢀminimumꢀcycleꢀtime.ꢀSinceꢀtheꢀcurrentsꢀareꢀtransient,ꢀtheseꢀvaluesꢀdecreaseꢀasꢀtheꢀcycleꢀtimeꢀin-
creases.ꢀAlsoꢀnoteꢀthatꢀaꢀbypassꢀcapacitorꢀofꢀꢀatꢀꢀleastꢀꢀ0.01ꢀµFꢀshouldꢀbeꢀinsertedꢀbetweenꢀVDD andꢀVssꢀforꢀeachꢀmemoryꢀchipꢀ
toꢀsuppressꢀpowerꢀsupplyꢀvoltageꢀnoiseꢀ(voltageꢀdrops)ꢀdueꢀtoꢀtheseꢀtransientꢀcurrents.
2.ꢀIcc1ꢀandꢀIcc4ꢀdependꢀonꢀtheꢀoutputꢀload.ꢀTheꢀmaximumꢀvaluesꢀforꢀIcc1ꢀandꢀIcc4ꢀareꢀobtainedꢀwithꢀtheꢀoutputꢀopenꢀstate.
3.ꢀꢀInputsꢀchangedꢀonceꢀeveryꢀtwoꢀclocks.
4.ꢀꢀNotꢀallꢀparametersꢀareꢀtestedꢀatꢀtheꢀwaferꢀlevel,ꢀbutꢀtheꢀparametersꢀhaveꢀbeenꢀpreviouslyꢀcharacterized.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
100,000ꢀ
IS42VS16100Eꢀ
(1,2,3,6)
ACꢀCHARACTERISTICS
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-7.5ꢀ ꢀ
ꢀ
-10ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ Parameterꢀ
Min.ꢀ ꢀ Max.
ꢀ
Min.ꢀ ꢀ Max.ꢀ
ꢀ Units
ꢀ tck3ꢀ
ꢀ tck2ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
7.5ꢀ ꢀ —ꢀ
10ꢀ ꢀ —ꢀ
10ꢀ
12ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tac3ꢀ
ꢀ tac2ꢀ
AccessꢀTimeꢀFromꢀCLK(4)ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
6ꢀ
8ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tchiꢀ
ꢀ tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
ꢀ
ꢀ
2.5ꢀ ꢀ —ꢀ
2.5ꢀ ꢀ —ꢀ
3ꢀ
3ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tOh3ꢀ
ꢀ tOh2ꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ꢀ
ns
ꢀ thz3ꢀ
ꢀ thz2ꢀ
OutputꢀHIGHꢀImpedanceꢀTime(5)
ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
6ꢀ
8ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
7ꢀ
8ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tDsꢀ
ꢀ tDhꢀ
ꢀ tasꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
CKEꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2ꢀ
ꢀ tahꢀ
ꢀ tcksꢀ
ꢀ tckhꢀ
ꢀ tckaꢀ
ꢀ tcsꢀ
ꢀ tchꢀ
ꢀ trcꢀ
ꢀ trasꢀ
ꢀ trpꢀ
ꢀ trcDꢀ
ꢀ trrDꢀ
1ꢀ
2.5ꢀ
1ꢀ
CKEꢀHoldꢀTimeꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3ꢀ —ꢀ
1CLK+3ꢀ —ꢀ
CommandꢀSetupꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ
CommandꢀHoldꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
75ꢀ ꢀ —ꢀ
45ꢀ 100,000ꢀ
100ꢀ
60ꢀ
30ꢀ
30ꢀ
20ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
22.5ꢀ ꢀ —ꢀ
22.5ꢀ ꢀ —ꢀ
15ꢀ ꢀ —ꢀ
2CLKꢀꢀ —ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀꢀ
ꢀ tDpl3ꢀ
ꢀ ꢀ ꢀ
ꢀ tDpl2ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ ꢀ —ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tDal3ꢀ
ꢀ ꢀ ꢀ
ꢀ tDal2ꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)ꢀ
ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ꢀ tt
TransitionꢀTimeꢀ
ꢀ
ꢀ
0.5ꢀ ꢀ 5ꢀ
0.5ꢀ
—ꢀ
ꢀ
ꢀ
5ꢀ
ꢀ trefꢀ
Notes:
RefreshꢀCycleꢀTimeꢀ(2048)ꢀ
—ꢀ
ꢀ
32ꢀ
32ꢀ
ms
1.ꢀTheꢀꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2.ꢀmeasuredꢀwithꢀtt =ꢀ0.5ꢀns.
3.ꢀTheꢀreferenceꢀlevelꢀisꢀ0.9Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil (max.).
4.ꢀAccessꢀtimeꢀisꢀmeasuredꢀatꢀ0.9Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.
5.ꢀTheꢀtimeꢀthz (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀbecomeꢀhighꢀimpedance.
6.ꢀNotꢀallꢀparametersꢀareꢀtestedꢀatꢀtheꢀwaferꢀlevel,ꢀbutꢀtheꢀparametersꢀhaveꢀbeenꢀpreviouslyꢀcharacterized.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
7
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
OPERATINGꢀFREQUENCYꢀ/ꢀLATENCYꢀRELATIONSHIPS
ꢀ SYMBOLꢀ PARAMETERꢀ
ꢀ
ꢀ
ꢀ
-7.5ꢀ -7.5/-10ꢀ
-10ꢀ
12ꢀ
UNITS
ns
ꢀ
—ꢀ
—ꢀ
ClockꢀCycleꢀTimeꢀ
7.5ꢀ
10ꢀ
ꢀ
OperatingꢀFrequencyꢀ
133ꢀ
100ꢀ
83ꢀ
MHz
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tcacꢀ
trcDꢀ
tracꢀ
trc
CASꢀꢀLatencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
3ꢀ
2/3ꢀ
3ꢀ
2ꢀ
2ꢀ
4ꢀ
8ꢀ
5ꢀ
2ꢀ
2ꢀ
1ꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(trcDꢀ+ꢀtcac)ꢀ
6ꢀ
6ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
10ꢀ
6ꢀ
10ꢀ
6ꢀ
trasꢀ
trpꢀ
3ꢀ
3ꢀ
trrDꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
tccDꢀ
ꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
1ꢀ
ꢀ
tDplꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
2ꢀ
4ꢀ
cycle
cycle
ꢀ
ꢀ
tDalꢀ
ꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)
ꢀ
ꢀ
trbDꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
—ꢀ
3ꢀ
2ꢀ
—ꢀ
2
cycle
cycle
cycle
cycle
cycleꢀ
ꢀ
ꢀ
twbDꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
trqlꢀ
ꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
—ꢀ
3ꢀ
2ꢀ
—ꢀ
2
ꢀ
ꢀ
twDlꢀ
ꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)
ꢀ
0ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
tpqlꢀ
ꢀ
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)ꢀ
ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
-2ꢀ
—ꢀ
–2ꢀ
-1ꢀ
—ꢀ
-1
ꢀ
ꢀ
ꢀ
tqmDꢀ
tDmDꢀ
tmrDꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
cycle
cycle
cycle
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
ACꢀTESTꢀCONDITIONSꢀ(Input/OutputꢀReferenceꢀLevel:ꢀ0.9V)
OutputꢀLoad
Input
t
CK
t
CL
t
CHI
1.8V
0.9V
50 Ω
CLK
0.0V
0.5 x VDDQ V
I/O
t
CS
t
CH
1.8V
0.9V
0.0V
INPUT
30 pF
t
AC
t
OH
0.9V
0.9V
OUTPUT
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
COMMANDSꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀActiveꢀCommandꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀReadꢀCommand
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
ROW
A0-A9
A0-A9
AUTO PRECHARGE
ROW
A10
A11
A10
A11
NO PRECHARGE
BANK 1
BANK 1
BANK 0
BANK 0
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀWriteꢀCommandꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀPrechargeꢀCommand
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
A0-A9
A0-A9
AUTO PRECHARGE
BANK 0 AND BANK 1
A10
A11
A10
A11
NO PRECHARGE
BANK 1
BANK 0 OR BANK 1
BANK 1
BANK 0
BANK 0
Don't Care
Notes:ꢀ
1.ꢀꢀA8-A9ꢀ=ꢀDon’tꢀCare.
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9
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
COMMANDSꢀ(cont.)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀNo-OperationꢀCommandꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀDeviceꢀDeselectꢀCommand
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
A0-A9
A10
A11
A10
A11
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀModeꢀRegisterꢀSetꢀCommandꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀAuto-RefreshꢀCommand
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
OP-CODE
OP-CODE
OP-CODE
A0-A9
A10
A11
A10
A11
Don't Care
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
COMMANDSꢀ(cont.)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀSelf-RefreshꢀCommandꢀ ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀPowerꢀDownꢀCommand
CLK
CLK
ALL BANKS IDLE
CKE
CKE
CS
CS
NOP
RAS
RAS
NOP
CAS
WE
CAS
NOP
WE
A0-A9
A0-A9
A10
A11
A10
A11
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀClockꢀSuspendꢀCommandꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBurstꢀStopꢀCommand
CLK
CLK
BANK(S) ACTIVE
CKE
HIGH
CKE
NOP
CS
CS
NOP
RAS
RAS
NOP
CAS
CAS
WE
NOP
WE
A0-A9
A0-A9
A10
A11
A10
A11
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
11
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ModeꢀRegisterꢀSetꢀCommand
(CS,ꢀRAS,ꢀCAS,ꢀWEꢀ=ꢀLOW)
WhenꢀtheꢀA10ꢀpinꢀisꢀHIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀaꢀ
readꢀwithꢀauto-prechargeꢀcommand.ꢀAfterꢀtheꢀburstꢀreadꢀ
completes,ꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀisꢀprecharged.ꢀ
WhenꢀtheꢀA10ꢀpinꢀisꢀLOW,ꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀ
pinꢀ remainsꢀ inꢀ theꢀ activatedꢀ stateꢀ afterꢀ theꢀ burstꢀ readꢀ
completes.
Theꢀ IS42VS16100Eꢀ productꢀ incorporatesꢀ aꢀ registerꢀ
thatꢀdefinesꢀtheꢀdeviceꢀoperatingꢀmode.ꢀThisꢀcommandꢀ
functionsꢀasꢀaꢀdataꢀinputꢀpinꢀthatꢀloadsꢀthisꢀregisterꢀfromꢀ
theꢀ pinsꢀ A0ꢀ toꢀ A11.ꢀWhenꢀ ꢀ powerꢀ isꢀ firstꢀ applied,ꢀ theꢀ
stipulatedꢀpower-onꢀsequenceꢀshouldꢀbeꢀexecutedꢀandꢀ
thenꢀtheꢀIS42VS16100Eꢀshouldꢀbeꢀinitializedꢀbyꢀexecutingꢀ
aꢀmodeꢀregisterꢀsetꢀcommand.
Noteꢀ thatꢀ theꢀ modeꢀ registerꢀ setꢀ commandꢀ canꢀ beꢀ
executedꢀonlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀstateꢀ(i.e.ꢀ
deactivated).
WriteꢀCommand
(CS,ꢀCAS,ꢀWEꢀ=ꢀLOW,ꢀꢀRASꢀ=ꢀHIGH)
Whenꢀburstꢀwriteꢀmodeꢀhasꢀbeenꢀselectedꢀwithꢀtheꢀmodeꢀ
registerꢀsetꢀcommand,ꢀthisꢀcommandꢀselectsꢀtheꢀbankꢀ
specifiedꢀbyꢀtheꢀA11ꢀpinꢀandꢀstartsꢀaꢀburstꢀwriteꢀoperationꢀ
atꢀtheꢀstartꢀaddressꢀspecifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀThisꢀfirstꢀ
dataꢀmustꢀbeꢀinputꢀtoꢀtheꢀDQꢀpinsꢀinꢀtheꢀcycleꢀinꢀwhichꢀ
thisꢀcommand.
Anotherꢀ commandꢀ cannotꢀ beꢀ executedꢀ afterꢀ aꢀ modeꢀ
registerꢀsetꢀcommandꢀuntilꢀafterꢀtheꢀpassageꢀofꢀtheꢀperiodꢀ
tmcD, whichꢀisꢀtheꢀperiodꢀrequiredꢀforꢀmodeꢀregisterꢀsetꢀ
commandꢀexecution.
Theꢀ selectedꢀ bankꢀ mustꢀ beꢀ activatedꢀ beforeꢀ executingꢀ
thisꢀcommand.
ActiveꢀCommandꢀ
(CS,ꢀRASꢀ=ꢀLOW,ꢀCAS,ꢀWE=ꢀHIGH)
Whenꢀ A10ꢀ pinꢀ isꢀ HIGH,ꢀ thisꢀ commandꢀ functionsꢀ asꢀ aꢀ
writeꢀwithꢀauto-prechargeꢀcommand.ꢀAfterꢀtheꢀburstꢀwriteꢀ
completes,ꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀisꢀprecharged.ꢀ
WhenꢀtheꢀA10ꢀpinꢀisꢀlow,ꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀ
pinꢀ remainsꢀ inꢀ theꢀ activatedꢀ stateꢀ afterꢀ theꢀ burstꢀ writeꢀ
completes.
TheꢀIS42VS16100Eꢀincludesꢀtwoꢀbanksꢀofꢀ2048ꢀrowsꢀeach.ꢀ
Thisꢀcommandꢀselectsꢀoneꢀofꢀtheꢀtwoꢀbanksꢀaccordingꢀ
toꢀtheꢀA11ꢀpinꢀandꢀactivatesꢀtheꢀrowꢀselectedꢀbyꢀtheꢀpinsꢀ
A0ꢀtoꢀA10.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀfallꢀofꢀtheꢀRASꢀsignalꢀ
fromꢀHIGHꢀtoꢀLOWꢀinꢀconventionalꢀDRAMs.
Afterꢀtheꢀinputꢀofꢀtheꢀlastꢀburstꢀwriteꢀdata,ꢀtheꢀapplicationꢀ
mustꢀwaitꢀforꢀtheꢀwriteꢀrecoveryꢀperiodꢀ(tDpl,ꢀtDal)ꢀtoꢀelapseꢀ
accordingꢀtoꢀCASꢀlatency.
PrechargeꢀCommandꢀ
(CS,ꢀRAS,ꢀWEꢀ=ꢀLOW,ꢀCASꢀ=ꢀHIGH)
Auto-RefreshꢀCommand
(CS,ꢀRAS,ꢀCASꢀ=ꢀLOW,ꢀWE,ꢀCKEꢀꢀ=ꢀHIGH)
Thisꢀcommandꢀstartsꢀprechargingꢀtheꢀbankꢀselectedꢀbyꢀ
pinsꢀA10ꢀandꢀA11.ꢀWhenꢀA10ꢀisꢀHIGH,ꢀbothꢀbanksꢀareꢀ
prechargedꢀatꢀtheꢀsameꢀtime.ꢀWhenꢀA10ꢀisꢀLOW,ꢀtheꢀ
bankꢀselectedꢀbyꢀA11ꢀisꢀprecharged.ꢀAfterꢀexecutingꢀthisꢀ
command,ꢀtheꢀnextꢀcommandꢀforꢀtheꢀselectedꢀbank(s)ꢀ
isꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtrp,ꢀwhichꢀisꢀtheꢀ
periodꢀrequiredꢀforꢀbankꢀprecharging.
Thisꢀcommandꢀexecutesꢀtheꢀauto-refreshꢀoperation.ꢀTheꢀ
rowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.
Bothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀidleꢀstateꢀbeforeꢀexecutingꢀ
thisꢀcommand.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀRASꢀsignalꢀfromꢀLOWꢀ
toꢀHIGHꢀinꢀconventionalꢀDRAMs
Theꢀstipulatedꢀperiodꢀ(trc)ꢀisꢀrequiredꢀforꢀaꢀsingleꢀrefreshꢀ
operation,ꢀandꢀnoꢀotherꢀcommandsꢀcanꢀbeꢀexecutedꢀduringꢀ
thisꢀperiod.
Theꢀdeviceꢀgoesꢀtoꢀtheꢀidleꢀstateꢀafterꢀtheꢀinternalꢀrefreshꢀ
operationꢀcompletes.
ReadꢀCommandꢀ
(CS,ꢀCASꢀ=ꢀLOW,ꢀRAS,ꢀWEꢀ=ꢀHIGH)
Thisꢀ commandꢀ mustꢀ beꢀ executedꢀ atꢀ leastꢀ 2048ꢀ timesꢀ
everyꢀ64ꢀms.
ThisꢀcommandꢀselectsꢀtheꢀbankꢀspecifiedꢀbyꢀtheꢀA11ꢀpinꢀ
andꢀstartsꢀaꢀburstꢀreadꢀoperationꢀatꢀtheꢀstartꢀaddressꢀ
specifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀDataꢀisꢀoutputꢀfollowingꢀCASꢀ
latency.
Thisꢀ commandꢀ correspondsꢀ toꢀ CBRꢀ auto-refreshꢀ inꢀ
conventionalꢀDRAMs.
Theꢀselectedꢀbankꢀmustꢀbeꢀactivatedꢀbeforeꢀexecutingꢀ
thisꢀcommand.
12ꢀ
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Rev.ꢀ 00E
01/21/2011
operations.Whenꢀthisꢀcommandꢀisꢀexecutedꢀduringꢀaꢀburstꢀ
readꢀoperation,ꢀdataꢀoutputꢀstopsꢀafterꢀtheꢀCASꢀlatencyꢀ
periodꢀhasꢀelapsed.
operationꢀrestarts.Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀ
untilꢀtheꢀrecoveryꢀperiodꢀ(tcka)ꢀhasꢀelapsed.
operation.
theꢀCKEꢀpinꢀfromꢀHIGHꢀtoꢀLOW.
Theꢀself-refreshꢀoperationꢀisꢀstartedꢀbyꢀdroppingꢀ
Theꢀself-refreshꢀoperationꢀ
IS42VS16100Eꢀ
Self-RefreshꢀCommand
Power-DownꢀCommand
(CS,ꢀRAS,ꢀCAS,ꢀCKEꢀ=ꢀLOW,ꢀWEꢀ=ꢀHIGH)
(CKEꢀ=ꢀLOW,ꢀCSꢀ=ꢀHIGH)
Thisꢀcommandꢀexecutesꢀtheꢀself-refreshꢀoperation.ꢀTheꢀ
rowꢀaddressꢀtoꢀbeꢀrefreshed,ꢀtheꢀbank,ꢀandꢀtheꢀrefreshꢀ
intervalꢀareꢀgeneratedꢀautomaticallyꢀinternallyꢀduringꢀthisꢀ
Whenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀ(inactive)ꢀstate,ꢀorꢀwhenꢀ
atꢀleastꢀoneꢀofꢀtheꢀbanksꢀisꢀnotꢀinꢀtheꢀidleꢀ(inactive)ꢀstate,ꢀ
thisꢀcommandꢀcanꢀbeꢀusedꢀtoꢀsuppressꢀdeviceꢀpowerꢀ
dissipationꢀbyꢀreducingꢀdeviceꢀinternalꢀoperationsꢀtoꢀtheꢀ
minimalꢀlevelꢀinꢀorderꢀtoꢀretainꢀdataꢀcontent.ꢀPower-downꢀ
modeꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀfromꢀHIGHꢀtoꢀ
LOW,ꢀwhileꢀsatisfyingꢀtheꢀotherꢀcommandꢀinputꢀconditionsꢀ
(seeꢀCKEꢀTruthꢀTable).ꢀPower-downꢀmodeꢀcontinuesꢀasꢀ
longꢀasꢀtheꢀCKEꢀpinꢀisꢀheldꢀlow.ꢀAllꢀpinsꢀotherꢀthanꢀtheꢀ
CKEꢀpinꢀareꢀinvalidꢀandꢀnoneꢀofꢀtheꢀotherꢀcommandsꢀcanꢀ
beꢀexecutedꢀinꢀthisꢀmode.ꢀTheꢀpower-downꢀoperationꢀisꢀ
terminatedꢀbyꢀraisingꢀtheꢀCKEꢀpinꢀfromꢀLOWꢀtoꢀHIGH.ꢀ
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀrecoveryꢀ
periodꢀ(tcka)ꢀhasꢀelapsed.
continuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀremainsꢀLOWꢀandꢀthereꢀ
isꢀ noꢀ needꢀ forꢀ externalꢀ controlꢀ ofꢀ anyꢀ otherꢀ pins.ꢀTheꢀ
self-refreshꢀoperationꢀisꢀterminatedꢀbyꢀraisingꢀtheꢀCKEꢀ
pinꢀfromꢀLOWꢀtoꢀHIGH.ꢀTheꢀnextꢀcommandꢀcannotꢀbeꢀ
executedꢀuntilꢀtheꢀdeviceꢀinternalꢀrecoveryꢀperiodꢀ(trc)
hasꢀelapsed.ꢀAfterꢀtheꢀself-refresh,ꢀsinceꢀitꢀisꢀimpossibleꢀ
toꢀdetermineꢀtheꢀaddressꢀofꢀtheꢀlastꢀrowꢀtoꢀbeꢀrefreshed,ꢀ
anꢀauto-refreshꢀshouldꢀimmediatelyꢀbeꢀperformedꢀforꢀallꢀ
addressesꢀ(2048ꢀcycles).
Bothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀidleꢀstateꢀbeforeꢀexecutingꢀ
thisꢀcommand.
Sinceꢀthisꢀcommandꢀdiffersꢀfromꢀtheꢀself-refreshꢀcommandꢀ
describedꢀ aboveꢀ inꢀ thatꢀ theꢀ refreshꢀ operationꢀ isꢀ notꢀ
performedꢀautomaticallyꢀinternally,ꢀtheꢀrefreshꢀoperationꢀ
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tref).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀpower-downꢀmodeꢀcanꢀbeꢀheldꢀ
isꢀjustꢀunderꢀtheꢀrefreshꢀcycleꢀtime.
BurstꢀStopꢀCommandꢀ
(CS,ꢀWE,ꢀ=ꢀLOW,ꢀRAS,ꢀCASꢀ=ꢀHIGH)
Theꢀcommandꢀforciblyꢀterminatesꢀburstꢀreadꢀandꢀwriteꢀ
ClockꢀSuspend
(CKEꢀ=ꢀLOW)
Thisꢀcommandꢀcanꢀbeꢀusedꢀtoꢀstopꢀtheꢀdeviceꢀinternalꢀclockꢀ
temporarilyꢀduringꢀaꢀreadꢀorꢀwriteꢀcycle.ꢀClockꢀsuspendꢀ
modeꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀfromꢀHIGHꢀtoꢀ
LOW.ꢀClockꢀsuspendꢀmodeꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀ
pinꢀisꢀheldꢀLOW.ꢀAllꢀinputꢀpinsꢀotherꢀthanꢀtheꢀCKEꢀpinꢀareꢀ
invalidꢀandꢀnoneꢀofꢀtheꢀotherꢀcommandsꢀcanꢀbeꢀexecutedꢀ
inꢀthisꢀmode.ꢀAlsoꢀnoteꢀthatꢀtheꢀdeviceꢀinternalꢀstateꢀisꢀ
maintained.ꢀClockꢀsuspendꢀmodeꢀisꢀterminatedꢀbyꢀraisingꢀ
theꢀCKEꢀpinꢀfromꢀLOWꢀtoꢀHIGH,ꢀatꢀwhichꢀpointꢀdeviceꢀ
NoꢀOperation
(CS,ꢀ=ꢀLOW,ꢀRAS,ꢀCAS,ꢀWEꢀ=ꢀHIGH)
Thisꢀcommandꢀhasꢀnoꢀeffectꢀonꢀtheꢀdevice.
DeviceꢀDeselectꢀCommandꢀꢀ
(CSꢀ=ꢀHIGH)
Thisꢀcommandꢀdoesꢀnotꢀselectꢀtheꢀdeviceꢀforꢀanꢀobjectꢀofꢀ
operation.ꢀInꢀotherꢀwords,ꢀitꢀperformsꢀnoꢀoperationꢀwithꢀ
respectꢀtoꢀtheꢀdevice.
Sinceꢀthisꢀcommandꢀdiffersꢀfromꢀtheꢀself-refreshꢀcommandꢀ
describedꢀ aboveꢀ inꢀ thatꢀ theꢀ refreshꢀ operationꢀ isꢀ notꢀ
performedꢀautomaticallyꢀinternally,ꢀtheꢀrefreshꢀoperationꢀ
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tref).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀclockꢀsuspendꢀmodeꢀcanꢀbeꢀheldꢀ
isꢀjustꢀunderꢀtheꢀrefreshꢀcycleꢀtime.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
13
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
(1,2)
COMMANDꢀTRUTHꢀTABLE
ꢀ ꢀ
ꢀ Symbolꢀ Commandꢀ
ꢀ (E)MRSꢀ (Extended)ꢀModeꢀRegisterꢀSet(3,4)ꢀ Hꢀ Xꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCKEꢀ
ꢀ
ꢀ
n-1ꢀ nꢀ CS RAS CAS WEꢀ DQMꢀ A11ꢀ A10ꢀ A9-A0ꢀꢀ I/On
Lꢀ
Hꢀ Hꢀ Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀꢀOPꢀCODEꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
ꢀ REFꢀ
ꢀ SREFꢀ
ꢀ PREꢀ
ꢀ PALLꢀ
ꢀ ACTꢀ
ꢀ WRITꢀ
ꢀ WRITAꢀ
ꢀ READꢀ
Auto-Refresh(5)ꢀ
Self-Refresh(5,6)ꢀ
Lꢀ Hꢀ
Lꢀ Hꢀ
Hꢀ Lꢀ
Hꢀ Lꢀ
Hꢀ Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
HIGH-Z
HIGH-Z
Hꢀ Lꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Hꢀ Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
PrechargeꢀSelectedꢀBankꢀ
PrechargeꢀBothꢀBanksꢀ
BankꢀActivate(7)ꢀ
Writeꢀ
WriteꢀWithꢀAuto-Precharge(8)ꢀ
Read(8)ꢀ
Xꢀ BSꢀ Lꢀ
Xꢀ Xꢀ Hꢀ
Xꢀ BSꢀ Rowꢀ
Xꢀ BSꢀ Lꢀ Column
Xꢀ BSꢀ Hꢀ Column
Xꢀ BSꢀ Lꢀ Column
Xꢀ BSꢀ Hꢀ ꢀColumn
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
X
X
X
Lꢀ
Rowꢀ
(18)
(18)
(18)
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
X
X
X
X
X
X
X
X
Lꢀ Hꢀ
Lꢀ Hꢀ
Hꢀ Lꢀ
Hꢀ Hꢀ
Xꢀ Xꢀ
Xꢀ Xꢀ
Xꢀ Xꢀ
Xꢀ Xꢀ
ꢀ READAꢀ ReadꢀWithꢀAuto-Precharge(8)ꢀ
ꢀ
(18)
ꢀ BSTꢀ
BurstꢀStop(9)ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ NOPꢀ
ꢀ DESLꢀ
ꢀ SBYꢀ
ꢀ ENBꢀ
ꢀ MASKꢀ
NoꢀOperationꢀ
DeviceꢀDeselectꢀ
Hꢀ Xꢀ Hꢀ
ClockꢀSuspendꢀ/ꢀStandbyꢀModeꢀ Lꢀ Xꢀ Xꢀ
DataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
DataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
Hꢀ Xꢀ Xꢀ
Hꢀ Xꢀ Xꢀ
Active
HIGH-Z
Hꢀ
(1,2)
DQMꢀTRUTHꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCKEꢀ ꢀꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀDQMꢀ
ꢀ
Symbolꢀ Commandꢀ
n-1ꢀ
nꢀ
UPPERꢀ LOWER
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ENBꢀ
DataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
DataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
UpperꢀByteꢀDataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
LowerꢀByteꢀDataꢀWriteꢀ/ꢀOutputꢀEnableꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
L
H
X
L
X
H
MASKꢀ
ENBUꢀ
ENBLꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
MASKUꢀ UpperꢀByteꢀDataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
MASKLꢀ LowerꢀByteꢀDataꢀMaskꢀ/ꢀOutputꢀDisableꢀ
(1,2)
CKEꢀTRUTHꢀTABLE
ꢀ ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCKEꢀ
ꢀ
ꢀ
ꢀ Symbolꢀ Commandꢀ
CurrentꢀStateꢀ
n-1ꢀ nꢀ CSꢀ RASꢀCASꢀ WEꢀ A11ꢀ A10A9-A0ꢀ
ꢀ SPNDꢀ StartꢀClockꢀSuspendꢀModeꢀ
Activeꢀ
OtherꢀStatesꢀ
Hꢀ Lꢀ
Lꢀ Lꢀ
Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
X
X
X
X
ꢀ —ꢀ
ClockꢀSuspendꢀ
ꢀ —ꢀ
TerminateꢀClockꢀSuspendꢀModeꢀ ClockꢀSuspendꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Hꢀ Hꢀ Lꢀ
Hꢀ Lꢀ Lꢀ
ꢀ REFꢀ
Auto-Refreshꢀ
Idleꢀ
Idleꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
ꢀ SELFꢀ StartꢀSelf-RefreshꢀModeꢀ
ꢀ SELFXꢀ TerminateꢀSelf-RefreshꢀModeꢀ
Self-Refreshꢀ
ꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
ꢀ ꢀ
ꢀ
X
ꢀ PDWNꢀ StartꢀPower-DownꢀModeꢀ
Idleꢀ
ꢀ
Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ
ꢀ ꢀ
ꢀ
Hꢀ Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
ꢀ —ꢀ
ꢀ ꢀ
TerminateꢀPower-DownꢀModeꢀ
ꢀ
Power-Downꢀ
ꢀ
Lꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ ꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ
X
ꢀ DPDꢀ
ꢀ —ꢀ
StartꢀDeepꢀPower-DownꢀModeꢀ
TerminateꢀDeepꢀPower-DownꢀModeꢀ
Idleꢀ
Hꢀ Lꢀ Lꢀ Hꢀ Hꢀ Lꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
X
Power-Down
ꢀ
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
CurrentꢀStateꢀꢀꢀCommandꢀ
Operationꢀꢀ
CSꢀ RASꢀCASꢀ WEꢀ A11ꢀ A10
A9-A0ꢀ
IS42VS16100Eꢀ
(1,2)
OPERATIONꢀCOMMANDꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Idleꢀ
DESLꢀ
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Downꢀ
Illegalꢀ
ꢀ
ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READꢀ/ꢀREADAꢀ
WRIT/WRITAꢀ
ACTꢀ
Hꢀ
Lꢀ
V
(18)
ꢀ
Illegalꢀ
Lꢀ
V
(18)
ꢀ
RowꢀActiveꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
V
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperationꢀ
Lꢀ
X
X
ꢀ
Auto-RefreshꢀorꢀSelf-Refresh(13)
ModeꢀRegisterꢀSetꢀ
NoꢀOperationꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
RowꢀActiveꢀ
DESLꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
NoꢀOperationꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
NoꢀOperationꢀ
ReadꢀStart(17)
WriteꢀStart(17)
Illegal(10)
ꢀ
Hꢀ
Lꢀ
V
V
V
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
(18)
ꢀ
ꢀ
Lꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Precharge(15)
ꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODEꢀ
Readꢀ
DESLꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀInterrupted,ꢀReadꢀRestartꢀAfterꢀInterrupt(16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀInterruptedꢀWriteꢀStartꢀAfterꢀInterrupt(11,16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀReadꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Illegalꢀ
Lꢀ
X
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
Writeꢀ
DESLꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀWriteꢀInterrupted,ꢀReadꢀStartꢀAfterꢀInterrupt(11,16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀWriteꢀInterrupted,ꢀWriteꢀRestartꢀAfterꢀInterrupt(16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀWriteꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Lꢀ
X
Illegalꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
ReadꢀWithꢀ
Auto-ꢀ
DESLꢀ
NOPꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Prechargeꢀ
BSTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
V
(18)
(18)
V
V
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
Illegalꢀ
ꢀ OPꢀCODE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
15
Rev.ꢀ 00E
01/21/2011
Illegalꢀ
OPꢀCODE
CurrentꢀStateꢀꢀꢀCommandꢀꢀ
Operationꢀ
CSꢀ RASꢀCASꢀ WEꢀ A11ꢀ A10
A9-A0ꢀ
IS42VS16100Eꢀ
(1,2)
OPERATIONꢀCOMMANDꢀTABLE
WriteꢀWithꢀ
Auto-Prechargeꢀ
DESLꢀ
ꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
WhenꢀDone
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
BSTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
X
(18)
(18)
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
V
V
V
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
Illegalꢀ
ꢀ OPCODE
RowꢀPrechargeꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrp HasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal(10)
Illegal(10)
Illegal(10)
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsed(10)
ꢀ
X
X
Illegalꢀ
Illegalꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
Immediatelyꢀ
Followingꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcDꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcDꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Xꢀ
Xꢀ
Vꢀ
ꢀ
RowꢀActiveꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcDꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
X
(18)
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal(10)
ꢀ
V
Illegal(10)
Illegal(10,14)
ꢀ
Lꢀ Hꢀ Lꢀ
Vꢀ Vꢀ V
(18)
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Hꢀ Vꢀ Vꢀ V
Lꢀ Hꢀ Lꢀ Vꢀ Vꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Illegal(10)
Illegalꢀ
Illegalꢀ
ꢀ
X
X
Lꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀOPꢀCODE
ꢀ
ꢀ
Writeꢀ
Recoveryꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtDpl HasꢀElapsed
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtDpl HasꢀElapsed
ꢀ
ꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtDplꢀHasꢀElapsed
ꢀ
Lꢀ Hꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Vꢀ Vꢀ V
Xꢀ Xꢀ
X
(18)
(18)
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
ReadꢀStartꢀ
WriteꢀRestartꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ
Lꢀ Hꢀ Hꢀ Vꢀ Vꢀ V
Lꢀ Hꢀ Lꢀ Vꢀ Vꢀ
Lꢀ Hꢀ Xꢀ Xꢀ
Lꢀ Lꢀ
Vꢀ Vꢀ V
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
X
X
Lꢀ
Lꢀ
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
CurrentꢀStateꢀꢀCommandꢀ
Operationꢀ
CSꢀ RASꢀCASꢀ WEꢀ A11ꢀ A10
A9-A0ꢀ
IS42VS16100Eꢀ
(1,2)
OPERATIONꢀCOMMANDꢀTABLE
ꢀWriteꢀRecoveryꢀ
ꢀWithꢀAuto-ꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtDalꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtDalꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀPrechargeꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtDalꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
Illegal(10)
Illegal(10)
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
ꢀ
V
(18)
ꢀ
Hꢀ
Lꢀ
V
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
ꢀ
Hꢀ
Lꢀ
ꢀ
Illegalꢀ
ꢀ OPꢀCODE
Refreshꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrp HasꢀElapsedꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
Hꢀ
Lꢀ
X
ꢀ OPꢀCODE
ꢀ
ꢀ
ModeꢀRegisterꢀ DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcDꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcDꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Setꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcDꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
V
V
V
(18)
(18)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
X
X
ꢀ
ꢀ OPꢀCODE
Notes:ꢀ
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput,ꢀV:ꢀValidꢀdataꢀinput
2.ꢀAllꢀinputꢀsignalsꢀareꢀlatchedꢀonꢀtheꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignal.
3.ꢀBothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
4.ꢀTheꢀstateꢀofꢀtheꢀA0ꢀtoꢀA11ꢀpinsꢀisꢀloadedꢀintoꢀtheꢀmodeꢀregisterꢀasꢀanꢀOPꢀcode.
5.ꢀTheꢀrowꢀaddressꢀisꢀgeneratedꢀautomaticallyꢀinternallyꢀatꢀthisꢀtime.ꢀTheꢀDQꢀpinꢀandꢀtheꢀaddressꢀpinꢀdataꢀisꢀignored.
6.ꢀDuringꢀaꢀself-refreshꢀoperation,ꢀallꢀpinꢀdataꢀ(states)ꢀotherꢀthanꢀCKEꢀisꢀignored.
7.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
8.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀactiveꢀstateꢀinꢀadvance.
9.ꢀThisꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀburstꢀlengthꢀsetꢀtoꢀfullꢀpage.
10.ꢀThisꢀisꢀpossibleꢀdependingꢀonꢀtheꢀstateꢀofꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀpin.
11.ꢀTimeꢀtoꢀswitchꢀinternalꢀbussesꢀisꢀrequired.
12.ꢀTheꢀIS42VS16100Eꢀcanꢀbeꢀswitchedꢀtoꢀpower-downꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀꢀ
state.ꢀInputꢀpinsꢀotherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
13.ꢀTheꢀIS42VS16100Eꢀcanꢀbeꢀswitchedꢀtoꢀself-refreshꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀstate.ꢀ
InputꢀpinsꢀotherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
14.ꢀPossibleꢀifꢀtrrDꢀisꢀsatisfied.
15.ꢀIllegalꢀifꢀtrasꢀisꢀnotꢀsatisfied.
16.ꢀTheꢀconditionsꢀforꢀburstꢀinterruptionꢀmustꢀbeꢀobserved.ꢀAlsoꢀnoteꢀthatꢀtheꢀIS42VS16100Eꢀwillꢀenterꢀtheꢀprechargedꢀstateꢀꢀ
immediatelyꢀafterꢀtheꢀburstꢀoperationꢀcompletesꢀifꢀauto-prechargeꢀisꢀselected.
17.ꢀCommandꢀinputꢀbecomesꢀpossibleꢀafterꢀtheꢀperiodꢀtrcD hasꢀelapsed.ꢀAlsoꢀnoteꢀthatꢀtheꢀIS42VS16100Eꢀwillꢀenterꢀtheꢀpre-
chargedꢀstateꢀimmediatelyꢀafterꢀtheꢀburstꢀoperationꢀcompletesꢀifꢀauto-prechargeꢀisꢀselected.
18.ꢀꢀA8,A9ꢀꢀ=ꢀdon’tꢀcare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
17
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
(1)
CKEꢀRELATEDꢀCOMMANDꢀTRUTHꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCKEꢀ ꢀ
ꢀ
ꢀ
CurrentꢀStateꢀ
Operationꢀ
n-1ꢀ
Hꢀ
Lꢀ
n
CSꢀ RASꢀ CASꢀ WEꢀ A11ꢀ A10ꢀ A9-A0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Self-Refreshꢀ
Undefinedꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Xꢀ
ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Self-RefreshꢀRecovery(2)ꢀ
Illegal(2)ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Illegal(2)ꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Self-Refreshꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Self-RefreshꢀRecoveryꢀ
IdleꢀStateꢀAfterꢀtrcꢀHasꢀElapsedꢀ
IdleꢀStateꢀAfterꢀtrcꢀHasꢀElapsedꢀ
Illegalꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
Illegalꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Power-DownꢀonꢀtheꢀNextꢀCycleꢀ
Power-DownꢀonꢀtheꢀNextꢀCycleꢀ
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycleꢀ(2)ꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ClockꢀSuspendꢀ
Undefinedꢀ
Lꢀ
Power-Downꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power-DownꢀModeꢀTermination,ꢀIdleꢀAfterꢀꢀ
ThatꢀTermination(2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power-DownꢀModeꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
BothꢀBanksꢀIdleꢀ
NoꢀOperationꢀ
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
BankꢀActiveꢀOrꢀPrechargeꢀ
Auto-Refreshꢀ
ꢀ
ꢀ
ꢀ
ModeꢀRegisterꢀSetꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
Self-Refresh(3)ꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
ꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
Power-DownꢀMode(3)ꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
OtherꢀStatesꢀ
SeeꢀtheꢀOperationꢀCommandꢀTableꢀ
ClockꢀSuspendꢀonꢀtheꢀNextꢀCycle(4)ꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycleꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
Lꢀ
ClockꢀSuspendꢀTerminationꢀonꢀtheꢀNextꢀCycle
ꢀ
Lꢀ
Notes:ꢀ
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput
2.ꢀTheꢀCLKꢀpinꢀandꢀtheꢀotherꢀinputꢀareꢀreactivatedꢀasynchronouslyꢀbyꢀtheꢀtransitionꢀofꢀtheꢀCKEꢀlevelꢀfromꢀLOWꢀtoꢀHIGH.ꢀꢀ
Theꢀminimumꢀsetupꢀtimeꢀ(tcka)ꢀrequiredꢀbeforeꢀallꢀcommandsꢀotherꢀthanꢀmodeꢀterminationꢀmustꢀbeꢀsatisfied.
3.ꢀBothꢀbanksꢀmustꢀbeꢀsetꢀtoꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvanceꢀtoꢀswitchꢀtoꢀpower-downꢀmodeꢀorꢀself-refreshꢀmode.
4.ꢀTheꢀinputꢀmustꢀbeꢀcommandꢀdefinedꢀinꢀtheꢀoperationꢀcommandꢀtable.
ꢀꢀꢀꢀꢀ
18ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
Operation
CSꢀ RASꢀCASꢀ WEꢀ A11ꢀ A10
BANKꢀ1ꢀ BANKꢀ0
BANKꢀ1
IS42VS16100Eꢀ
(1,2)
TWOꢀBANKSꢀOPERATIONꢀCOMMANDꢀTRUTHꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀPreviousꢀStateꢀꢀꢀꢀꢀꢀꢀNextꢀStateꢀ
A9-A0ꢀꢀ BANKꢀ0
ꢀ
ꢀ
DESLꢀ
NOPꢀ
Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Any
Any
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
Lꢀ Hꢀ Hꢀ Lꢀ
Xꢀ Xꢀ Xꢀ
R/W/Aꢀ I/Aꢀ
Iꢀ I/Aꢀ
I/Aꢀ R/W/Aꢀ
I/Aꢀ Iꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ
Iꢀ
I/Aꢀ
I/Aꢀ
I/Aꢀ
Aꢀ
I/Aꢀ
Aꢀ
RPꢀ
RPꢀ
Rꢀ
Rꢀ
I/Aꢀ
Aꢀ
I/Aꢀ
I/Aꢀ
Aꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I
READ/READAꢀ
Lꢀ Hꢀ Lꢀ Hꢀ Hꢀ Hꢀ CA(3)ꢀ
RP
RP
R
R
I/A
A
I/A
A
WP
WP
W
W
I/A
A
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Hꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
WRIT/WRITAꢀ
Lꢀ Hꢀ Lꢀ
Lꢀ Hꢀ Hꢀ CA(3)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Hꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Hꢀ Lꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
Lꢀ Hꢀ CA(3)ꢀ
I/Aꢀ
Aꢀ
WPꢀ
WPꢀ
Wꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
I/A
A
Aꢀ
R/Wꢀ
Wꢀ
ꢀ
ꢀ
ACTꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ Hꢀ Hꢀ Hꢀ RAꢀ RAꢀ
Anyꢀ
Iꢀ
Iꢀ
Anyꢀ
Anyꢀ
Aꢀ
Aꢀ
Any
ꢀ
ꢀ
ꢀ
Lꢀ RAꢀ RAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
PRE/PALLꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ Hꢀ Lꢀ
Xꢀ Hꢀ Xꢀ
Xꢀ Hꢀ Xꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
I/Aꢀ R/W/A/Iꢀ
R/W/A/Iꢀ I/Aꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
Iꢀ
Iꢀ
I/Aꢀ
Iꢀ
Iꢀ
Iꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Lꢀ
Hꢀ Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
R/W/A/Iꢀ Iꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Iꢀ
I/Aꢀ
ꢀ
Iꢀ R/W/A/I
ꢀ
ꢀ
REFꢀ
MRSꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Hꢀ Xꢀ Xꢀ Xꢀ
Lꢀ Lꢀ ꢀOPCODEꢀꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
I
I
Notes:ꢀ
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput,ꢀRA:ꢀRowꢀAddress,ꢀCA:ꢀColumnꢀAddress
2.ꢀTheꢀdeviceꢀstateꢀsymbolsꢀareꢀinterpretedꢀasꢀfollows:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Iꢀ
Aꢀ
Rꢀ
Idleꢀ(inactiveꢀstate)
RowꢀActiveꢀState
Read
Wꢀ Write
RPꢀ ReadꢀWithꢀAuto-Precharge
WPꢀ WriteꢀWithꢀAuto-Precharge
Anyꢀ AnyꢀState
3.ꢀꢀCA:ꢀA8,A9ꢀ=ꢀdon’tꢀcare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
19
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
SIMPLIFIEDꢀSTATEꢀTRANSITIONꢀDIAGRAMꢀ(OneꢀBankꢀOperation)
SELF
REFRESH
SREF entry
SREF exit
MRS
MODE
REGISTER
SET
AUTO
REF
IDLE
REFRESH
CKE_
CKE
IDLE
ACT
POWER
DOWN
ACTIVE
POWER
DOWN
CKE_
CKE
BANK
ACTIVE
BST
BST
READ
WRIT
WRIT
CKE_
READ
CKE_
WRITA
READA
READ
WRITE
READ
WRIT
CKE
READA
CKE_
CLOCK
SUSPEND
CKE
CLOCK
SUSPEND
WRITA
WRITA
READA
CKE_
CKE
CKE
WRITE WITH
AUTO
READ WITH
AUTO
PRECHARGE
PRECHARGE
PRE
PRE
PRE
PRE-
CHARGE
PRE
POWER APPLIED
POWER ON
Automatic transition following the
completion of command execution.
Transition due to command input.
20ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
DeviceꢀInitializationꢀAtꢀPower-On
BurstꢀLength
(Power-OnꢀSequence)
Whenꢀwritingꢀorꢀreading,ꢀdataꢀcanꢀbeꢀinputꢀorꢀoutputꢀdataꢀ
continuously.ꢀInꢀtheseꢀoperations,ꢀanꢀaddressꢀisꢀinputꢀonlyꢀ
onceꢀandꢀthatꢀaddressꢀisꢀtakenꢀasꢀtheꢀstartingꢀaddressꢀ
internallyꢀ byꢀ theꢀ device.ꢀTheꢀ deviceꢀ thenꢀ automaticallyꢀ
generatesꢀ theꢀ followingꢀ address.ꢀTheꢀ burstꢀ lengthꢀ fieldꢀ
inꢀtheꢀmodeꢀregisterꢀstipulatesꢀtheꢀnumberꢀofꢀdataꢀitemsꢀ
inputꢀorꢀoutputꢀinꢀsequence.ꢀInꢀtheꢀIS42VS16100Eꢀproduct,ꢀ
aꢀburstꢀlengthꢀofꢀ1,ꢀ2,ꢀ4,ꢀ8,ꢀorꢀfullꢀpageꢀcanꢀbeꢀspecified.ꢀ
Seeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀonꢀsettingꢀtheꢀ
modeꢀregister.
AsꢀisꢀtheꢀcaseꢀwithꢀconventionalꢀDRAMs,ꢀtheꢀIS42VS16100Eꢀ
productꢀmustꢀbeꢀinitializedꢀbyꢀexecutingꢀaꢀstipulatedꢀpower-
onꢀsequenceꢀafterꢀpowerꢀisꢀapplied.
AfterꢀpowerꢀisꢀappliedꢀandꢀVDDꢀandꢀVDDQꢀreachꢀtheirꢀ
stipulatedꢀvoltages,ꢀsetꢀandꢀholdꢀtheꢀCKEꢀandꢀDQMꢀpinsꢀ
HIGHꢀforꢀ100ꢀµs.ꢀThen,ꢀexecuteꢀtheꢀprechargeꢀcommandꢀ
toꢀprechargeꢀbothꢀbank.ꢀNext,ꢀexecuteꢀtheꢀauto-refreshꢀ
commandꢀtwiceꢀorꢀmoreꢀandꢀdefineꢀtheꢀdeviceꢀoperationꢀ
modeꢀbyꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀcommand.
Theꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀalsoꢀsetꢀbeforeꢀ
auto-refreshꢀcommand.
BurstꢀType
Theꢀ burstꢀ dataꢀ orderꢀ duringꢀ aꢀ readꢀ orꢀ writeꢀ operationꢀ
isꢀstipulatedꢀbyꢀtheꢀburstꢀtype,ꢀwhichꢀcanꢀbeꢀsetꢀbyꢀtheꢀ
modeꢀregisterꢀsetꢀcommand.ꢀTheꢀIS42VS16100Eꢀproductꢀ
supportsꢀ sequentialꢀ modeꢀ andꢀ interleavedꢀ modeꢀ burstꢀ
typeꢀsettings.ꢀSeeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀ
onꢀsettingꢀtheꢀmodeꢀregister.ꢀSeeꢀtheꢀ“BurstꢀLengthꢀandꢀ
ColumnꢀAddressꢀSequence”ꢀitemꢀforꢀdetailsꢀonꢀDQꢀdataꢀ
ordersꢀinꢀtheseꢀmodes.
ModeꢀRegisterꢀSettingsꢀ
Theꢀmodeꢀregisterꢀsetꢀcommandꢀsetsꢀtheꢀmodeꢀregister.ꢀ
Whenꢀthisꢀcommandꢀisꢀexecuted,ꢀpinsꢀA0ꢀtoꢀA9,ꢀA10,ꢀandꢀ
A11ꢀfunctionꢀasꢀdataꢀinputꢀpinsꢀforꢀsettingꢀtheꢀregister,ꢀandꢀ
thisꢀdataꢀbecomesꢀtheꢀdeviceꢀinternalꢀOPꢀcode.ꢀThisꢀOPꢀ
codeꢀhasꢀfourꢀfieldsꢀasꢀlistedꢀinꢀtheꢀtableꢀbelow.
ꢀ
InputꢀPinꢀ
Fieldꢀ
WriteꢀMode
BurstꢀwriteꢀorꢀsingleꢀwriteꢀmodeꢀisꢀselectedꢀbyꢀtheꢀOPꢀ
codeꢀ(A11,ꢀA10,ꢀA9)ꢀofꢀtheꢀmodeꢀregister.
ꢀA11,ꢀA10,ꢀA9,ꢀA8,ꢀA7ꢀ
ModeꢀOptions
CASꢀLatency
BurstꢀType
ꢀ
ꢀ
ꢀ
A6,ꢀA5,ꢀA4ꢀ
A3ꢀ
A2,ꢀA1,ꢀA0ꢀ
AꢀburstꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀtheꢀOPꢀcodeꢀ
(A11,ꢀA10,ꢀA9)ꢀtoꢀ(0,0,0).ꢀAꢀburstꢀwriteꢀstartsꢀonꢀtheꢀsameꢀ
cycleꢀasꢀaꢀwriteꢀcommandꢀset.ꢀTheꢀwriteꢀstartꢀaddressꢀisꢀ
specifiedꢀbyꢀtheꢀcolumnꢀaddressꢀandꢀbankꢀselectꢀaddressꢀ
atꢀtheꢀwriteꢀcommandꢀsetꢀcycle.
BurstꢀLength
Noteꢀthatꢀtheꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀexecutedꢀ
onlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀ(inactive)ꢀstate.ꢀWaitꢀ
atꢀleastꢀtwoꢀcyclesꢀafterꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀ
commandꢀbeforeꢀexecutingꢀtheꢀnextꢀcommand.
AꢀsingleꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀOPꢀcodeꢀ(A11,ꢀ
A10,ꢀA9)ꢀtoꢀ(0,ꢀ0,1).ꢀInꢀaꢀsingleꢀwriteꢀoperation,ꢀdataꢀisꢀonlyꢀ
writtenꢀtoꢀtheꢀcolumnꢀaddressꢀandꢀbankꢀselectꢀaddressꢀ
specifiedꢀbyꢀtheꢀwriteꢀcommandꢀsetꢀcycleꢀwithoutꢀregardꢀ
toꢀtheꢀbustꢀlengthꢀsetting.
CASꢀLatency
Duringꢀaꢀreadꢀoperation,ꢀtheꢀbetweenꢀtheꢀexecutionꢀofꢀtheꢀ
readꢀcommandꢀandꢀdataꢀoutputꢀisꢀstipulatedꢀasꢀtheꢀCASꢀ
latency.ꢀThisꢀperiodꢀcanꢀbeꢀsetꢀusingꢀtheꢀmodeꢀregisterꢀsetꢀ
command.ꢀTheꢀoptimalꢀCASꢀlatencyꢀisꢀdeterminedꢀbyꢀtheꢀ
clockꢀfrequencyꢀandꢀdeviceꢀspeedꢀgradeꢀ(-10).ꢀSeeꢀtheꢀ
“OperatingꢀFrequencyꢀ/ꢀLatencyꢀRelationships”ꢀitemꢀꢀforꢀ
detailsꢀonꢀtheꢀrelationshipꢀbetweenꢀtheꢀclockꢀfrequencyꢀ
andꢀtheꢀCASꢀlatency.ꢀSeeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀ
detailsꢀonꢀsettingꢀtheꢀmodeꢀregister.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
21
Rev.ꢀ 00E
01/21/2011
WRITEꢀMODEꢀ ꢀ LTꢀ
MODEꢀ ꢀ BTꢀ
ꢀ
BL
IS42VS16100Eꢀ
MODEꢀREGISTER
AddressꢀBusꢀ(Ax)
ModeꢀRegisterꢀ(Mx)
ꢀA11ꢀA10ꢀ A9ꢀ A8ꢀ A7ꢀ A6ꢀ A5ꢀ A4ꢀ A3ꢀ A2ꢀ A1ꢀ A0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
M2ꢀ M1ꢀ M0ꢀ Sequentialꢀ Interleaved
BurstꢀLengthꢀ 0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
1ꢀ
2ꢀ
4ꢀ
8ꢀ
1
2
4
8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
Reservedꢀ Reserved
Reservedꢀ Reserved
Reservedꢀ Reserved
FullꢀPageꢀ Reserved
ꢀ
ꢀ
M3ꢀ
0ꢀ
1ꢀ
Type
ꢀ
ꢀ
BurstꢀTypeꢀ
ꢀ
Sequential
Interleavedꢀ
ꢀ
ꢀ
M6ꢀ M5ꢀ M4ꢀ CASꢀLatency
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
LatencyꢀModeꢀ 0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
Reserved
Reserved
2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
3
Reserved
Reserved
Reserved
Reserved
ꢀ M11ꢀ M10ꢀ
M9ꢀ
1ꢀ
0ꢀ
M8ꢀ
0ꢀ
0ꢀ
M7ꢀ
0ꢀ
0ꢀ
WriteꢀModeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
BurstꢀReadꢀ&ꢀSingleꢀWrite
BurstꢀReadꢀ&ꢀBurstꢀWrite
Note:ꢀOtherꢀvaluesꢀforꢀtheseꢀbitsꢀareꢀreserved.
22ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
BURSTꢀLENGTHꢀANDꢀCOLUMNꢀADDRESSꢀSEQUENCE
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀColumnꢀAddressꢀ
ꢀ AddressꢀSequence
Sequentialꢀ Interleaved
ꢀBurstꢀLengthꢀ A2ꢀ A1ꢀ A0ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
1ꢀ
0-1ꢀ
1-0ꢀ
0-1ꢀ
1-0
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
0-1-2-3ꢀ
1-0-3-2ꢀ
2-3-0-1ꢀ
3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
2-3-4-5-6-7-0-1ꢀ
3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
0-1-2-3-4-5-6-7ꢀ
1-0-3-2-5-4-7-6ꢀ
2-3-0-1-6-7-4-5ꢀ
3-2-1-0-7-6-5-4ꢀ
4-5-6-7-0-1-2-3ꢀ
5-4-7-6-1-0-3-2ꢀ
6-7-4-5-2-3-0-1ꢀ
7-6-5-4-3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
FullꢀPageꢀ
(256)ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
Cn,ꢀCn+1,ꢀCn+2ꢀ
Cn+3,ꢀCn+4.....ꢀ
...Cn-1(Cn+255),ꢀ
Cn(Cn+256).....ꢀ
Noneꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:ꢀ
1.ꢀTheꢀburstꢀlengthꢀinꢀfullꢀpageꢀmodeꢀisꢀ256.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
23
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
BANKꢀSELECTꢀANDꢀPRECHARGEꢀADDRESSꢀALLOCATION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Rowꢀ
X0ꢀ
X1ꢀ
X2ꢀ
X3ꢀ
X4ꢀ
X5ꢀ
X6ꢀ
X7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X8ꢀ
—ꢀ
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X9ꢀ
X10ꢀ
ꢀ
—ꢀ
0ꢀ
1ꢀ
RowꢀAddressꢀ
PrechargeꢀofꢀtheꢀSelectedꢀBankꢀ(PrechargeꢀCommand)ꢀ RowꢀAddressꢀ
PrechargeꢀofꢀBothꢀBanksꢀ(PrechargeꢀCommand)ꢀ
(Activeꢀ
Command)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X11ꢀ
ꢀ
0ꢀ
1ꢀ
Bankꢀ0ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommand)ꢀ
Bankꢀ1ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommand)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Columnꢀ
Y0ꢀ
Y1ꢀ
Y2ꢀ
Y3ꢀ
Y4ꢀ
Y5ꢀ
Y6ꢀ
Y7ꢀ
Y8ꢀ
Y9ꢀ
Y10ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Don’tꢀCareꢀ
Don’tꢀCareꢀ
Auto-Prechargeꢀ-ꢀDisabledꢀ
Auto-Prechargeꢀ-ꢀEnablesꢀ
Bankꢀ0ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)ꢀ
Bankꢀ1ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)
1ꢀ
0ꢀ
1ꢀ
Y11ꢀ
ꢀ
24ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
BurstꢀRead
Theꢀreadꢀcycleꢀisꢀstartedꢀbyꢀexecutingꢀtheꢀreadꢀcommand.ꢀ
Theꢀaddressꢀprovidedꢀduringꢀreadꢀcommandꢀexecutionꢀisꢀ
usedꢀasꢀtheꢀstartingꢀaddress.ꢀFirst,ꢀtheꢀdataꢀcorrespondingꢀtoꢀ
thisꢀaddressꢀisꢀoutputꢀinꢀsynchronizationꢀwithꢀtheꢀclockꢀsignalꢀ
afterꢀtheꢀCASꢀlatencyꢀperiod.ꢀNext,ꢀdataꢀcorrespondingꢀtoꢀ
anꢀaddressꢀgeneratedꢀautomaticallyꢀbyꢀtheꢀdeviceꢀisꢀoutputꢀ
inꢀsynchronizationꢀwithꢀtheꢀclockꢀsignal.
isꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀInꢀthisꢀcaseꢀtheꢀoutputꢀbuffersꢀ
mustꢀbeꢀsetꢀtoꢀtheꢀhighꢀimpedanceꢀstateꢀbyꢀexecutingꢀaꢀ
burstꢀstopꢀcommand.
Noteꢀ thatꢀ upperꢀ byteꢀ andꢀ lowerꢀ byteꢀ outputꢀ dataꢀ canꢀ
beꢀmaskedꢀindependentlyꢀunderꢀcontrolꢀofꢀtheꢀsignalsꢀ
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tqmD)ꢀisꢀ
fixedꢀatꢀtwo,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting,ꢀwhenꢀ
thisꢀfunctionꢀisꢀused.
TheꢀoutputꢀbuffersꢀgoꢀtoꢀtheꢀLOWꢀimpedanceꢀstateꢀCASꢀ
latencyꢀminusꢀoneꢀcycleꢀafterꢀtheꢀreadꢀcommand,ꢀandꢀgoꢀ
toꢀtheꢀHIGHꢀimpedanceꢀstateꢀautomaticallyꢀafterꢀtheꢀlastꢀ
dataꢀisꢀoutput.ꢀHowever,ꢀtheꢀcaseꢀwhereꢀtheꢀburstꢀlengthꢀ
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
HI-Z
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
BurstꢀWrite
Theꢀwriteꢀcycleꢀisꢀstartedꢀbyꢀexecutingꢀtheꢀcommand.ꢀTheꢀ
addressꢀprovidedꢀduringꢀwriteꢀcommandꢀexecutionꢀisꢀusedꢀ
asꢀtheꢀstartingꢀaddress,ꢀandꢀatꢀtheꢀsameꢀtime,ꢀdataꢀforꢀthisꢀ
addressꢀisꢀinputꢀinꢀsynchronizationꢀwithꢀtheꢀclockꢀsignal.
isꢀzero,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting.ꢀHowever,ꢀaꢀ
waitꢀperiodꢀ(writeꢀrecovery:ꢀtDpl)ꢀafterꢀtheꢀlastꢀdataꢀinputꢀisꢀ
requiredꢀforꢀtheꢀdeviceꢀtoꢀcompleteꢀtheꢀwriteꢀoperation.
Noteꢀthatꢀtheꢀupperꢀbyteꢀandꢀlowerꢀbyteꢀinputꢀdataꢀcanꢀ
beꢀ maskedꢀ independentlyꢀ underꢀ controlꢀ ofꢀ theꢀ signalsꢀ
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tDmD)ꢀisꢀ
fixedꢀatꢀzero,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting,ꢀwhenꢀ
thisꢀfunctionꢀisꢀused.
Next,ꢀdataꢀisꢀinputꢀinꢀotherꢀinꢀsynchronizationꢀwithꢀtheꢀ
clockꢀ signal.ꢀ Duringꢀ thisꢀ operation,ꢀ dataꢀ isꢀ writtenꢀ toꢀ
addressꢀgeneratedꢀautomaticallyꢀbyꢀtheꢀdevice.ꢀThisꢀcycleꢀ
terminatesꢀautomaticallyꢀafterꢀaꢀnumberꢀofꢀclockꢀcyclesꢀ
determinedꢀbyꢀtheꢀstipulatedꢀburstꢀlength.ꢀHowever,ꢀtheꢀ
caseꢀwhereꢀtheꢀburstꢀlengthꢀisꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀ
Inꢀthisꢀcaseꢀtheꢀwriteꢀcycleꢀmustꢀbeꢀterminatedꢀbyꢀexecutingꢀ
aꢀburstꢀꢀstopꢀcommand.ꢀꢀTheꢀlatencyꢀforꢀDQꢀpinꢀdataꢀinputꢀ
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
WRITE
DIN
0
DIN
1
DIN
2
DIN 3
BURST LENGTH
CAS ꢀlatencyꢀ=ꢀ2,3,ꢀburstꢀlengthꢀ=ꢀ4
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25
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀWithꢀAuto-Precharge
Theꢀreadꢀwithꢀauto-prechargeꢀcommandꢀfirstꢀexecutesꢀaꢀ
burstꢀreadꢀoperationꢀandꢀthenꢀputsꢀtheꢀselectedꢀbankꢀinꢀ
theꢀprechargedꢀstateꢀautomatically.ꢀAfterꢀtheꢀprechargeꢀ
completes,ꢀ theꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ state.ꢀ Thusꢀ thisꢀ
commandꢀperformsꢀaꢀreadꢀcommandꢀandꢀaꢀprechargeꢀ
commandꢀinꢀaꢀsingleꢀoperation.
three,ꢀtheꢀprechargeꢀoperationꢀstartsꢀonꢀtwoꢀclockꢀcyclesꢀ
beforeꢀtheꢀlastꢀburstꢀdataꢀisꢀoutputꢀ(tpqlꢀ=ꢀ–2).ꢀTherefore,ꢀ
theꢀselectedꢀbankꢀcanꢀbeꢀmadeꢀactiveꢀafterꢀaꢀdelayꢀofꢀtrpꢀ
fromꢀtheꢀstartꢀpositionꢀofꢀthisꢀprechargeꢀoperation.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
Duringꢀthisꢀoperation,ꢀtheꢀdelayꢀperiodꢀ(tpql)ꢀbetweenꢀtheꢀ
lastꢀburstꢀdataꢀoutputꢀandꢀtheꢀstartꢀofꢀtheꢀprechargeꢀopera-
tionꢀdiffersꢀdependingꢀonꢀtheꢀCASꢀlatencyꢀsetting.
Theꢀauto-prechargeꢀfunctionꢀisꢀinvalidꢀifꢀtheꢀburstꢀlengthꢀ
isꢀsetꢀtoꢀfullꢀpage.
WhenꢀtheꢀCASꢀlatencyꢀsettingꢀisꢀtwo,ꢀtheꢀprechargeꢀopera-
tionꢀstartsꢀonꢀoneꢀclockꢀcycleꢀbeforeꢀtheꢀlastꢀburstꢀdataꢀisꢀ
outputꢀ(tpqlꢀ=ꢀ–1).ꢀWhenꢀtheꢀCASꢀlatencyꢀsettingꢀisꢀ
ꢀ
CASꢀLatencyꢀ
3ꢀ
2ꢀ
ꢀ
tpqlꢀ
–2ꢀ
–1ꢀ
CLK
COMMAND
DQ
READA 0
ACT 0
t
PQL
DOUT
0
D
OUT
1
D
OUT DOUT 3
2
tRP
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
COMMAND
DQ
ACT 0
READA 0
t
PQL
D
OUT
0
D
OUT
1
D
OUT
2
DOUT 3
t
RP
READ WITH AUTO-PRECHARGE
(BANK 0)
PRECHARGE START
CAS latencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
26ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀWithꢀAuto-Precharge
Theꢀwriteꢀwithꢀauto-prechargeꢀcommandꢀfirstꢀexecutesꢀaꢀ
burstꢀwriteꢀoperationꢀandꢀthenꢀputsꢀtheꢀselectedꢀbankꢀinꢀ
theꢀprechargedꢀstateꢀautomatically.ꢀAfterꢀtheꢀprechargeꢀ
completesꢀ theꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ state.ꢀ Thusꢀ thisꢀ
commandꢀperformsꢀaꢀwriteꢀcommandꢀandꢀaꢀprechargeꢀ
commandꢀinꢀaꢀsingleꢀoperation.
Therefore,ꢀtheꢀselectedꢀbankꢀcanꢀbeꢀmadeꢀactiveꢀafterꢀaꢀ
delayꢀofꢀtDal.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
Theꢀauto-prechargeꢀfunctionꢀisꢀinvalidꢀifꢀtheꢀburstꢀlengthꢀ
isꢀsetꢀtoꢀfullꢀpage.
Duringꢀthisꢀoperation,ꢀtheꢀdelayꢀperiodꢀ(tDal)ꢀbetweenꢀtheꢀ
lastꢀburstꢀdataꢀinputꢀandꢀtheꢀcompletionꢀofꢀtheꢀprechargeꢀ
operationꢀdiffersꢀdependingꢀonꢀtheꢀCASꢀlatencyꢀsetting.ꢀ
Theꢀdelayꢀ(tDal)ꢀisꢀtrpꢀplusꢀoneꢀCLKꢀperiod.ꢀThatꢀis,ꢀtheꢀ
prechargeꢀoperationꢀstartsꢀoneꢀclockꢀperiodꢀafterꢀtheꢀlastꢀ
burstꢀdataꢀinput.ꢀ
ꢀ
CASꢀLatencyꢀ
3ꢀ
2
ꢀ
ꢀ
tDalꢀ
ꢀ
2CLKꢀ
+trpꢀ
2CLK
+trp
CLK
COMMAND
DQ
WRITE A0
ACT 0
PRECHARGE START
DIN
0
D
IN
1
D
IN
2
DIN 3
t
RP
tDAL
WRITE WITH AUTO-PRECHARGE
(BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
ACT 0
COMMAND
DQ
WRITE A0
PRECHARGE START
DIN
0
D
IN
1
D
IN
2
DIN 3
t
RP
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tDAL
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
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27
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
IntervalꢀBetweenꢀReadꢀCommand
Aꢀnewꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀreadꢀcycleꢀisꢀ
inꢀprogress,ꢀi.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀWhenꢀtheꢀ
secondꢀreadꢀcommandꢀisꢀexecuted,ꢀafterꢀtheꢀCASꢀlatencyꢀ
hasꢀelapsed,ꢀdataꢀcorrespondingꢀtoꢀtheꢀnewꢀreadꢀcommandꢀ
isꢀoutputꢀinꢀplaceꢀofꢀtheꢀdataꢀdueꢀtoꢀtheꢀpreviousꢀreadꢀ
command.
Theꢀintervalꢀbetweenꢀtwoꢀreadꢀcommandꢀ(tccD)ꢀmustꢀbeꢀ
atꢀleastꢀoneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
READ A0
READ B0
D
OUT A0
DOUT B0
D
OUT B1
DOUT B3
DOUT B2
tCCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
IntervalꢀBetweenꢀWriteꢀCommand
Aꢀnewꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀisꢀinꢀ
progress,ꢀi.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀAtꢀtheꢀpointꢀtheꢀ
secondꢀwriteꢀcommandꢀisꢀexecuted,ꢀdataꢀcorrespondingꢀ
toꢀtheꢀnewꢀwriteꢀcommandꢀcanꢀbeꢀinputꢀinꢀplaceꢀofꢀtheꢀ
dataꢀforꢀtheꢀpreviousꢀwriteꢀcommand.
Theꢀintervalꢀbetweenꢀtwoꢀwriteꢀcommandsꢀ(tccD)ꢀmustꢀbeꢀ
atꢀleastꢀoneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITE A0 WRITE B0
DIN A0
D
IN B0
D
IN B1
D
IN B2
DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
28ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
IntervalꢀBetweenꢀWriteꢀandꢀReadꢀCommands
Aꢀnewꢀreadꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀ
isꢀ inꢀ progress,ꢀ i.e.,ꢀ beforeꢀ thatꢀ cycleꢀ completes.ꢀ Dataꢀ
correspondingꢀtoꢀtheꢀnewꢀreadꢀcommandꢀisꢀoutputꢀafterꢀ
theꢀCASꢀlatencyꢀhasꢀelapsedꢀfromꢀtheꢀpointꢀtheꢀnewꢀreadꢀ
commandꢀwasꢀexecuted.ꢀTheꢀDQnꢀpinsꢀmustꢀbeꢀplacedꢀinꢀ
theꢀHIGHꢀimpedanceꢀstateꢀatꢀleastꢀoneꢀcycleꢀbeforeꢀdataꢀ
isꢀoutputꢀduringꢀthisꢀoperation.
Theꢀintervalꢀ(tccD)ꢀbetweenꢀcommandꢀmustꢀbeꢀatꢀleastꢀ
oneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
CCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
29
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
IntervalꢀBetweenꢀReadꢀandꢀWriteꢀCommands
Aꢀreadꢀcommandꢀcanꢀbeꢀinterruptedꢀandꢀaꢀnewꢀwriteꢀ
commandꢀexecutedꢀwhileꢀtheꢀreadꢀcycleꢀisꢀinꢀprogress,ꢀ
i.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀDataꢀcorrespondingꢀ
toꢀtheꢀnewꢀwriteꢀcommandꢀcanꢀbeꢀinputꢀatꢀtheꢀpointꢀ
newꢀwriteꢀcommandꢀisꢀexecuted.ꢀToꢀpreventꢀcollisionꢀ
betweenꢀinputꢀandꢀoutputꢀdataꢀatꢀtheꢀDQnꢀpinsꢀduringꢀ
thisꢀoperation,ꢀtheꢀ
outputꢀdataꢀmustꢀbeꢀmaskedꢀusingꢀtheꢀU/LDQMꢀpins.ꢀTheꢀ
intervalꢀ(tccD)ꢀbetweenꢀtheseꢀcommandsꢀmustꢀbeꢀatꢀleastꢀ
oneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
WRITE B0
COMMAND
U/LDQM
DQ
READ A0
HI-Z
DIN B0
D
IN B1
DIN B2
DIN B3
READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latencyꢀ=ꢀ2,ꢀ3,ꢀburstlengthꢀ=ꢀ4
30ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
Precharge
ReadꢀCycleꢀInterruption
TheꢀprechargeꢀcommandꢀsetsꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀ
toꢀtheꢀprechargedꢀstate.ꢀThisꢀcommandꢀcanꢀbeꢀexecutedꢀatꢀ
aꢀtimeꢀtras followingꢀtheꢀexecutionꢀofꢀanꢀactiveꢀcommandꢀ
toꢀ theꢀ sameꢀ bank.ꢀTheꢀ selectedꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ
stateꢀatꢀaꢀtimeꢀtrpꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀprechargeꢀ
command,ꢀandꢀanꢀactiveꢀcommandꢀcanꢀbeꢀexecutedꢀagainꢀ
forꢀthatꢀbank.
UsingꢀtheꢀPrechargeꢀCommand
Aꢀreadꢀcycleꢀcanꢀbeꢀinterruptedꢀbyꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀcommandꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀTheꢀ
delayꢀtimeꢀ(trql)ꢀfromꢀtheꢀexecutionꢀofꢀtheꢀprechargeꢀ
commandꢀtoꢀtheꢀcompletionꢀofꢀtheꢀburstꢀoutputꢀisꢀtheꢀ
clockꢀcycleꢀofꢀCASꢀlatency.
IfꢀpinꢀA10ꢀisꢀlowꢀwhenꢀthisꢀcommandꢀisꢀexecuted,ꢀtheꢀbankꢀ
selectedꢀbyꢀpinꢀA11ꢀwillꢀbeꢀprecharged,ꢀandꢀifꢀpinꢀA10ꢀisꢀ
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprechargedꢀatꢀtheꢀsameꢀtime.ꢀThisꢀ
inputꢀtoꢀpinꢀA11ꢀisꢀignoredꢀinꢀtheꢀlatterꢀcase.
ꢀ
CASꢀLatencyꢀ
3ꢀ
2
ꢀ
trqlꢀ
3ꢀ
2
CLK
tRQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
RQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
31
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀInterruptionꢀUsingꢀtheꢀ
PrechargeꢀCommand
Aꢀwriteꢀcycleꢀcanꢀbeꢀinterruptedꢀbyꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀ commandꢀ beforeꢀ thatꢀ cycleꢀ completes.ꢀTheꢀ
delayꢀtimeꢀ(twDl)ꢀfromꢀtheꢀprechargeꢀcommandꢀtoꢀtheꢀpointꢀ
whereꢀburstꢀinputꢀisꢀinvalid,ꢀi.e.,ꢀtheꢀpointꢀwhereꢀinputꢀdataꢀ
isꢀnoꢀlongerꢀwrittenꢀtoꢀdeviceꢀinternalꢀmemoryꢀisꢀzeroꢀclockꢀ
cyclesꢀregardlessꢀofꢀtheꢀCAS.
Inversely,ꢀtoꢀwriteꢀallꢀtheꢀburstꢀdataꢀtoꢀtheꢀdevice,ꢀtheꢀ
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀafterꢀtheꢀwriteꢀ
dataꢀrecoveryꢀperiodꢀ(tDpl)ꢀhasꢀelapsed.ꢀTherefore,ꢀtheꢀ
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀonꢀoneꢀclockꢀ
cycleꢀthatꢀfollowsꢀtheꢀinputꢀofꢀtheꢀlastꢀburstꢀdataꢀitem.
Toꢀinhibitꢀinvalidꢀwrite,ꢀtheꢀDQMꢀsignalꢀmustꢀbeꢀassertedꢀ
HIGHꢀwithꢀtheꢀprechargeꢀcommand.
ꢀ
CASꢀLatencyꢀ
3ꢀ
2
ꢀ
ꢀ
twDlꢀ
0ꢀ
0
Thisꢀprechargeꢀcommandꢀandꢀburstꢀwriteꢀcommandꢀmustꢀ
beꢀofꢀtheꢀsameꢀbank,ꢀotherwiseꢀitꢀisꢀnotꢀprechargeꢀinterruptꢀ
butꢀonlyꢀanotherꢀbankꢀprechargeꢀofꢀdualꢀbankꢀoperation.
tDplꢀ
2ꢀ
2
CLK
tWDL=0
PRE 0
COMMAND
WRITE A0
DQM
DQ
DIN A0
DIN A1
DIN A2
DIN A3
MASKED BY DQM
PRECHARGE (BANK 0)
WRITE (CA=A, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
DPL
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
D
IN A1
D
IN A2
DIN A3
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
32ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ(FullꢀPage)ꢀInterruptionꢀUsingꢀ
theꢀBurstꢀStopꢀCommand
TheꢀIS42VS16100Eꢀcanꢀoutputꢀdataꢀcontinuouslyꢀfromꢀ
theꢀ burstꢀ startꢀ addressꢀ (a)ꢀ toꢀ locationꢀ a+255ꢀ duringꢀ aꢀ
readꢀcycleꢀinꢀwhichꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀfullꢀpage.ꢀ
Theꢀ IS42VS16100Eꢀ repeatsꢀ theꢀ operationꢀ startingꢀ atꢀ
theꢀ256thꢀcycleꢀwithꢀtheꢀdataꢀoutputꢀreturningꢀtoꢀlocationꢀ
(a)ꢀandꢀcontinuingꢀwithꢀa+1,ꢀa+2,ꢀa+3,ꢀetc.ꢀAꢀburstꢀstopꢀ
commandꢀ mustꢀ beꢀ executedꢀ toꢀ terminateꢀ thisꢀ cycle.ꢀ Aꢀ
prechargeꢀcommandꢀmustꢀbeꢀexecutedꢀwithinꢀtheꢀACTꢀ
toꢀPREꢀcommandꢀperiodꢀ(trasꢀmax.)ꢀfollowingꢀtheꢀburstꢀ
stopꢀcommand.ꢀꢀ
Afterꢀtheꢀperiodꢀ(trbD)ꢀrequiredꢀforꢀburstꢀdataꢀoutputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀimpedanceꢀ
state.ꢀThisꢀperiodꢀ(trbD)ꢀisꢀtwoꢀclockꢀcycleꢀwhenꢀtheꢀ
CASꢀlatencyꢀisꢀtwoꢀandꢀthreeꢀclockꢀcycleꢀwhenꢀtheꢀCASꢀ
latencyꢀisꢀthree.
ꢀ
CASꢀLatencyꢀ
3ꢀ
2
ꢀ
trbDꢀ
3ꢀ
2
CLK
tRBD
BST
COMMAND
DQ
READ A0
D
OUT A0
DOUT A0
D
OUT A1
D
OUT A2
DOUT A3
HI-Z
BURST STOP
READ (CA=A, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
RBD
BST
COMMAND
DQ
READ A0
DOUT A0
D
OUT A0
D
OUT A2
D
OUT A3
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
BURST STOP
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
33
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ(FullꢀPage)ꢀInterruptionꢀUsingꢀ
theꢀBurstꢀStopꢀCommand
mustꢀbeꢀexecutedꢀwithinꢀtheꢀACTꢀtoꢀPREꢀcommandꢀ
periodꢀ(trasꢀmax.)ꢀfollowingꢀtheꢀburstꢀstopꢀcommand.ꢀ
Afterꢀtheꢀperiodꢀ(twbD)ꢀrequiredꢀforꢀburstꢀdataꢀꢀinputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀwriteꢀcycleꢀterminates.ꢀThisꢀperiodꢀ
(twbD)ꢀisꢀzeroꢀclockꢀcycles,ꢀregardlessꢀofꢀtheꢀCASꢀ
latency.ꢀ
TheꢀIS42VS16100Eꢀcanꢀinputꢀdataꢀcontinuouslyꢀfromꢀ
theꢀburstꢀstartꢀaddressꢀ(a)ꢀtoꢀlocationꢀa+255ꢀduringꢀaꢀ
writeꢀcycleꢀinꢀwhichꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀfullꢀpage.ꢀ
TheꢀIS42VS16100Eꢀrepeatsꢀtheꢀoperationꢀstartingꢀatꢀ
theꢀ256thꢀcycleꢀwithꢀdataꢀinputꢀreturningꢀtoꢀlocationꢀ(a)ꢀ
andꢀcontinuingꢀwithꢀa+1,ꢀa+2,ꢀa+3,ꢀetc.ꢀAꢀburstꢀstopꢀ
commandꢀmustꢀbeꢀexecutedꢀtoꢀterminateꢀthisꢀcycle.ꢀAꢀ
prechargeꢀcommandꢀ
CLK
t
WBD=0
BST
INVALID DATA
tRP
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
DIN A1
DIN
A
DIN A1
DIN A2
READ (CA=A, BANK 0)
BURST STOP PRECHARGE (BANK 0)
Don't Care
BurstꢀDataꢀInterruptionꢀUsingꢀtheꢀU/LDQMꢀ
Pinsꢀ(ReadꢀCycle)
outputꢀ controlꢀ operatesꢀ independentlyꢀ onꢀ aꢀ byteꢀ basisꢀ
withꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀoutputꢀ(pinsꢀ
DQ8-DQ15)ꢀ andꢀ theꢀ LDQMꢀ pinꢀ controllingꢀ lowerꢀ byteꢀ
outputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
Burstꢀdataꢀoutputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(masked)ꢀ
duringꢀaꢀreadꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀofꢀ
theꢀCASꢀlatency,ꢀtwoꢀclockꢀcyclesꢀ(tqmD)ꢀafterꢀoneꢀofꢀtheꢀ
U/LDQMꢀpinsꢀgoesꢀHIGH,ꢀtheꢀcorrespondingꢀoutputsꢀgoꢀ
toꢀtheꢀHIGHꢀimpedanceꢀstate.ꢀSubsequently,ꢀtheꢀoutputsꢀ
areꢀmaintainedꢀinꢀtheꢀhighꢀimpedanceꢀstateꢀasꢀlongꢀasꢀ
thatꢀU/LDQMꢀpinꢀremainsꢀHIGH.ꢀWhenꢀtheꢀU/LDQMꢀpinꢀ
goesꢀLOW,ꢀoutputꢀisꢀresumedꢀatꢀaꢀtimeꢀtqmDꢀlater.ꢀThisꢀ
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀoutputꢀbuffersꢀ
only,ꢀtheꢀreadꢀcycleꢀcontinuesꢀinternallyꢀand,ꢀinꢀparticular,ꢀ
incrementingꢀofꢀtheꢀinternalꢀburstꢀcounterꢀcontinues.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
HI-Z
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
34ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
BurstꢀDataꢀInterruptionꢀU/LDQMꢀPinsꢀ(Writeꢀ
Cycle)
Burstꢀdataꢀinputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(mutedꢀ)ꢀ
duringꢀaꢀwriteꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀ
ofꢀtheꢀCASꢀlatency,ꢀasꢀsoonꢀasꢀoneꢀofꢀtheꢀU/LDQMꢀpinsꢀ
goesꢀHIGH,ꢀtheꢀcorrespondingꢀexternallyꢀappliedꢀinputꢀ
dataꢀwillꢀnoꢀlongerꢀbeꢀwrittenꢀtoꢀtheꢀdeviceꢀinternalꢀcircuits.ꢀ
Subsequently,ꢀtheꢀcorrespondingꢀinputꢀcontinuesꢀtoꢀbeꢀ
mutedꢀasꢀlongꢀasꢀthatꢀU/LDQMꢀpinꢀremainsꢀHIGH.
thatꢀpinꢀisꢀdroppedꢀtoꢀLOWꢀandꢀdataꢀwillꢀbeꢀwrittenꢀtoꢀtheꢀ
device.Thisꢀinputꢀcontrolꢀoperatesꢀindependentlyꢀonꢀaꢀbyteꢀ
basisꢀwithꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀinputꢀ(pinꢀ
DQ8ꢀtoꢀDQ15)ꢀandꢀtheꢀLDQMꢀpinꢀcontrollingꢀtheꢀlowerꢀ
byteꢀinputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀinputꢀbuffersꢀ
only,ꢀ theꢀ cycleꢀ continuesꢀ internallyꢀ and,ꢀ inꢀ particular,ꢀ
incrementingꢀofꢀtheꢀinternalꢀburstꢀcounterꢀcontinues.
TheꢀIS42VS16100Eꢀwillꢀrevertꢀtoꢀacceptingꢀinputꢀasꢀsoonꢀ
asꢀ
CLK
COMMAND
UDQM
WRITE A0
t
DMD=0
LDQM
DQ8-DQ15
DQ0-DQ7
DIN A1
D
IN A3
DIN A2
D
IN A0
DIN A3
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
Don't Care
DATA MASK (UPPER BYTE)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
BurstꢀReadꢀandꢀSingleꢀWrite
Theꢀburstꢀreadꢀandꢀsingleꢀwriteꢀmodeꢀisꢀsetꢀupꢀusingꢀtheꢀ
modeꢀregisterꢀsetꢀcommand.ꢀDuringꢀthisꢀoperation,ꢀtheꢀburstꢀ
readꢀcycleꢀoperatesꢀnormally,ꢀbutꢀtheꢀwriteꢀcycleꢀonlyꢀwritesꢀ
aꢀsingleꢀdataꢀitemꢀforꢀeachꢀwriteꢀcycle.ꢀTheꢀCASꢀlatencyꢀ
andꢀDQMꢀlatencyꢀareꢀtheꢀsameꢀasꢀinꢀnormalꢀmode.
CLK
COMMAND
DQ
WRITE A0
D
IN A0
WRITE (CA=A, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀ3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
35
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
BankꢀActiveꢀCommandꢀInterval
thatꢀbankꢀwithinꢀtheꢀACTꢀtoꢀPREꢀcommandꢀperiodꢀ(trasꢀmax).ꢀ
Alsoꢀnoteꢀthatꢀaꢀprechargeꢀcommandꢀcannotꢀbeꢀexecutedꢀ
forꢀanꢀactiveꢀbankꢀbeforeꢀtrasꢀ(min)ꢀhasꢀelapsed.
Whenꢀtheꢀselectedꢀbankꢀisꢀprecharged,ꢀtheꢀperiodꢀtrpꢀ
hasꢀelapsedꢀandꢀtheꢀbankꢀhasꢀenteredꢀtheꢀidleꢀstate,ꢀ
theꢀbankꢀcanꢀbeꢀactivatedꢀbyꢀexecutingꢀtheꢀactiveꢀ
command.ꢀIfꢀtheꢀotherꢀbankꢀisꢀinꢀtheꢀidleꢀstateꢀatꢀthatꢀ
time,ꢀtheꢀactiveꢀcommandꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbankꢀ
afterꢀtheꢀperiodꢀtrrDꢀhasꢀelapsed.ꢀAtꢀthatꢀpointꢀbothꢀ
banksꢀwillꢀbeꢀinꢀtheꢀactiveꢀstate.ꢀWhenꢀaꢀbankꢀactiveꢀ
commandꢀhasꢀbeenꢀexecuted,ꢀaꢀprechargeꢀcommandꢀ
mustꢀbeꢀexecutedꢀforꢀ
Afterꢀ aꢀ bankꢀ activeꢀ commandꢀ hasꢀ beenꢀ executedꢀ andꢀ
theꢀtrcdꢀperiodꢀhasꢀelapsed,ꢀreadꢀwriteꢀ(includingꢀauto-
precharge)ꢀcommandsꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbank.
CLK
t
RRD
COMMAND
ACT 0
ACT 1
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
CLK
COMMAND
t
RCD
ACT 0
READ 0
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
CASꢀlatencyꢀ=ꢀ3
ClockꢀSuspend
WhenꢀtheꢀCKEꢀpinꢀisꢀdroppedꢀfromꢀHIGHꢀtoꢀLOWꢀduringꢀ
aꢀ readꢀ orꢀ writeꢀ cycle,ꢀ theꢀ IS42VS16100Eꢀ entersꢀ clockꢀ
suspendꢀmodeꢀonꢀtheꢀnextꢀCLKꢀrisingꢀedge.Thisꢀcommandꢀ
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀrecoveryꢀ
periodꢀ(tcka)ꢀhasꢀelapsed.
Sinceꢀthisꢀcommandꢀdiffersꢀfromꢀtheꢀself-refreshꢀcommandꢀ
describedꢀpreviouslyꢀinꢀthatꢀtheꢀrefreshꢀoperationꢀisꢀnotꢀ
performedꢀautomaticallyꢀinternally,ꢀtheꢀrefreshꢀoperationꢀ
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tref).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀclockꢀsuspendꢀmodeꢀcanꢀbeꢀheldꢀ
isꢀjustꢀunderꢀtheꢀrefreshꢀcycleꢀtime.
reducesꢀ theꢀ deviceꢀ powerꢀ dissipationꢀ byꢀ stoppingꢀ theꢀ
deviceꢀinternalꢀclock.ꢀClockꢀsuspendꢀmodeꢀcontinuesꢀasꢀ
longꢀasꢀtheꢀCKEꢀpinꢀremainsꢀlow.ꢀInꢀthisꢀstate,ꢀallꢀinputsꢀ
otherꢀthanꢀCKEꢀpinꢀareꢀinvalidꢀandꢀnoꢀotherꢀcommandsꢀ
canꢀ beꢀ executed.ꢀ Also,ꢀ theꢀ deviceꢀ internalꢀ statesꢀ areꢀ
maintained.ꢀWhenꢀtheꢀCKEꢀpinꢀgoesꢀfromꢀLOWꢀtoꢀHIGHꢀ
clockꢀsuspendꢀmodeꢀisꢀterminatedꢀonꢀtheꢀnextꢀCLKꢀrisingꢀ
edgeꢀandꢀdeviceꢀoperationꢀresumes.
CLK
CKE
COMMAND
DQ
READ 0
D
OUT
0
DOUT
1
DOUT
2
DOUT 3
READ (BANK 0)
CLOCK SUSPEND
CAS latencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
36ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
OPERATIONꢀTIMINGꢀEXAMPLE
Power-OnꢀSequence,ꢀModeꢀRegisterꢀSetꢀCycle
T0
T1
T2
T3
T10
T17
T18
T19
T20
CLK
t
CHI
tCK
tCL
HIGH
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
ROW
CODE
CODE
CODE
A0-A9
A10
t
t
AS
AS
tAH
t
AS
tAH
ROW
BANK 0 & 1
t
AH
BANK 1
A11
BANK 0
HIGH
DQM
DQ
WAIT TIME
T=100 µs
t
RAS
t
MCD
tRP
t
RC
tRC
t
RC
Undefined
Don't Care
CASꢀlatencyꢀ=ꢀ2,ꢀ3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
37
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
Power-DownꢀModeꢀCycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
t
CHI
t
CKH
tCKS
tCK
t
CL
tCKS
CKE
CS
t
CKA
t
CKA
tCS
tCH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
ROW
A0-A9
A10
t
AS
tAH
BANK 0 & 1
BANK 0 OR 1
BANK 1
ROW
BANK 1
A11
BANK 0
BANK 0
DQM
DQ
EXIT
t
RAS
RC
t
RP
POWER DOWN MODE
POWER DOWN MODE
t
<
PRE
>
<SBY>
<ACT>
Undefined
Don't Care
CASꢀlatencyꢀ=ꢀ2,ꢀ3
38ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
Auto-RefreshꢀCycle
T0
T1
T2
T3
Tl
Tm
Tn
Tn+1
CLK
t
CHI
t
CK
tCKS
tCL
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
ROW
A0-A9
A10
t
AS
tAH
ROW
BANK 0 & 1
BANK 1
A11
BANK 0
DQM
DQ
t
RC
t
RAS
RC
t
RP
t
RC
tRC
t
Undefined
Don't Care
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
39
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
Self-RefreshꢀCycle
T0
T1
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
t
CHI
t
CKS
t
CK
tCKS
t
CKS
tCL
CKE
CS
t
CKA
t
CKA
t
CS
t
CH
t
CS
tCH
RAS
t
CS
CS
tCH
CAS
WE
t
t
CH
A0-A9
A10
t
AS
tAH
BANK 0 & 1
A11
DQM
DQ
EXIT
SELF
REFRESH
t
RC
SELF REFRESH MODE
t
RC
t
RP
Undefined
Don't Care
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
40ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
t
AH
t
AS
BANK 1
BANK 1
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
BANK 0
t
CH
t
CS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
RAS
t
RCD
t
CAC
tRQL
t
t
RAS
RC
tRP
t
RC
t
<
PRE>
<
ACT>
<
ACT
>
<READ>
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
41
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀAuto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN m
ROW
ROW
ROW
A0-A9
A10
t
AS
t
AH
AUTO PRE
ROW
t
AH
t
AS
BANK 1
BANK 1
BANK 1
A11
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
tLZ
t
HZ
t
RCD
tRCD
tCAC
t
PQL
t
RAS
t
RAS
RC
t
RP
t
RC
t
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
42ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀFullꢀPage
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263
CLK
t
CHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
tAS
tAH
COLUMN
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
t
AH
t
AS
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
t
CAC
t
RBD
(BANK 0)
t
RP
t
RAS
(BANK 0)
t
RC
(BANK 0)
BST
PRE 0
ACT 0
READ0
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
43
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPing-PongꢀOperationꢀ(BankꢀSwitching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
ROW
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
AS
t
AH
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
BANK 0 OR 1
BANK 1
NO PRE
BANK 0
t
AH
t
AS
BANK 0
BANK 0
BANK 1
tCH
tCS
tQMD
DQM
t
AC
t
AC
t
AC
t
AC
tOH
tOH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
DQ
t
LZ
t
LZ
t
HZ
tHZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
t
CAC
t
CAC
t
RCD
(BANK 1)
t
RCD
(BANK 0)
RAS
(BANK 0)
(BANK 1)
(BANK 1)
t
RP
(BANK 0)
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<
ACT 0>
<ACT1>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<
PRE 0
>
<
ACT 0>
<PRE 1>
<
>
<
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
44ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
ROW
ROW
COLUMN m
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
A10
A11
t
AH
tAS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
tRP
t
t
t
t
<
PRE
>
<
ACT>
<WRIT
>
<ACT>
PALL
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
45
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀAuto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
ROW
ROW
COLUMN m
ROW
A0-A9
t
AS
t
AH
ROW
AUTO PRE
A10
A11
tAH
tAS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
t
CH
DQM
DQ
t
DH
t
DS
DS
t
DH
t
DS
t
DH
tDS
tDH
D
IN m+2
DIN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
t
RP
t
t
t
t
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
46ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀFullꢀPage
T0
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
t
AH
(1)
COLUMN m
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
tAH
t
AS
BANK 0
BANK 0
tCH
tCS
DQM
DQ
t
DH
tDS
t
DS
t
DH
tDS
t
DH
t
DS
tDH
D
IN 0m+2
D
IN 0m
D
IN 0m-1
D
IN 0m
D
IN 0m+1
t
DPL
tRCD
t
RAS
RC
tRP
t
BST
PRE 0
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
47
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPing-PongꢀOperation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCK
t
CL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
t
AS
AUTO PRE
AUTO PRE
t
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
AH
t
AS
BANK 0
BANK 0
BANK 1
tCH
t
CS
DQM
DQ
t
DS
t
DS
tDS
t
DS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
t
DH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
tDPL
t
DPL
t
t
RCD
tRCD
(BANK 1)
(BANK 0)
t
RP
t
RAS
t
RAS
(BANK 0)
(BANK 0)
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<ACT 0
>
<ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1
>
<PRE 0
>
<ACT 0>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
48ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100E
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
tAH
NO PRE
NO PRE
BANK 1
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
tAH
tAS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
tCH
tCS
tQMD
DQM
DQ
tAC
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
tLZ
tHZ
tRCD
tRAS
tCAC
tCAC
tCAC
tRQL
tRP
tRC
<ACT>
<READ>
<READ>
<READ>
<PRE>
READA
PALL
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
49
Rev. 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPageꢀMode;ꢀDataꢀMasking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
NO PRE
CH
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
tQMD
tCS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
tLZ
tLZ
t
HZ
t
HZ
t
RCD
tCAC
t
CAC
t
CAC
t
RQL
tRAS
t
RP
tRC
<ACT>
<READ
>
<
MASK>
<
READ, ENB
>
<
PRE>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
50ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPageꢀMode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
t
AS
t
AH
NO PRE
NO PRE
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
t
AH
BANK 1
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
tCH
t
CS
DQM
DQ
t
DH
t
DS
t
DS
t
DH
tDH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
D
IN
m
D
IN n
D
IN n+1
D
IN
o
D
IN o+1
D
IN m+1
t
RCD
t
DPL
t
RAS
tRP
tRC
<
ACT>
<WRIT
>
<
WRIT>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
51
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPageꢀMode;ꢀDataꢀMasking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 1OR 0
t
AS
t
AH
NO PRE
BANK 1
NO PRE
A10
A11
NO PRE
tAH
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
tCH
DQM
DQ
t
DH
t
DH
tDH
t
DS
t
DS
t
DH
tDS
t
DH
tDS
tDS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
tRCD
t
DPL
tRAS
tRP
t
RC
<
ACT>
<WRIT
>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
52ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀClockꢀSuspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCKS
tCKH
tCL
tCK
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
AUTO PRE
tAH
ROW
A10
A11
NO PRE
BANK 1
tAH
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tAC
tCS
tQMD
DQM
DQ
tAC
tOH
tOH
D
OUT
m
DOUT m+1
tLZ
tHZ
tRCD
tCAC
tRAS
tRAS
tRP
tRC
tRC
<SPND>
<SPND>
<PRE>
<ACT 0>
<READ>
READ A
<ACT >
<PALL>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
53
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀClockꢀSuspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCKS
tCL
tCKH
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 1
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
tDS
tDS
t
DH
tDH
D
IN
m
DIN m+1
t
RCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<ACT
>
<
WRIT, SPND
>
<ACT >
WRITA, SPND
PALL
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
54ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPrechargeꢀTermination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
NO PRE
BANK 1
tAH
t
AS
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
t
CH
tQMD
DQM
DQ
tAC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
t
CAC
t
RQL
RP
tCAC
t
RCD
RAS
RC
tRAS
RC
t
t
t
t
<PRE 0
>
<
READ
>
<
ACT 0>
<
READ 0
>
<ACT >
READA
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
55
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPrechargeꢀTermination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
NO PRE
BANK 1
t
AH
t
AS
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
tCH
BANK 0
CS
tCS
tCH
t
DQM
DQ
t
DH
DS
t
DH
DS
t
DH
tDH
t
DS
t
t
tDS
DIN 0m+2
D
IN 0m+1
D
IN 0m
D
IN 0n
t
RCD
t
RCD
RAS
RC
t
t
RAS
t
t
RP
RC
t
<
PRE 0>
<
WRIT
>
<
ACT 0>
<
WRIT 0
>
<ACT >
WRITA
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
56ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀByteꢀOperation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN m
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
BANK 0 AND 1
BANK 0 OR 1
t
AH
ROW
A10
A11
NO PRE
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
UDQM
tQMD
t
CS
tCH
LDQM
t
AC
t
HZ
tAC
t
AC
tOH
tOH
t
LZ
t
OH
t
LZ
DQ8-15
DOUT
m
D
OUT m+2
DOUT m+3
t
AC
t
AC
t
OH
tOH
t
LZ
D
OUT m+1
DOUT m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
RAS
RC
t
RAS
t
RP
t
t
RC
t
<
PRE>
<
ACT>
<
READ
READA
>
<
MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
57
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀByteꢀOperation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
tAH
ROW
A10
A11
NO PRE
tAH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tCS
UDQM
tCS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
tDH
t
DH
t
DS
DH
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
tDS
t
DH
t
DS
tDH
D
IN
DIN m+3
t
RCD
t
DPL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<ENB>
<
>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
58ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycle,ꢀWriteꢀCycleꢀ/ꢀBurstꢀRead,ꢀSingleꢀWrite
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
t
AS
tAH
COLUMN m
COLUMN n
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
AUTO PRE
t
AH
NO PRE
BANK 1
A10
A11
NO PRE
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
DS
t
OH
t
OH
t
OH
tOH
t
DH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
DIN
n
t
LZ
t
HZ
t
RCD
t
CAC
tDPL
t
RAS
RC
tRP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<ACT>
<READ>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
59
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AH
NO PRE
BANK 1
ROW
ROW
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
tCS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
t
RCD
t
CAC
t
RQL
t
RAS
t
RAS
RC
t
RP
tRC
t
<
PRE>
<
ACT>
<READ>
<ACT>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
60ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀAuto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN
ROW
ROW
ROW
A0-A9
A10
AUTO PRE
t
AS
tAH
ROW
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
A11
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
tLZ
t
HZ
t
RCD
RAS
t
RCD
tCAC
t
PQL
RP
t
t
RAS
RC
t
t
RC
t
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
61
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀFullꢀPage
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN
ROW
ROW
A0-A9
t
AS
t
AH
NO PRE
A10
A11
BANK 0 OR 1
BANK 0
tAH
t
AS
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
(BANK 0)
RAS
(BANK 0)
t
CAC
tRBD
(BANK 0)
t
RP
t
(BANK 0)
t
RC
(BANK 0)
BST
PRE 0
ACT 0
READ0
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
62ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPingꢀPongꢀOperationꢀ(BankꢀSwitching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CAS
WE
CS
t
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
COLUMN
ROW
ROW
ROW
A0-A9
AUTO PRE
AUTO PRE
t
AS
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
AS
BANK 0
BANK 0
BANK 1
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
t
CAC
t
RCD
t
HZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
(BANK 1)
(BANK 1)
t
CAC
t
t
RQL
(BANK 0)
RP
(BANK 0)
t
RCD
(BANK 0)
RAS
(BANK 0)
(BANK 0)
t
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<ACT 0>
<
ACT1>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<
PRE 0>
<
PRE 1>
<
ACT 0>
<
>
<
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
63
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycle
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
tCHI
t
CKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
A10
A11
tAH
t
AS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
tCH
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
t
RP
t
t
t
t
<
PRE
>
<ACT>
<
WRIT>
<ACT>
PALL
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
64ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀAuto-Precharge
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
A10
AUTO PRE
t
AS
tAH
ROW
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
t
CS
t
t
CH
DQM
DQ
t
DH
tDS
DS
t
DH
t
DS
t
DH
t
DS
tDH
D
IN
m
DIN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
t
RP
t
t
t
t
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
65
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀFullꢀPage
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
COLUMN
NO PRE
BANK 0
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
BANK 0 OR 1
BANK 0
t
AH
t
AS
BANK 0
t
CH
t
CS
DQM
DQ
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN 0m
D
IN 0m+2
D
IN 0m-1
D
IN 0m
D
IN 0m+1
tRCD
tDPL
t
RAS
RC
tRP
t
BST
PRE 0
ACT 0
WRIT0
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
66ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPing-PongꢀOperationꢀ(BankꢀSwitching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
ROW
COLUMN
COLUMN
A0-A9
t
AS
AUTO PRE
AUTO PRE
t
AH
ROW
A10
A11
NO PRE
BANK 1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
tAH
t
AS
BANK 0
BANK 1
BANK 0
BANK 1
tCH
t
CS
DQM
DQ
tDS
t
DS
t
DS
t
DS
t
DS
tDS
tDS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
DPL
tDPL
(BANK 0)
t
t
RCD
t
RCD
RAS
RC
(BANK 1)
t
RP
t
RAS
t
(BANK 0)
(BANK 0)
t
RC
t
(BANK 0)
tRAS
(BANK 1)
t
RC
(BANK 1)
<ACT 0
>
<
ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1
>
<PRE 0
>
<ACT 0>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
67
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPageꢀMode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
tAS
tAH
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
BANK 1
NO PRE
NO PRE
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
t
CAC
t
HZ
t
CAC
t
RCD
t
CAC
t
t
RQL
RP
t
RAS
tRC
<
ACT>
<
READ>
<
READ>
<
READ
>
<
PRE>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
68ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPageꢀMode;ꢀDataꢀMasking
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
NO PRE
NO PRE
t
AH
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
tCH
tQMD
tCS
tQMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
tLZ
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
HZ
t
CAC
t
CAC
tRCD
tCAC
t
RQL
t
RAS
tRP
t
RC
<
ACT>
<READ
>
<
READ>
<
READ, MASK
>
<ENB>
<
PRE
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
69
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPageꢀMode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
COLUMN n
COLUMN o
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
AUTO PRE
t
AH
ROW
NO PRE
BANK 1
NO PRE
A10
A11
NO PRE
t
AH
BANK 1
t
AS
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
t
DH
t
DS
t
DH
tDH
tDS
t
DH
t
DS
t
DH
tDS
tDS
D
IN
m
D
IN n
D
IN
o
D
IN o+1
D
IN m+1
tRCD
t
DPL
tRAS
tRP
t
RC
<
ACT>
<
WRIT>
<WRIT
>
<MASK
>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
70ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100E
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 1OR 0
tAS
tAH
ROW
NO PRE
NO PRE
NO PRE
tAH
BANK 1
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CS
tCH
DQM
DQ
t
DH
t
DH
t
DH
t
DS
tDS
t
DH
t
DS
t
DH
tDS
tDS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
t
RCD
t
DPL
t
RAS
tRP
t
RC
<
ACT>
<WRIT
>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
71
Rev. 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀClockꢀSuspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CKS
tCKH
tCL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
t
AH
(1)
COLUMN m
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
tAS
AUTO PRE
t
AH
NO PRE
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
OH
t
OH
D
OUT
m
D
OUT m+1
t
LZ
t
HZ
t
RCD
tCAC
t
RAS
RC
tRP
t
<
SPND>
<
SPND>
<
PRE
PALL
>
<ACT>
<
READ
>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
72ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀClockꢀSuspend
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCKS
tCKH
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
ROW
NO PRE
BANK 1
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CH
tCS
DQM
DQ
t
DS
tDS
t
DH
tDH
D
IN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<
ACT
>
<
WRIT, SPND
>
<ACT >
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
73
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀPrechargeꢀTermination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
AS
t
AH
ROW
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
t
AH
t
AS
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
t
CAC
t
RQL
RP
t
RCD
RAS
RP
t
RAS
RC
t
t
t
t
<
PRE 0>
ACT 0
READ 0
ACT
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
74ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀPrechargeꢀTermination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN m
ROW
ROW
A0-A9
A10
t
AS
tAH
ROW
ROW
BANK 0 OR 1
BANK 0
NO PRE
tAH
t
AS
BANK 1
BANK 0
BANK 0
A11
t
CS
BANK 0
t
CS
t
CH
t
CH
DQM
DQ
t
DH
DS
t
DH
DS
tDH
t
DS
t
t
DIN 0m+2
D
IN 0m+1
D
IN 0m
tRCD
tRCD
t
RAS
t
RAS
tRP
tRC
tRP
ACT
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
75
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycleꢀ/ꢀByteꢀOperation
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CAS
WE
t
CS
t
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
AS
AUTO PRE
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
tCH
t
CS
t
QMD
QMD
UDQM
t
t
CS
t
CH
LDQM
t
AC
tHZ
tAC
t
AC
t
HZ
t
OH
t
LZ
t
OH
t
LZ
DQ8-15
DOUT
m
D
OUT m+2
D
OUT m+3
t
AC
t
AC
t
HZ
t
LZ
t
OH
tOH
DOUT m+1
D
OUT
m
DQ0-7
t
RCD
t
CAC
tQMD
t
RQL
RP
t
RCD
RAS
RP
t
RAS
RC
t
t
t
t
<
PRE>
<ACT>
<
READ
READA
>
<
MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
76ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
WriteꢀCycleꢀ/ꢀByteꢀOperation
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
tCH
UDQM
t
CS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
DH
tDH
t
DH
t
DS
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
D
IN m+3
t
RCD
t
DPL
t
RCD
RAS
RP
t
RAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<
ENB>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
77
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ReadꢀCycle,ꢀWriteꢀCycleꢀ/ꢀBurstꢀRead,ꢀSingleꢀWrite
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CAS
WE
t
CS
t
t
AS
AS
t
AH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
AUTO PRE
t
AH
AH
NO PRE
BANK 1
NO PRE
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
DS
t
OH
t
OH
t
DH
D
OUT
m
D
OUT m+1
DIN
n
t
LZ
t
HZ
tRC
tCAC
t
DPL
t
RAS
RC
t
RP
t
<
WRIT
>
<
PRE
>
<
ACT>
<
READ>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
78ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
ORDERINGꢀINFORMATION
CommercialꢀRange:ꢀ0°Cꢀtoꢀ+70°C
ꢀ
Frequencyꢀ
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
ꢀ
133ꢀMHzꢀ
ꢀ
7.5ꢀ
ꢀ
IS42VS16100E-75TLꢀ
IS42VS16100E-75BLꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-free
ꢀ
ꢀ
100ꢀMHzꢀ
ꢀ
10ꢀ
ꢀ
IS42VS16100E-10TLꢀ
IS42VS16100E-10BLꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-free
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°C
ꢀ
Frequencyꢀ
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
ꢀ
133ꢀMHzꢀ
ꢀ
7.5ꢀ
ꢀ
IS42VS16100E-75TLIꢀ
IS42VS16100E-75BLIꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-free
ꢀ
ꢀ
100ꢀMHzꢀ
ꢀ
10ꢀ
ꢀ
IS42VS16100E-10TLIꢀ
IS42VS16100E-10BLIꢀ
400-milꢀTSOPꢀII,ꢀLead-freeꢀ ꢀ
60-ballꢀBGA,ꢀLead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
79
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
80ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.ꢀ 00E
01/21/2011
IS42VS16100Eꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
81
Rev.ꢀ 00E
01/21/2011
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