IS42VS16100F-75BL [ISSI]
Synchronous DRAM, 1MX16, 6ns, CMOS, PBGA60, 10.10 X 6.40 MM, 0.65 MM PITCH, LEAD FREE, TFBGA-60;
| 型号： | IS42VS16100F-75BL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 1MX16, 6ns, CMOS, PBGA60, 10.10 X 6.40 MM, 0.65 MM PITCH, LEAD FREE, TFBGA-60 动态存储器 |
| 文件： | 总86页 (文件大小：1568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42/45S16100F, IS42VS16100F
512K Words x 16 Bits x 2 Banks
16Mb SDRAM
JUNE 2012
FEATURES
DESCRIPTION
•ꢀ Clockꢀfrequency:ꢀ
ISSI’sꢀ16MbꢀSynchronousꢀDRAMꢀIS42S16100F,ꢀ
IS45S16100FꢀandꢀIS42VS16100Fꢀareꢀeachꢀorganizedꢀ
asꢀaꢀ524,288-wordꢀxꢀ16-bitꢀxꢀ2-bankꢀforꢀimprovedꢀ
performance.ꢀTheꢀsynchronousꢀDRAMsꢀachieveꢀhigh-
speedꢀdataꢀtransferꢀusingꢀpipelineꢀarchitecture.ꢀAllꢀ
inputsꢀandꢀoutputsꢀsignalsꢀreferꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀ
clockꢀinput.
ꢀ IS42/45S16100F:ꢀ200,ꢀ166,ꢀ143ꢀMHzꢀ
IS42VS16100F:ꢀ133,ꢀ100ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positiveꢀclockꢀedge
•ꢀ Twoꢀbanksꢀcanꢀbeꢀoperatedꢀsimultaneouslyꢀandꢀ
independently
ADDRESS TABLE
Parameter
•ꢀ DualꢀinternalꢀbankꢀcontrolledꢀbyꢀA11ꢀꢀ
(bankꢀselect)
IS42/45S16100F IS42VS16100F
PowerꢀSupplyꢀVdd/Vddq
RefreshꢀCount
3.3V
1.8V
•ꢀ Singleꢀpowerꢀsupply:ꢀ
2K/32ms
2K/32ms
IS42/45S16100F:ꢀVdd/Vddqꢀ=ꢀ3.3V
IS42VS16100F:ꢀVdd/Vddqꢀ=ꢀ1.8V
RowꢀꢀAddressing
ColumnꢀAddressing
BankꢀAddressing
PrechargeꢀAddressing
A0-A10
A0-A7
A11
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
A10
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ
Sequential/Interleave
KEY TIMING PARAMETERS
•ꢀ 2048ꢀrefreshꢀcyclesꢀeveryꢀ32ꢀms
Parameter
-5(1)
-6(2) -7 (2) -75 (3) -10 (3) Unit
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
CLK Frequency
CAS Latency = 3
CAS Latency = 2
5
6
7
7.5
10
10
12
ns
ns
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ
operationsꢀcapability
10
10
10
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀꢀ
prechargeꢀcommand
200 166 143
100 100 100
133
100
100 Mhz
83
Mhz
•ꢀ ByteꢀcontrolledꢀbyꢀLDQMꢀandꢀUDQM
Access Time from
Clock
•ꢀ Packagesꢀ400-milꢀ50-pinꢀTSOP-IIꢀandꢀ60-ballꢀ
BGA
CAS Latency = 3
CAS Latency = 2
5
6
5.5
6
5.5
6
6
8
7
8
ns
ns
•ꢀ Lead-freeꢀpackageꢀoption
•ꢀ AvailableꢀinꢀIndustrialꢀꢀTemperature
Notes:
1. Available for IS42S16100F only
2. Available for IS42S16100F and IS45S16100F only
3. Available for IS42VS16100F only
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀ
latestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
1
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
UDQM
CLK
CKE
NC
CAS
RAS
CS
A11
A9
A10
A8
A0
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
AddressꢀInput
CAS ꢀ
WEꢀ
ColumnꢀAddressꢀStrobeꢀCommand
WriteꢀEnable
A0-A10ꢀ ꢀ
RowꢀAddressꢀInput
BankꢀSelectꢀAddress
ColumnꢀAddressꢀInput
DataꢀDQ
A11ꢀꢀ
ꢀ
ꢀ
LDQMꢀ LowerꢀBye,ꢀInput/OutputꢀMask
UDQMꢀ UpperꢀBye,ꢀInput/OutputꢀMask
A0-A7ꢀ
DQ0ꢀtoꢀDQ15ꢀ
VDDꢀ
VSSꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
Ground
VDDQꢀ PowerꢀSupplyꢀforꢀDQꢀPin
VSSQꢀ GroundꢀforꢀDQꢀPin
ChipꢀSelect
RASꢀ
RowꢀAddressꢀStrobeꢀCommand
NCꢀ
NoꢀConnection
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
PIN CONFIGURATION
PACKAGEꢀCODE:ꢀBꢀꢀ60ꢀBALLꢀTF-BGAꢀ(TopꢀView)ꢀ(10.1ꢀmmꢀxꢀ6.4ꢀmmꢀBody,ꢀ0.65ꢀmmꢀBallꢀPitch)
1 2 3 4 5 6 7
A
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8 NC
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ DQ6
B
C
D
E
F
G
H
J
NC
DQ7
NC
NC
NC UDQM
NC CLK
CKE NC
NC
VDD
LDQM WE
K
L
CAS
CS
RAS
NC
NC
A0
M
N
P
R
A11
A8
A9
A7
A5
A4
NC
A10
A1
A6
A2
VSS
VDD
A3
PIN DESCRIPTIONS
A0-A10ꢀ ꢀ
RowꢀAddressꢀInput
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
WEꢀ
ꢀ
WriteꢀEnable
A0-A7ꢀ
A11ꢀ
ꢀ
ꢀ
LDQM,ꢀUDQMꢀ x16ꢀInput/OutputꢀMask
Vddꢀ
Vssꢀ
Vddqꢀ
Vssqꢀ
NCꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power
DQ0ꢀtoꢀDQ15ꢀ
Ground
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
NoꢀConnection
ChipꢀSelect
RASꢀ
CAS
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
3
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
PIN FUNCTIONS
Pin No.
Symbol
Type
Function (In Detail)
ꢀ
ꢀ
20ꢀtoꢀ24ꢀ
27ꢀtoꢀ32ꢀ
A0-A10ꢀ
ꢀ
InputꢀPinꢀ
ꢀ
A0ꢀtoꢀA10ꢀareꢀaddressꢀinputs.ꢀA0-A10ꢀareꢀusedꢀasꢀrowꢀaddressꢀinputsꢀduringꢀactive
commandꢀinputꢀandꢀA0-A7ꢀasꢀcolumnꢀaddressꢀinputsꢀduringꢀreadꢀorꢀwriteꢀcommandꢀinput.ꢀ
A10ꢀisꢀalsoꢀusedꢀtoꢀdetermineꢀtheꢀprechargeꢀmodeꢀduringꢀotherꢀcommands.ꢀIfꢀA10ꢀisꢀ
LOWꢀduringꢀprechargeꢀcommand,ꢀtheꢀbankꢀselectedꢀbyꢀA11ꢀisꢀprecharged,ꢀbutꢀifꢀA10ꢀisꢀ
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprecharged.ꢀ
WhenꢀA10ꢀisꢀHIGHꢀinꢀreadꢀorꢀwriteꢀcommandꢀcycle,ꢀtheꢀprechargeꢀstartsꢀautomaticallyꢀ
afterꢀtheꢀburstꢀaccess.ꢀ
TheseꢀsignalsꢀbecomeꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀcommandꢀinput.
ꢀ
19ꢀ
A11ꢀ
InputꢀPinꢀ
A11ꢀisꢀtheꢀbankꢀselectionꢀsignal.ꢀWhenꢀA11ꢀisꢀLOW,ꢀbankꢀ0ꢀisꢀselectedꢀandꢀwhenꢀhigh,ꢀ
bankꢀ1ꢀisꢀselected.ꢀThisꢀsignalꢀbecomesꢀpartꢀofꢀtheꢀOPꢀCODEꢀduringꢀmodeꢀregisterꢀsetꢀ
commandꢀinput.
ꢀ
ꢀ
16ꢀ
34ꢀ
CASꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CAS,ꢀinꢀconjunctionꢀwithꢀtheꢀRASꢀandꢀꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ
“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
CKEꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀWhenꢀisꢀ
CKEꢀHIGH,ꢀtheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalid,ꢀandꢀwhenꢀLOW,ꢀinvalid.ꢀ
WhenꢀCKEꢀisꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀtheꢀpower-downꢀmode,ꢀtheꢀclockꢀsuspendꢀ
mode,ꢀorꢀtheꢀselfꢀrefreshꢀmode.ꢀTheꢀCKEꢀisꢀanꢀasynchronousꢀinput.
ꢀ
ꢀ
35ꢀ
18ꢀ
CLKꢀ
InputꢀPinꢀ
InputꢀPinꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀ
acquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.
CSꢀ
TheꢀCSꢀinputꢀdeterminesꢀwhetherꢀcommandꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀꢀ
ꢀ
CommandꢀinputꢀisꢀenabledꢀwhenꢀCSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀdeviceꢀ
remainsꢀinꢀtheꢀpreviousꢀstateꢀwhenꢀCSꢀisꢀHIGH.
ꢀ
2,ꢀ3,ꢀ5,ꢀ6,ꢀ8,ꢀ9,ꢀ11ꢀ DQ0ꢀtoꢀ
DQꢀPinꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀDQꢀpins.ꢀDQꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
ꢀ 12,ꢀ39,ꢀ40,ꢀ42,ꢀ43,ꢀ
DQ15ꢀ
ꢀ
45,ꢀ46,ꢀ48,ꢀ49
ꢀ
ꢀ
14,ꢀ36ꢀ
ꢀ
LDQM,ꢀ
UDQMꢀ
InputꢀPinꢀ
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀDQꢀbuffers.ꢀInꢀread
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀꢀ
toꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀOEꢀ
inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀ
LDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀcanꢀbeꢀ
writtenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀandꢀcannotꢀ
beꢀwrittenꢀtoꢀtheꢀdevice.
ꢀ
ꢀ
17ꢀ
15ꢀ
RASꢀ
ꢀWEꢀ
InputꢀPinꢀ
InputꢀPinꢀ
RAS,ꢀinꢀconjunctionꢀwithꢀCASꢀandꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ“Commandꢀ
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀWE,ꢀinꢀconjunctionꢀwithꢀRASꢀandꢀCAS,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ“Commandꢀ
TruthꢀTable”ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
7,ꢀ13,ꢀ38,ꢀ44ꢀ
1,ꢀ25ꢀ
VddQꢀ
Vddꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
PowerꢀSupplyꢀPinꢀ
VddQꢀisꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
Vddꢀisꢀtheꢀdeviceꢀinternalꢀpowerꢀsupply.
VSSQꢀisꢀtheꢀoutputꢀbufferꢀground.
VSSꢀisꢀtheꢀdeviceꢀinternalꢀground.
4,ꢀ10,ꢀ41,ꢀ47ꢀ
26,ꢀ50ꢀ
VSSQꢀ
VSSꢀ
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
MEMORY CELL
ARRAY
ROW
ADDRESS
BUFFER
2048
CLOCK
MODE
REGISTER
BANK 0
11
GENERATOR
11
A11
DQM
DATA IN
BUFFER
11
SENSE AMP I/O GATE
256
16
16
A10
8
SELF
DQ 0-15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
COLUMN DECODER
REFRESH
8
CONTROLLER
256
DATA OUT
BUFFER
SENSE AMP I/O GATE
REFRESH
COUNTER
16
16
MEMORY CELL
ARRAY
VDD/VDDQ
VSS/VSSQ
2048
ROW
ADDRESS
BUFFER
BANK 1
ROW
ADDRESS
LATCH
11
11
11
S16BLK.eps
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
5
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42S16100F ELECTRICAL SPECIFICATIONS
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd maxꢀ
Vddqꢀꢀmax
Vinꢀ
Parameters
Rating
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀ+4.6ꢀ
1ꢀ
Unit
V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
Voutꢀ
OutputꢀVoltageꢀ
V
Pd max
Ics
AllowableꢀPowerꢀDissipationꢀ
outputꢀShortedꢀCurrentꢀ
W
mA
50ꢀ
ꢀ
ꢀ
ꢀ
Topr
ꢀ
ꢀ
operatingꢀTemperatureꢀ
ꢀ
ꢀ
Com.ꢀ
Ind.ꢀ
Automotive,ꢀA1ꢀ
0ꢀtoꢀ+70ꢀ
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+85ꢀ
°Cꢀ
°Cꢀ
°C
ꢀ
ꢀ
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–55ꢀtoꢀ+150ꢀ
°C
(2)
DC RECOMMENDED OPERATING CONDITIONS
Commercial (Ta = 0°C to +70°C), Industrial (Ta = -40°C to +85°C), Automotive, A1 (Ta = -40°C to +85°C)
Symbol
Parameter
Test Condition
Min. Typ.
Max.
Unit
Vdd, Vddqꢀ SupplyꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
3.0ꢀ
2.0ꢀ
-0.3ꢀ
-5ꢀ
3.3ꢀ
3.6ꢀ
V
V
Vihꢀ
Vilꢀ
InputꢀHighꢀVoltage(3)ꢀ
InputꢀLowꢀVoltage(4)ꢀ
—ꢀ Vddq +ꢀ0.3ꢀ
—ꢀ
ꢀ
+0.8ꢀ
5ꢀ
V
iil
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀ≤ꢀVinꢀ≤ꢀVdd,ꢀwithꢀpinsꢀotherꢀthanꢀ
theꢀtestedꢀpinꢀatꢀ0V
µA
iol
OutputꢀLeakageꢀCurrentꢀ Outputꢀisꢀdisabled,ꢀ0Vꢀ≤ꢀVoutꢀ≤ꢀVddꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ ioutꢀ=ꢀ–2ꢀmAꢀ
-5ꢀ
2.4ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
µA
V
Voh
Vol
—ꢀ
0.4ꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ ioutꢀ=ꢀ+2ꢀmAꢀ
V
(1,2)
CAPACITANCE CHARACTERISTICS
(AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVDDꢀ=ꢀVDDQꢀ=ꢀ3.3ꢀ±ꢀ0.3V,ꢀfꢀ=ꢀ1ꢀMHz)
Symbol
Cin1ꢀ
Parameter
Min.
Max.
4.0ꢀ
4.0ꢀ
5.0ꢀ
Unit
ꢀ
ꢀ
ꢀ
InputꢀCapacitance:ꢀCLKꢀ
2.5ꢀ
pF
pF
pF
Cin2ꢀ
InputꢀCapacitance:ꢀ(A0-A11,ꢀCKE, CS, RAS,ꢀCAS,ꢀWE,ꢀLDQM,ꢀUDQM)ꢀ 2.5ꢀ
DataꢀInput/OutputꢀCapacitance:ꢀDQ0-DQ15ꢀ 4.0ꢀ
CI/Oꢀ
Notes:
1.ꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀ
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀ
reliability.
2.ꢀAllꢀvoltagesꢀareꢀreferencedꢀtoꢀVSS.
3.ꢀVihꢀ(max)ꢀ=ꢀVddqꢀ+ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ≤ꢀ3ꢀns.
4. Vil (min) = -1.2V with a pulse width ≤ 3 ns.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42S16100F and IS45S16100F DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
-5
-6
-7
Unit
icc1
Operating Current(1,2)
One Bank Operation, CAS Latency = 3
Burst Length=1
Com.
Ind., A1
120 110 100
mA
mA
—
120 110
trc ≥ trc (min)
Iout = 0mA
icc2p
Precharge Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max) tck = tck (min)
2
2
2
2
2
2
mA
mA
Icc2psꢀ
Precharge Standby Current
(In Power-Down and
Clock Suspend Mode)
ꢀ
CKE ≤ Vil (max)ꢀtckꢀ=ꢀ∞
CLK ≤ Vil (max)
ꢀicc2n
Precharge Standby Current(3) CKE ≥ Vih (min) tck = tck (min)
(In Non Power-Down Mode) CS ≥ Vih (min)
35
20
35
20
35
20
mA
mA
Icc2nsꢀ
Precharge Standby Current
(In Non Power-Down and
Clock Suspend Mode)
CKE ≥ Vih (min) tckꢀ=ꢀ∞ꢀ
CLK ≤ Vil (max) Inputs are stable
ꢀicc3P
Active Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max) tck = tck (min)
3
3
3
3
3
3
mA
mA
Icc3Psꢀ
Active Standby Currentꢀ
(In Power-Down and
CKE ≤ Vil (max) tckꢀ=ꢀ∞ꢀ
CLK ≤ Vil (max) Inputs are stable
Clock Suspend Mode)
ꢀicc3n
Active Standby Current(3) CKE ≥ Vih (min) tck = tck (min)
(In Non Power-Down Mode) CS ≥ Vih (min)
55
30
55
30
55
30
mA
mA
Icc3nsꢀ
Active Standby Current
(In Non Power-Down and
Clock Suspend Mode)
CKE ≥ Vih (min) tckꢀ=ꢀ∞ꢀ
CLK ≤ Vil (max) Inputs are stable
icc4
icc5
Operating Current
(In Burst Mode)(1,3)
Both Banks activated tck = tck (min)
Page Burst
120 110 100
mA
Ioutꢀ= 0mA
Auto-Refresh Current
Self-Refresh Current
trc = trcꢀ(min)
Com.
Ind., A1
120 100
80
90
mA
mA
—
110
icc6
CKE ≤ 0.2V
2
2
2
mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vddꢀand Vss for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
3. Inputs changed once every two clocks.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
7
Rev. A
06/13/2012
35ꢀ
100,000ꢀ
100,000ꢀ
100,000ꢀ
1.ꢀWhenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ100ꢀµsꢀafterꢀVdd andꢀVddq reachꢀtheirꢀstipulatedꢀvoltages.ꢀAlsoꢀnoteꢀthatꢀtheꢀpower-onꢀ
IS42/45S16100F, IS42VS16100F
(1,2,3)
IS42S16100F and IS45S16100F AC CHARACTERISTICS
ꢀ ꢀ
-5
-6
-7
Symbol Parameter
Min. Max.
5ꢀ —ꢀ
10ꢀ ꢀ —ꢀ
Min.
Max.
Min.
Max.
Units
ꢀ tck3ꢀ
ꢀ tck2ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
7ꢀ
10ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ tac3ꢀ
ꢀ tac2ꢀ
AccessꢀTimeꢀFromꢀCLK(4)ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
ns
ns
ꢀ tchiꢀ
ꢀ tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
ꢀ
ꢀ
2ꢀ
2ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ toh3ꢀ
ꢀ toh2ꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.0ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2.0ꢀ
2.5ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
2.5ꢀ ꢀ —ꢀ
ꢀ tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
0ꢀ
ꢀ
—ꢀ
ns
ꢀ thz3ꢀ
ꢀ thz2ꢀ
OutputꢀHIGHꢀImpedanceꢀTime(5)
ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
5.5ꢀ
6ꢀ
ns
ns
ꢀ tdsꢀ
ꢀ tdhꢀ
ꢀ tasꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
CKEꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ tahꢀ
ꢀ tcksꢀ
ꢀ tckhꢀ
ꢀ tckaꢀ
ꢀ tcsꢀ
ꢀ tchꢀ
ꢀ trcꢀ
ꢀ trasꢀ
ꢀ trpꢀ
ꢀ trcdꢀ
ꢀ trrdꢀ
CKEꢀHoldꢀTimeꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3ꢀ —ꢀ
1CLK+3ꢀ —ꢀ
1CLK+3ꢀ —ꢀ
CommandꢀSetupꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ
CommandꢀHoldꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
1ꢀ
1ꢀ
50ꢀ ꢀ —ꢀ
54ꢀ
36ꢀ
18ꢀ
18ꢀ
12ꢀ
63ꢀ
42ꢀ
20ꢀ
20ꢀ
14ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
15ꢀ ꢀ —ꢀ
15ꢀ ꢀ —ꢀ
10ꢀ ꢀ —ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀꢀ
ꢀ tdpl3ꢀ
ꢀ tdpl2ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2CLKꢀꢀ —ꢀ
2CLKꢀꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
2CLKꢀ ꢀ —ꢀ
ns
ns
ꢀ tdal3ꢀ
ꢀ tdal2ꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)ꢀ CAS Latencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
2CLK+trp —ꢀ
ns
ns
ꢀ txsr
ꢀ tt
ExitꢀSelf-RefreshꢀtoꢀActiveꢀTimeꢀ
TransitionꢀTimeꢀ
ꢀ
ꢀ
ꢀ
55ꢀ ꢀ —ꢀ
0.3ꢀ ꢀ 1.2ꢀ
60ꢀ
0.3ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
1.2ꢀ
32ꢀ
70ꢀ
0.3ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
1.2ꢀ
32ꢀ
ns
ns
ꢀ trefꢀ
RefreshꢀCycleꢀTimeꢀ(2048)ꢀ
—ꢀ
ꢀ
32ꢀ
ms
Notes:
ꢀ
sequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2.ꢀmeasuredꢀwithꢀtt =ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tt/2ꢀ-ꢀ0.5)nsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.
3.ꢀTheꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil (max.).
4.ꢀAccessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀthatꢀfollows.
5.ꢀTheꢀtimeꢀthz (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ±ꢀ200ꢀmVꢀfromꢀVoh (min.)ꢀorꢀVolꢀ(max.)ꢀwhenꢀthe
ꢀ
ꢀoutputꢀisꢀinꢀtheꢀhighꢀimpedanceꢀstate.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42S16100F and IS45S16100F OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-5
5ꢀ
-6
6ꢀ
-7
7ꢀ
UNITS
ns
ꢀ
—ꢀ
—ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
OperatingꢀFrequencyꢀ
200ꢀ
166ꢀ
143ꢀ
MHz
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tcacꢀ
trcdꢀ
tracꢀ
trc
CASꢀꢀLatencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
3ꢀ
3ꢀ
3ꢀ
6ꢀ
9ꢀ
6ꢀ
3ꢀ
2ꢀ
1ꢀ
3ꢀ
3ꢀ
6ꢀ
9ꢀ
6ꢀ
3ꢀ
2ꢀ
1ꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(trcdꢀ+ꢀtcac)ꢀ
6ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
10ꢀ
7ꢀ
trasꢀ
trpꢀ
3ꢀ
trrdꢀ
2ꢀ
ꢀ
ꢀ
tccdꢀ
ꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
1ꢀ
ꢀ
tdplꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
2ꢀ
5ꢀ
cycle
cycle
ꢀ
ꢀ
tdalꢀ
ꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)
ꢀ
ꢀ
trbdꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
ꢀ
ꢀ
ꢀ
ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
3ꢀ
0ꢀ
cycle
cycle
cycle
cycle
ꢀ
ꢀ
twbdꢀ
ꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)ꢀ
ꢀ
ꢀ
trqlꢀ
ꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTimeꢀ
(Read)
ꢀ
ꢀ
twdlꢀ
ꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)
ꢀ
ꢀ
ꢀ
ꢀ
tpqlꢀ
tqmdꢀ
tdmdꢀ
tmcdꢀ
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-2ꢀ
2ꢀ
0ꢀ
2ꢀ
–2ꢀ
2ꢀ
–2ꢀ
2ꢀ
cycle
cycle
cycle
cycle
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
0ꢀ
0ꢀ
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
2ꢀ
2ꢀ
AC TEST CONDITIONS (Input/OutputꢀReferenceꢀLevel:ꢀ1.4V)
Output Load
Input
t
CK
t
CL
t
CHI
3.0V
1.4V
50 Ω
CLK
0.0V
+1.4V
t
CS
I/O
t
CH
3.0V
1.4V
0.0V
INPUT
50 pF
t
AC
t
OH
1.4V
1.4V
OUTPUT
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
9
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42VS16100F ELECTRICAL SPECIFICATIONS
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Vddꢀmax
Vddq maxꢀ
Vin
Parameters
Rating
Unit
V
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
–0.5 to +2.6
–0.5 to +2.6
–0.5 to +2.6
V
V
Vout
Pdꢀmaxꢀ
Icsꢀ
Output Voltage
–0.5 to +2.6
V
W
Allowable Power Dissipation
output Shorted Current
operating Temperature
1
50
mA
Toprꢀ
Com
Ind.
0 to +70
-40 to +85
°C
°C
Tstg
Storage Temperature
–55 to +150
°C
(2)
DC RECOMMENDED OPERATING CONDITIONS
Commercial (Ta = 0°C to +70°C), Industrial (Ta = -40°C to +85°C)
Symbol Parameter Test Conditions
Vdd,ꢀVddq Supply Voltage
Min.
Typ.
1.8
—
Max.
Unit
V
V
V
mA
1.7
0.8 x Vddq
-0.3
1.9
Vddqꢀ+ 0.3
+0.3
Vih
Vil
iilꢀ
Input High Voltage(3)
Input Low Voltage(4)
Input Leakage Current
—
0V ≤ Vin ≤ Vdd, with pins other than
-1.0
1.0
the tested pin at 0V
iolꢀ
Output Leakage Current
Output High Voltage Level ioh = –0.1 mAꢀ
Output Low Voltage Level
Output is disabled, 0V ≤ Vout ≤ Vddꢀ
-1.5ꢀ
0.9 x Vddqꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
1.5ꢀ
—ꢀ
0.2
mA
V
V
Vohꢀ
Volꢀ
iol = +0.1 mAꢀ
(1,2)
CAPACITANCE CHARACTERISTICS
(Ta = 0°C to +25°C, Vdd = Vddqꢀ=ꢀ1.8V + 0.15V, f = 1 MHz)
Symbol
Cin1
Parameter
Min.
Max.
4.0
Unit
pF
Input Capacitance: CLK
2.5
Cin2
Input Capacitance: (A0-A11, CKE, CS, RAS, CAS, WE, LDQM, UDQM) 2.5
Data Input/Output Capacitance: DQ0-DQ15 4.0
5.0
pF
CI/O
6.5
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. All voltages are referenced to Vss.
3. Vih (max) = Vddq + 1.2V with a pulse width ≤ 3 ns.
4. Vil (min) = -1.2V with a pulse width ≤ 3 ns.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42VS16100F DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
-75
-10
Unit
icc1
Operating Current(1,2)
One Bank Operation, CAS Latency = 3
Burst Length=1
45
35
mA
mA
trc ≥ trc (min)
Iout = 0mA
CAS Latency = 2
tck = tck (min)
tckꢀ=ꢀ∞
50
0.3
0.3
40
0.3
0.3
mA
mA
mA
icc2p
Precharge Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max)
Icc2psꢀ
Precharge Standby Current
(In Power-Down and
Clock Suspend Mode)
ꢀ
CKE ≤ Vil (max)ꢀ
CLK ≤ Vil (max)
ꢀicc2n
Precharge Standby Current(3) CKE ≥ Vih (min)
(In Non Power-Down Mode) CS ≥ Vih (min)
tck = tck (min)
25
10
20
10
mA
mA
Icc2nsꢀ
Precharge Standby Current
(In Non Power-Down and
Clock Suspend Mode)
CKE ≥ Vih (min)
CLK ≤ Vil (max)
tckꢀ=ꢀ∞ꢀ
Inputs are stable
ꢀicc3P
Active Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max)
tck = tck (min)
3
3
3
3
mA
mA
Icc3Psꢀ
Active Standby Currentꢀ
(In Power-Down and
CKE ≤ Vil (max)
CLK ≤ Vil (max)
tckꢀ=ꢀ∞ꢀ
Inputs are stable
Clock Suspend Mode)
ꢀicc3n
Active Standby Current(3) CKE ≥ Vih (min)
(In Non Power-Down Mode) CS ≥ Vih (min)
tck = tck (min)
30
10
25
10
mA
mA
Icc3nsꢀ
Active Standby Current
(In Non Power-Down and
Clock Suspend Mode)
CKE ≥ Vih (min)
CLK ≤ Vil (max)
tckꢀ=ꢀ∞ꢀ
Inputs are stable
icc4
Operating Current
(In Burst Mode)(1,3)
Both Banks activated tck = tck (min)
Page Burst
60
50
mA
mA
Ioutꢀ= 0mA
trc = trcꢀ(min)
CKE ≤ 0.2V
icc5
Auto-Refresh Current
Self-Refresh Current
50
40
mA
icc6
180
180
µA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vddꢀand Vss for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
3. Inputs changed once every two clocks.
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11
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2,3,6)
IS42VS16100F AC CHARACTERISTICS
-75
-10
Symbol Parameter
Min. Max.
Min.
Max.
Units
tck3
tck2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
—
—
10
12
—
—
ns
ns
tac3
tac2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
—
—
6
8
—
—
7
8
ns
ns
tchi
tcl
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
2.5
2.5
—
—
3
3
—
—
ns
ns
toh3
toh2
CAS Latency = 3
CAS Latency = 2
2
2
—
—
2
2
—
—
ns
ns
tlz
Output LOW Impedance Time
0
—
0
—
ns
thz3
thz2
Output HIGH Impedance Time(5)
CAS Latency = 3
CAS Latency = 2
—
—
6
8
—
—
7
8
ns
ns
tds
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
2
—
—
—
—
—
—
—
—
—
—
2
1
2
1
2
1
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdh
1
tas
2
tah
1
tcks
tckh
tcka
tcs
CKE Setup Time
2
CKE Hold Time
1
CKE to CLK Recovery Delay Time
1CLK+3
1CLK+3
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
2
1
2
1
tch
trc
75
100
tras
trp
45 100,000
60 100,000
Command Period (PRE to ACT)
20
20
—
—
—
—
24
24
—
—
—
—
trcd
trrd
tdpl3
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
15
20
Input Data To Precharge
Command Delay time
CAS Latency = 3
2CLK
2CLK
tdpl2
tdal3
CAS Latency = 2
CAS Latency = 3
2CLK
—
2CLK
—
—
ns
ns
Input Data To Active / Refresh
2CLK+trpꢀ —
2CLK+trpꢀ
Command Delay time (During Auto-Precharge)
tdal2
ttꢀ
CAS Latency = 2
2CLK+trpꢀ —
2CLK+trpꢀ
—
1.2
32
ns
ns
Transition Time
0.5
—
1.2
32
0.5
—
tref
Refresh Cycle Time (2048)
ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. measured with ttꢀ= 1.0 ns. Ifꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tt/2ꢀ-ꢀ0.5)nsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between Vihꢀ(min.) and Vilꢀ(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time thzꢀ(max.) is defined as the time required for the output voltage to become high impedance.
6. Not all parameters are tested at the wafer level, but the parameters have been previously characterized.
12ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
IS42VS16100F OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-75
7.5
-10
10
-10
12
UNITS
ns
—
—
Clock Cycle Time
Operating Frequency
133
100
83
MHz
tcac
trcd
trac
trcꢀ
tras
trp
CAS Latency
3
3
3
3
2
2
4
8
5
2
2
1
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
Active Command To Read/Write Command Delay Time
RAS Latency (trcd + tcac)
6
6
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
10
6
10
6
3
3
trrd
tccd
2
2
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
tdpl
tdal
Input Data To Precharge Command Delay Time
2
5
2
5
2
4
cycle
cycle
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
trbd
twbd
trql
twdl
tpql
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
CAS Latency = 3
CAS Latency = 2
3
—
3
—
—
2
cycle
cycle
cycle
cycle
cycle
Burst Stop Command To Input in Invalid Delay Time
(Write)
0
0
0
Precharge Command To Output in HIGH-Z Delay Time
(Read)
CAS Latency = 3
CAS Latency = 2
3
—
3
—
—
2
Precharge Command To Input in Invalid Delay Time
(Write)
0
0
0
Last Output To Auto-Precharge Start Time (Read)
CAS Latency = 3
CAS Latency = 2
-2
—
–2
—
—
-1
tqmd
tdmd
tmrd
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
2
0
2
2
0
2
2
0
2
cycle
cycle
cycle
Mode Register Set To Command Delay Time
AC TEST CONDITIONS (Input/Output Reference Level: 0.9V)
Output Load
Input
t
CK
t
CL
t
CHI
1.8V
0.9V
50 Ω
CLK
0.0V
0.5 x VDDQ V
I/O
t
CS
t
CH
1.8V
0.9V
0.0V
INPUT
30 pF
t
AC
t
OH
0.9V
0.9V
OUTPUT
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13
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
COMMANDS
Active Command
Read Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
ROW
A0-A9
A10
A0-A9
AUTO PRECHARGE
ROW
A10
A11
NO PRECHARGE
BANK 1
BANK 1
A11
BANK 0
BANK 0
Write Command
Precharge Command
CLK
CLK
HIGH
HIGH
CKE
CS
CKE
CS
RAS
RAS
CAS
WE
CAS
WE
(1)
COLUMN
A0-A9
A0-A9
AUTO PRECHARGE
BANK 0 AND BANK 1
A10
A11
A10
A11
NO PRECHARGE
BANK 1
BANK 0 OR BANK 1
BANK 1
BANK 0
BANK 0
Don't Care
Notes:ꢀ
1.ꢀꢀA8-A9ꢀ=ꢀDon’tꢀCare.
14ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
COMMANDS (cont.)
No-Operation Command
Device Deselect Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
A0-A9
A10
A11
A10
A11
Mode Register Set Command
Auto-Refresh Command
CLK
CLK
HIGH
HIGH
CKE
CKE
CS
CS
RAS
RAS
CAS
WE
CAS
WE
A0-A9
OP-CODE
OP-CODE
OP-CODE
A0-A9
A10
A11
A10
A11
Don't Care
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15
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
COMMANDS (cont.)
Self-Refresh Command
Power Down Command
CLK
CLK
ALL BANKS IDLE
CKE
CS
CKE
CS
NOP
NOP
RAS
RAS
NOP
NOP
CAS
WE
CAS
WE
A0-A9
A0-A9
A10
A11
A10
A11
Clock Suspend Command
Burst Stop Command
CLK
CLK
BANK(S) ACTIVE
CKE
HIGH
CKE
CS
NOP
CS
NOP
RAS
RAS
NOP
CAS
CAS
WE
NOP
WE
A0-A9
A0-A9
A10
A11
A10
A11
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Mode Register Set Command
(CS,ꢀRAS,ꢀCAS,ꢀWEꢀ=ꢀLOW)
WhenꢀtheꢀA10ꢀpinꢀisꢀHIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀaꢀ
readꢀwithꢀauto-prechargeꢀcommand.ꢀAfterꢀtheꢀburstꢀreadꢀ
completes,ꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀisꢀprecharged.ꢀ
WhenꢀtheꢀA10ꢀpinꢀisꢀLOW,ꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀ
pinꢀ remainsꢀ inꢀ theꢀ activatedꢀ stateꢀ afterꢀ theꢀ burstꢀ readꢀ
completes.
Theꢀ IS42/45S16100Fꢀ andꢀ IS42VS16100Fꢀ productꢀ
incorporatesꢀaꢀregisterꢀthatꢀdefinesꢀtheꢀdeviceꢀoperatingꢀ
mode.ꢀThisꢀcommandꢀfunctionsꢀasꢀaꢀdataꢀinputꢀpinꢀthatꢀ
loadsꢀthisꢀregisterꢀfromꢀtheꢀpinsꢀA0ꢀtoꢀA11.ꢀWhenꢀꢀpowerꢀ
isꢀfirstꢀapplied,ꢀtheꢀstipulatedꢀpower-onꢀsequenceꢀshouldꢀ
beꢀexecutedꢀandꢀthenꢀtheꢀSDRAMꢀshouldꢀbeꢀinitializedꢀ
byꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀcommand.
Write Command
(CS,ꢀCAS,ꢀWEꢀ=ꢀLOW,ꢀꢀRASꢀ=ꢀHIGH)
Noteꢀ thatꢀ theꢀ modeꢀ registerꢀ setꢀ commandꢀ canꢀ beꢀ
executedꢀonlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀstateꢀ(i.e.ꢀ
deactivated).
Whenꢀburstꢀwriteꢀmodeꢀhasꢀbeenꢀselectedꢀwithꢀtheꢀmodeꢀ
registerꢀsetꢀcommand,ꢀthisꢀcommandꢀselectsꢀtheꢀbankꢀ
specifiedꢀbyꢀtheꢀA11ꢀpinꢀandꢀstartsꢀaꢀburstꢀwriteꢀoperationꢀ
atꢀtheꢀstartꢀaddressꢀspecifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀThisꢀfirstꢀ
dataꢀmustꢀbeꢀinputꢀtoꢀtheꢀDQꢀpinsꢀinꢀtheꢀcycleꢀinꢀwhichꢀ
thisꢀcommand.
Anotherꢀ commandꢀ cannotꢀ beꢀ executedꢀ afterꢀ aꢀ modeꢀ
registerꢀsetꢀcommandꢀuntilꢀafterꢀtheꢀpassageꢀofꢀtheꢀperiodꢀ
tmcd, whichꢀisꢀtheꢀperiodꢀrequiredꢀforꢀmodeꢀregisterꢀsetꢀ
commandꢀexecution.
Theꢀselectedꢀbankꢀmustꢀbeꢀactivatedꢀbeforeꢀexecutingꢀ
thisꢀcommand.
Active Command
WhenꢀA10ꢀ pinꢀ isꢀ HIGH,ꢀ thisꢀ commandꢀ functionsꢀ asꢀ aꢀ
writeꢀwithꢀauto-prechargeꢀcommand.ꢀAfterꢀtheꢀburstꢀwriteꢀ
completes,ꢀtheꢀbankꢀselectedꢀbyꢀpinꢀA11ꢀisꢀprecharged.ꢀ
WhenꢀtheꢀA10ꢀpinꢀisꢀlow,ꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀ
pinꢀ remainsꢀ inꢀ theꢀ activatedꢀ stateꢀ afterꢀ theꢀ burstꢀ writeꢀ
completes.
(CS,ꢀRASꢀ=ꢀLOW,ꢀCAS,ꢀWE=ꢀHIGH)
TheꢀSDRAMꢀincludesꢀtwoꢀbanksꢀofꢀ2048ꢀrowsꢀeach.ꢀThisꢀ
commandꢀselectsꢀoneꢀofꢀtheꢀtwoꢀbanksꢀaccordingꢀtoꢀtheꢀ
A11ꢀpinꢀandꢀactivatesꢀtheꢀrowꢀselectedꢀbyꢀtheꢀpinsꢀA0ꢀtoꢀ
A10.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀfallꢀofꢀtheꢀRASꢀsignalꢀ
fromꢀHIGHꢀtoꢀLOWꢀinꢀconventionalꢀDRAMs.
Afterꢀtheꢀinputꢀofꢀtheꢀlastꢀburstꢀwriteꢀdata,ꢀtheꢀapplicationꢀ
mustꢀwaitꢀforꢀtheꢀwriteꢀrecoveryꢀperiodꢀ(tdpl,ꢀtdal)ꢀtoꢀelapseꢀ
accordingꢀtoꢀCASꢀlatency.
Precharge Command
(CS,ꢀRAS,ꢀWEꢀ=ꢀLOW,ꢀCASꢀ=ꢀHIGH)
Auto-Refresh Command
(CS,ꢀRAS,ꢀCASꢀ=ꢀLOW,ꢀWE,ꢀCKEꢀꢀ=ꢀHIGH)
Thisꢀcommandꢀstartsꢀprechargingꢀtheꢀbankꢀselectedꢀbyꢀ
pinsꢀA10ꢀandꢀA11.ꢀWhenꢀA10ꢀisꢀHIGH,ꢀbothꢀbanksꢀareꢀ
prechargedꢀ atꢀ theꢀ sameꢀ time.ꢀ WhenꢀA10ꢀ isꢀ LOW,ꢀ theꢀ
bankꢀselectedꢀbyꢀA11ꢀisꢀprecharged.ꢀAfterꢀexecutingꢀthisꢀ
command,ꢀtheꢀnextꢀcommandꢀforꢀtheꢀselectedꢀbank(s)ꢀ
isꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtrp,ꢀwhichꢀisꢀtheꢀ
periodꢀrequiredꢀforꢀbankꢀprecharging.
Thisꢀcommandꢀexecutesꢀtheꢀauto-refreshꢀoperation.ꢀTheꢀ
rowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.
Bothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀidleꢀstateꢀbeforeꢀexecutingꢀ
thisꢀcommand.
Theꢀstipulatedꢀperiodꢀ(trc)ꢀisꢀrequiredꢀforꢀaꢀsingleꢀrefreshꢀ
operation,ꢀ andꢀ noꢀ otherꢀ commandsꢀ canꢀ beꢀ executedꢀ
duringꢀthisꢀperiod.
ThisꢀcommandꢀcorrespondsꢀtoꢀtheꢀRASꢀsignalꢀfromꢀLOWꢀ
toꢀHIGHꢀinꢀconventionalꢀDRAMs
Theꢀdeviceꢀgoesꢀtoꢀtheꢀidleꢀstateꢀafterꢀtheꢀinternalꢀrefreshꢀ
operationꢀcompletes.
Read Command
(CS,ꢀCASꢀ=ꢀLOW,ꢀRAS,ꢀWEꢀ=ꢀHIGH)
Thisꢀ commandꢀ mustꢀ beꢀ executedꢀ atꢀ leastꢀ 2048ꢀ timesꢀ
everyꢀ32ꢀms.
ThisꢀcommandꢀselectsꢀtheꢀbankꢀspecifiedꢀbyꢀtheꢀA11ꢀpinꢀ
andꢀ startsꢀ aꢀ burstꢀ readꢀ operationꢀ atꢀ theꢀ startꢀ addressꢀ
specifiedꢀbyꢀpinsꢀA0ꢀtoꢀA9.ꢀDataꢀisꢀoutputꢀfollowingꢀCASꢀ
latency.
Thisꢀ commandꢀ correspondsꢀ toꢀ CBRꢀ auto-refreshꢀ inꢀ
conventionalꢀDRAMs.
Theꢀselectedꢀbankꢀmustꢀbeꢀactivatedꢀbeforeꢀexecutingꢀ
thisꢀcommand.
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17
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
mode is started by dropping the CKE pin from HIGH to
LOW,whilesatisfyingtheothercommandinputconditions
(see CKE Truth Table). Power-down mode continues as
long as the CKE pin is held low. All pins other than the
CKE pin are invalid and none of the other commands can
be executed in this mode. The power-down operation is
terminated by raising the CKE pin from LOW to HIGH.
The next command cannot be executed until the recovery
period (tcka) has elapsed.
Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation.Theself-refreshoperationisstartedbydropping
the CKE pin from HIGH to LOW.The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The
self-refresh operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the device internal recovery period (trc)ꢀ
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addresses (2048 cycles).
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that power-down mode can be held
is just under the refresh cycle time.
Bothbanksmustbeplacedintheidlestatebeforeexecuting
this command.
Clock Suspend
(CKE = LOW)
Thiscommandcanbeusedtostopthedeviceinternalclock
temporarily during a read or write cycle. Clock suspend
mode is started by dropping the CKE pin from HIGH to
LOW.Clock suspend mode continues as long as the CKE
pin is held LOW. All input pins other than the CKE pin are
invalid and none of the other commands can be executed
in this mode. Also note that the device internal state is
maintained.Clock suspend mode is terminated by raising
the CKE pin from LOW to HIGH, at which point device
operationrestarts.Thenextcommandcannotbeexecuted
until the recovery period (tcka) has elapsed.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write
operations.Whenthiscommandisexecutedduringaburst
read operation, data output stops after the CAS latency
period has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
Sincethiscommanddiffersfromtheself-refreshcommand
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object
of operation. In other words, it performs no operation with
respect to the device.
Power-Down Command
(CKE = LOW, CS = HIGH)
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to the
minimal level in order to retain data content. Power-down
18ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2)
COMMAND TRUTH TABLE
CKE
Symbol Command
n-1 n CS RAS CAS WE DQM A11 A10
A9-A0 I/On
MRS
REF
SREF
PRE
PALL
ACT
WRIT
WRITA
READ
READA
BST
NOP
DESL
ENB
Mode Register Set(3,4)
Auto-Refresh(5)
Self-Refresh(5,6)
Precharge Selected Bank
Precharge Both Banks
Bank Activate(7)
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
X
X
X
L
H
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
X
X
X
X
X
X
X
H
X
X
X
X
BS
X
BS Row
BS
BS
BS
BS
X
L
H
X
X
X
X
X
X
X
X
X
X
Row
Column
Column
Column
Column
X
L
(18)
(18)
(18)
Write
H
H
H
H
H
H
X
X
X
L
H
L
H
X
X
X
X
X
Write With Auto-Precharge(8)
Read(8)
Read With Auto-Precharge(8)
Burst Stop(9)
No Operation
Device Deselect
L
H
H
L
H
X
X
X
(18)
X
X
X
X
X
X
X
X
X
Data Write / Output Enable
Data Mask / Output Disable
Active
HIGH-Z
MASK
H
(1,2)
DQM TRUTH TABLE
CKE
DQM
Symbol Command
n-1
H
H
H
H
n
UPPER
LOWER
ENB
Data Write / Output Enable
Data Mask / Output Disable
Upper Byte Data Write / Output Enable
Lower Byte Data Write / Output Enable
X
L
H
L
X
H
X
L
H
X
L
X
H
MASK
ENBU
ENBL
X
X
X
X
X
MASKU Upper Byte Data Mask / Output Disable
MASKL Lower Byte Data Mask / Output Disable
H
H
(1,2)
CKE TRUTH TABLE
CKE
Symbol Command
Current State
Active
Other States
Clock Suspend
Idle
n-1
n
CS RAS CAS WE A11 A10A9-A0
SPND Start Clock Suspend Mode
H
L
L
H
L
L
H
H
L
X
X
X
L
X
X
X
L
X
X
X
L
X
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
Clock Suspend
—
REF
SELF
Terminate Clock Suspend Mode
Auto-Refresh
Start Self-Refresh Mode
Idle
H
L
L
L
SELFX Terminate Self-Refresh Mode
Self-Refresh
L
L
H
H
L
H
H
X
H
X
H
X
X
X
X
X
X
X
PDWN Start Power-Down Mode
Idle
H
H
L
L
L
H
H
X
H
X
H
X
X
X
X
X
X
X
—
Terminate Power-Down Mode
Power-Down
L
L
H
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
19
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Idleꢀ
DESLꢀ
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Down(12)
NoꢀOperationꢀorꢀPower-Downꢀ
Illegalꢀ
ꢀ
ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READꢀ/ꢀREADAꢀ
WRIT/WRITAꢀ
ACTꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
ꢀ
Illegalꢀ
Lꢀ
ꢀ
RowꢀActiveꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperationꢀ
Lꢀ
X
ꢀ
Auto-RefreshꢀorꢀSelf-Refresh(13)
ModeꢀRegisterꢀSetꢀ
NoꢀOperationꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
RowꢀActiveꢀ
DESLꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
NoꢀOperationꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
NoꢀOperationꢀ
ReadꢀStart(17)
WriteꢀStart(17)
Illegal(10)
ꢀ
Hꢀ
Lꢀ
V
V
V
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
(18)
ꢀ
ꢀ
Lꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Precharge(15)
ꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODEꢀ
Readꢀ
DESLꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀRowꢀActiveꢀWhenꢀDoneꢀ
BurstꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀInterrupted,ꢀReadꢀRestartꢀAfterꢀInterrupt(16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
BSTꢀ
(18)
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀInterruptedꢀWriteꢀStartꢀAfterꢀInterrupt(11,16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀReadꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Illegalꢀ
Lꢀ
X
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
Writeꢀ
DESLꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀWhenꢀDoneꢀ
BurstꢀWriteꢀInterrupted,ꢀRowꢀActiveꢀAfterꢀInterruptꢀ
BurstꢀWriteꢀInterrupted,ꢀReadꢀStartꢀAfterꢀInterrupt(11,16)
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ꢀ
Hꢀ
Lꢀ
V
V
V
BurstꢀWriteꢀInterrupted,ꢀWriteꢀRestartꢀAfterꢀInterrupt(16)
Illegal(10)
ꢀ
Lꢀ
(18)
(18)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
BurstꢀWriteꢀInterrupted,ꢀPrechargeꢀAfterꢀInterruptꢀ
Lꢀ
X
Illegalꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
X
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
ReadꢀWithꢀ
Auto-ꢀ
DESLꢀ
NOPꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
BurstꢀReadꢀContinues,ꢀPrechargeꢀWhenꢀDoneꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Prechargeꢀ
BSTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
V
(18)
(18)
Lꢀ
V
V
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Lꢀ
X
Lꢀ
Hꢀ
Lꢀ
X
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
20ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
WriteꢀWithꢀ
Auto-Prechargeꢀ
DESLꢀ
ꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
WhenꢀDone
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
BurstꢀWriteꢀContinues,ꢀWriteꢀRecoveryꢀAndꢀPrechargeꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
BSTꢀ
Illegalꢀ
Illegalꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
Illegalꢀ
(10)
Lꢀ
Illegal
Illegal
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
(10)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Lꢀ
X
X
Illegalꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀ OPCODE
RowꢀPrechargeꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrp HasꢀElapsedꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
(10)
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal
Illegal
Illegal
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
V
V
V
(10)
(10)
(18)
(18)
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
(10)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsed
ꢀ
Lꢀ
X
X
Illegalꢀ
Illegalꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
Immediatelyꢀ
Followingꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcdꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcdꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Xꢀ
Xꢀ
Vꢀ
ꢀ
RowꢀActiveꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtrcdꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
X
(18)
(10)
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegal
ꢀ
V
(10)
(18)
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Illegal
Illegal
Illegal
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Vꢀ Vꢀ V
(10,14)
ꢀ
Hꢀ Hꢀ Vꢀ Vꢀ V
(10)
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Vꢀ Vꢀ
X
X
Illegalꢀ
Illegalꢀ
Hꢀ Xꢀ Xꢀ
Lꢀ
ꢀOPꢀCODE
ꢀ
ꢀ
Writeꢀ
Recoveryꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtdpl HasꢀElapsedꢀ Hꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtdpl HasꢀElapsedꢀ Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀRowꢀActiveꢀAfterꢀtdplꢀHasꢀElapsedꢀ Lꢀ
Hꢀ Hꢀ
Lꢀ
Xꢀ Xꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
ReadꢀStartꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ Vꢀ Vꢀ V
(18)
(18)
WriteꢀRestartꢀ
(10)
Lꢀ
Vꢀ Vꢀ V
Illegal
Illegal
ꢀ
ꢀ
Hꢀ Hꢀ Vꢀ Vꢀ V
(10)
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ Xꢀ Xꢀ
Lꢀ
Vꢀ Vꢀ
X
X
Illegalꢀ
Illegalꢀ
ꢀOPꢀCODE
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
21
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2)
OPERATION COMMAND TABLE
Current State Command
Operation
CS RAS CAS WE A11 A10A9-A0
ꢀWriteꢀRecoveryꢀ
ꢀWithꢀAuto-ꢀ
DESLꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtdalꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtdalꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
ꢀPrechargeꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtdalꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
Illegal(10)
Illegal(10)
Illegal(10)
Illegal(10)
Illegalꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
(18)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
(18)
(18)
ꢀ
Lꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
ꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Lꢀ
X
ꢀ
Lꢀ
Hꢀ
Lꢀ
X
ꢀ
Illegalꢀ
Lꢀ
Lꢀ
ꢀ OPꢀCODE
Refreshꢀ
DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrp HasꢀElapsedꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NOPꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtrpꢀHasꢀElapsedꢀ
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Hꢀ
Lꢀ
V
V
V
(18)
(18)
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Lꢀ
X
Lꢀ
Hꢀ
Lꢀ
X
Lꢀ
Lꢀ
ꢀ OPꢀCODE
ꢀ
ꢀ
ModeꢀRegisterꢀ DESLꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcdꢀHasꢀElapsedꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcdꢀHasꢀElapsedꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
Setꢀ
NOPꢀ
Xꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
NoꢀOperation,ꢀIdleꢀStateꢀAfterꢀtmcdꢀHasꢀElapsedꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Xꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Xꢀ
X
(18)
READ/READAꢀ
WRIT/WRITAꢀ
ACTꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
Illegalꢀ
V
V
V
(18)
(18)
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
PRE/PALLꢀ
REF/SELFꢀ
MRSꢀ
Lꢀ
X
Lꢀ
Hꢀ
Lꢀ
X
Lꢀ
Lꢀ
ꢀ OPꢀCODE
Notes:ꢀ
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀꢀlevelꢀinput,ꢀX:ꢀ"Don'tꢀCare"ꢀinput,ꢀV:ꢀValidꢀdataꢀinput
2.ꢀAllꢀinputꢀsignalsꢀareꢀlatchedꢀonꢀtheꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignal.
3.ꢀBothꢀbanksꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
4.ꢀTheꢀstateꢀofꢀtheꢀA0ꢀtoꢀA11ꢀpinsꢀisꢀloadedꢀintoꢀtheꢀmodeꢀregisterꢀasꢀanꢀOPꢀcode.
5.ꢀTheꢀrowꢀaddressꢀisꢀgeneratedꢀautomaticallyꢀinternallyꢀatꢀthisꢀtime.ꢀTheꢀDQꢀpinꢀandꢀtheꢀaddressꢀpinꢀdataꢀisꢀignored.
6.ꢀDuringꢀaꢀself-refreshꢀoperation,ꢀallꢀpinꢀdataꢀ(states)ꢀotherꢀthanꢀCKEꢀisꢀignored.
7.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀinactiveꢀ(idle)ꢀstateꢀinꢀadvance.
8.ꢀTheꢀselectedꢀbankꢀmustꢀbeꢀplacedꢀinꢀtheꢀactiveꢀstateꢀinꢀadvance.
9.ꢀThisꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀburstꢀlengthꢀsetꢀtoꢀfullꢀpage.
10.ꢀThisꢀisꢀpossibleꢀdependingꢀonꢀtheꢀstateꢀofꢀtheꢀbankꢀselectedꢀbyꢀtheꢀA11ꢀpin.
11.ꢀTimeꢀtoꢀswitchꢀinternalꢀbussesꢀisꢀrequired.
12.ꢀTheꢀSDRAMꢀcanꢀbeꢀswitchedꢀtoꢀpower-downꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀstate.ꢀInputꢀpinsꢀ
otherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
13.ꢀTheꢀSDRAMꢀcanꢀbeꢀswitchedꢀtoꢀself-refreshꢀmodeꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀLOWꢀwhenꢀbothꢀbanksꢀinꢀtheꢀidleꢀstate.ꢀInputꢀpinsꢀ
otherꢀthanꢀCKEꢀareꢀignoredꢀatꢀthisꢀtime.
14.ꢀPossibleꢀifꢀtrrdꢀisꢀsatisfied.
15.ꢀIllegalꢀifꢀtrasꢀisꢀnotꢀsatisfied.
16.ꢀTheꢀconditionsꢀforꢀburstꢀinterruptionꢀmustꢀbeꢀobserved.ꢀAlsoꢀnoteꢀthatꢀtheꢀSDRAMꢀwillꢀenterꢀtheꢀpreꢀ
stateꢀimmediatelyꢀafterꢀtheꢀburstꢀoperationꢀcompletesꢀifꢀauto-prechargeꢀisꢀselected.
ꢀ
chargedꢀ
17.ꢀCommandꢀinputꢀbecomesꢀpossibleꢀafterꢀtheꢀperiodꢀtrcd hasꢀelapsed.ꢀAlsoꢀnoteꢀthatꢀtheꢀSDRAMꢀwillꢀenterꢀtheꢀprechargedꢀstateꢀ
immediatelyꢀafterꢀtheꢀburstꢀoperationꢀcompletesꢀifꢀauto-prechargeꢀisꢀselected.
18.ꢀꢀA8,A9ꢀꢀ=ꢀdon’tꢀcare.
22ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1)
CKE RELATED COMMAND TRUTH TABLE
CKE
n-1
Current State
Operation
n
X
H
H
H
H
L
CS RAS CAS WE A11 A10 A9-A0
Self-Refresh
Undefined
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegal(2)
L
L
L
Illegal(2)
L
L
X
X
X
H
L
Maintain Self-Refresh
Idle State After trc Has Elapsed
Idle State After trc Has Elapsed
Illegal
L
X
H
L
X
X
H
H
L
Self-Refresh Recovery
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
Illegal
L
X
X
H
L
Power-Down on the Next Cycle
Power-Down on the Next Cycle
Illegal
H
L
X
H
H
L
L
L
L
Illegal
L
L
X
X
X
X
X
Clock Suspend Termination on the Next Cycle (2)
H
L
X
X
X
X
X
X
X
X
Maintain Clock Suspend
L
Power-Down
Undefined
H
L
X
H
Power-Down Mode Termination, Idle After
That Termination(2)
Maintain Power-Down Mode
No Operation
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
Both Banks Idle
X
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
X
L
X
L
L
X
Mode Register Set
L
L
L
OP CODE
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh(3)
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
L
X
L
L
X
L
L
L
X
See the Operation Command Table
Power-Down Mode(3)
L
L
L
L
OP CODE
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other States
See the Operation Command Table
Clock Suspend on the Next Cycle(4)
Clock Suspend Termination on the Next Cycle
Maintain Clock Suspend
H
H
L
H
L
L
Notes:
1. H: HIGH level input, L: LOW level input, X: "Don't Care" input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.
The minimum setup time (tcka) required before all commands other than mode termination must be satisfied.
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command defined in the operation command table.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
23
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
(1,2)
TWO BANKS OPERATION COMMAND TRUTH TABLE
Previous State
Next State
Operation
DESLꢀ
CS RAS CAS WE A11 A10A9-A0 BANK 0BANK 1 BANK 0BANK 1
ꢀ
ꢀ
Hꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ Xꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Anyꢀ
Any
Any
NOPꢀ
Lꢀ
Hꢀ Hꢀ Hꢀ Xꢀ Xꢀ Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BSTꢀ
Lꢀ
ꢀ
ꢀ
Hꢀ Hꢀ
Lꢀ
ꢀ
ꢀ
Xꢀ Xꢀ Xꢀ
R/W/Aꢀ I/Aꢀ
Iꢀ I/Aꢀ
I/Aꢀ R/W/Aꢀ
I/Aꢀ Iꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
I/Aꢀ R/W/Aꢀ
R/Wꢀ Aꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ R/Wꢀ
R/W/Aꢀ I/Aꢀ
Aꢀ
Iꢀ
I/Aꢀ
I/Aꢀ
I/Aꢀ
I/Aꢀ
Aꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
READ/READAꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ Hꢀ Hꢀ CA(3)ꢀ
I/Aꢀ
Aꢀ
I/Aꢀ
Aꢀ
RPꢀ
RPꢀ
Rꢀ
RP
RP
R
R
I/A
A
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Hꢀ CA(3)ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
Hꢀ CA(3)ꢀ
Hꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I/A
A
ꢀ
ꢀ
Rꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
WRIT/WRITAꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ Hꢀ CA(3)ꢀ
Hꢀ Hꢀ CA(3)ꢀ
I/Aꢀ
Aꢀ
I/Aꢀ
Aꢀ
WPꢀ
WPꢀ
Wꢀ
WP
WP
W
W
I/A
A
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
Hꢀ CA(3)ꢀ
Hꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
Lꢀ CA(3)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I/A
A
ꢀ
ꢀ
Aꢀ
R/Wꢀ
Wꢀ
ꢀ
ꢀ
ACTꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Hꢀ Hꢀ Hꢀ RAꢀ RAꢀ
Anyꢀ
Iꢀ
Iꢀ
Anyꢀ
Anyꢀ
Aꢀ
Aꢀ
Any
ꢀ
ꢀ
Lꢀ RAꢀ RAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
PRE/PALLꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Xꢀ Hꢀ Xꢀ
Xꢀ Hꢀ Xꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
I/Aꢀ R/W/A/Iꢀ
R/W/A/Iꢀ I/Aꢀ
R/W/A/Iꢀ I/Aꢀ
I/Aꢀ R/W/A/Iꢀ
Iꢀ
Iꢀ
I/Aꢀ
Iꢀ
Iꢀ
Iꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
R/W/A/Iꢀ Iꢀ
Iꢀ
I/Aꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Iꢀ R/W/A/I
ꢀ
ꢀ
REFꢀ
MRSꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ Xꢀ Xꢀ Xꢀ
Lꢀ ꢀOPCODEꢀꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
Iꢀ
I
I
Notes:ꢀ
1.ꢀH:ꢀHIGHꢀlevelꢀinput,ꢀL:ꢀLOWꢀlevelꢀinput,ꢀX:ꢀHIGHꢀorꢀLOWꢀlevelꢀinput,ꢀRA:ꢀRowꢀAddress,ꢀCA:ꢀColumnꢀAddress
2.ꢀTheꢀdeviceꢀstateꢀsymbolsꢀareꢀinterpretedꢀasꢀfollows:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Iꢀ
Aꢀ
Rꢀ
Idleꢀ(inactiveꢀstate)
RowꢀActiveꢀState
Read
Wꢀ Write
RPꢀ ReadꢀWithꢀAuto-Precharge
WPꢀ WriteꢀWithꢀAuto-Precharge
Anyꢀ AnyꢀState
3.ꢀꢀCA:ꢀA8,A9ꢀ=ꢀdon’tꢀcare.
24ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
SIMPLIFIED STATE TRANSITION DIAGRAM (OneꢀBankꢀOperation)
SELF
REFRESH
SREF entry
SREF exit
MRS
MODE
REGISTER
SET
AUTO
REF
IDLE
REFRESH
CKE_
CKE
IDLE
ACT
POWER
DOWN
ACTIVE
POWER
DOWN
CKE_
CKE
BANK
ACTIVE
BST
BST
READ
WRIT
WRIT
CKE_
READ
CKE_
WRITA
READA
READ
WRITE
READ
WRIT
CKE
READA
CKE_
CLOCK
SUSPEND
CKE
CLOCK
SUSPEND
WRITA
WRITA
READA
CKE_
CKE
CKE
WRITE WITH
AUTO
READ WITH
AUTO
PRECHARGE
PRECHARGE
PRE
PRE
PRE
PRE-
CHARGE
PRE
POWER APPLIED
POWER ON
Automatic transition following the
completion of command execution.
Transition due to command input.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
25
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Device Initialization At Power-On
Burst Length
(Power-OnꢀSequence)
Whenꢀwritingꢀorꢀreading,ꢀdataꢀcanꢀbeꢀinputꢀorꢀoutputꢀdataꢀ
continuously.ꢀInꢀtheseꢀoperations,ꢀanꢀaddressꢀisꢀinputꢀonlyꢀ
onceꢀandꢀthatꢀaddressꢀisꢀtakenꢀasꢀtheꢀstartingꢀaddressꢀ
internallyꢀbyꢀtheꢀdevice.ꢀTheꢀdeviceꢀthenꢀautomaticallyꢀ
generatesꢀtheꢀfollowingꢀaddress.ꢀTheꢀburstꢀlengthꢀfieldꢀ
inꢀtheꢀmodeꢀregisterꢀstipulatesꢀtheꢀnumberꢀofꢀdataꢀitemsꢀ
inputꢀorꢀoutputꢀinꢀsequence.ꢀInꢀtheꢀSDRAMꢀproduct,ꢀaꢀ
burstꢀlengthꢀofꢀ1,ꢀ2,ꢀ4,ꢀ8,ꢀorꢀfullꢀpageꢀcanꢀbeꢀspecified.ꢀ
Seeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀonꢀsettingꢀtheꢀ
modeꢀregister.
Asꢀ isꢀ theꢀ caseꢀ withꢀ conventionalꢀ DRAMs,ꢀ theꢀ SDRAMꢀ
productꢀmustꢀbeꢀinitializedꢀbyꢀexecutingꢀaꢀstipulatedꢀpower-
onꢀsequenceꢀafterꢀpowerꢀisꢀapplied.
AfterꢀpowerꢀisꢀappliedꢀandꢀVddꢀandꢀVddQꢀreachꢀtheirꢀ
stipulatedꢀvoltages,ꢀsetꢀandꢀholdꢀtheꢀCKEꢀandꢀDQMꢀpinsꢀ
HIGHꢀforꢀ100ꢀµs.ꢀThen,ꢀexecuteꢀtheꢀprechargeꢀcommandꢀ
toꢀprechargeꢀbothꢀbank.ꢀNext,ꢀexecuteꢀtheꢀauto-refreshꢀ
commandꢀtwiceꢀorꢀmoreꢀandꢀdefineꢀtheꢀdeviceꢀoperationꢀ
modeꢀbyꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀcommand.
Theꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀalsoꢀsetꢀbeforeꢀ
auto-refreshꢀcommand.
Burst Type
Theꢀburstꢀdataꢀorderꢀduringꢀaꢀreadꢀorꢀwriteꢀoperationꢀisꢀ
stipulatedꢀbyꢀtheꢀburstꢀtype,ꢀwhichꢀcanꢀbeꢀsetꢀbyꢀtheꢀmodeꢀ
registerꢀ setꢀ command.ꢀ Theꢀ SDRAMꢀ productꢀ supportsꢀ
sequentialꢀmodeꢀandꢀinterleavedꢀmodeꢀburstꢀtypeꢀsettings.ꢀ
Seeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀdetailsꢀonꢀsettingꢀtheꢀ
modeꢀregister.ꢀSeeꢀtheꢀ“BurstꢀLengthꢀandꢀColumnAddressꢀ
Sequence”ꢀitemꢀforꢀdetailsꢀonꢀDQꢀdataꢀordersꢀinꢀtheseꢀ
modes.
Mode Register Settings
Theꢀmodeꢀregisterꢀsetꢀcommandꢀsetsꢀtheꢀmodeꢀregister.ꢀ
Whenꢀthisꢀcommandꢀisꢀexecuted,ꢀpinsꢀA0ꢀtoꢀA9,ꢀA10,ꢀandꢀ
A11ꢀfunctionꢀasꢀdataꢀinputꢀpinsꢀforꢀsettingꢀtheꢀregister,ꢀandꢀ
thisꢀdataꢀbecomesꢀtheꢀdeviceꢀinternalꢀOPꢀcode.ꢀThisꢀOPꢀ
codeꢀhasꢀfourꢀfieldsꢀasꢀlistedꢀinꢀtheꢀtableꢀbelow.
Input Pin
Field
Write Mode
BurstꢀwriteꢀorꢀsingleꢀwriteꢀmodeꢀisꢀselectedꢀbyꢀtheꢀOPꢀcodeꢀ
(A11,ꢀA10,ꢀA9)ꢀofꢀtheꢀmodeꢀregister.
ꢀ A11,ꢀA10,ꢀA9,ꢀA8,ꢀA7ꢀ
ModeꢀOptions
CASꢀLatency
BurstꢀType
ꢀ
ꢀ
ꢀ
A6,ꢀA5,ꢀA4ꢀ
A3ꢀ
AꢀburstꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀtheꢀOPꢀcodeꢀ
(A11,ꢀA10,ꢀA9)ꢀtoꢀ(0,0,0).ꢀAꢀburstꢀwriteꢀstartsꢀonꢀtheꢀsameꢀ
cycleꢀasꢀaꢀwriteꢀcommandꢀset.ꢀTheꢀwriteꢀstartꢀaddressꢀisꢀ
specifiedꢀbyꢀtheꢀcolumnꢀaddressꢀandꢀbankꢀselectꢀaddressꢀ
atꢀtheꢀwriteꢀcommandꢀsetꢀcycle.
A2,ꢀA1,ꢀA0ꢀ
BurstꢀLength
Noteꢀthatꢀtheꢀmodeꢀregisterꢀsetꢀcommandꢀcanꢀbeꢀexecutedꢀ
onlyꢀwhenꢀbothꢀbanksꢀareꢀinꢀtheꢀidleꢀ(inactive)ꢀstate.ꢀWaitꢀ
atꢀleastꢀtwoꢀcyclesꢀafterꢀexecutingꢀaꢀmodeꢀregisterꢀsetꢀ
commandꢀbeforeꢀexecutingꢀtheꢀnextꢀcommand.
AꢀsingleꢀwriteꢀoperationꢀisꢀenabledꢀbyꢀsettingꢀOPꢀcodeꢀ(A11,ꢀ
A10,ꢀA9)ꢀtoꢀ(0,ꢀ0,1).ꢀInꢀaꢀsingleꢀwriteꢀoperation,ꢀdataꢀisꢀonlyꢀ
writtenꢀtoꢀtheꢀcolumnꢀaddressꢀandꢀbankꢀselectꢀaddressꢀ
specifiedꢀbyꢀtheꢀwriteꢀcommandꢀsetꢀcycleꢀwithoutꢀregardꢀ
toꢀtheꢀbustꢀlengthꢀsetting.
CAS Latency
Duringꢀaꢀreadꢀoperation,ꢀtheꢀbetweenꢀtheꢀexecutionꢀofꢀtheꢀ
readꢀcommandꢀandꢀdataꢀoutputꢀisꢀstipulatedꢀasꢀtheꢀCASꢀ
latency.ꢀThisꢀperiodꢀcanꢀbeꢀsetꢀusingꢀtheꢀmodeꢀregisterꢀ
setꢀ command.ꢀ Theꢀ optimalꢀ CASꢀ latencyꢀ isꢀ determinedꢀ
byꢀtheꢀclockꢀfrequencyꢀandꢀdeviceꢀspeedꢀgrade.ꢀSeeꢀtheꢀ
“OperatingꢀFrequencyꢀ/ꢀLatencyꢀRelationships”ꢀitemꢀꢀforꢀ
detailsꢀonꢀtheꢀrelationshipꢀbetweenꢀtheꢀclockꢀfrequencyꢀ
andꢀtheꢀCASꢀlatency.ꢀSeeꢀtheꢀtableꢀonꢀtheꢀnextꢀpageꢀforꢀ
detailsꢀonꢀsettingꢀtheꢀmodeꢀregister.
26ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
WRITEꢀMODEꢀ ꢀ LTꢀ
MODEꢀ ꢀ BTꢀ
ꢀ
BL
IS42/45S16100F, IS42VS16100F
MODE REGISTER
AddressꢀBusꢀ(Ax)
ModeꢀRegisterꢀ(Mx)
ꢀA11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
M2 M1 M0
Sequential Interleaved
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
BurstꢀLengthꢀ 0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
1ꢀ
2ꢀ
4ꢀ
8ꢀ
1
2
4
8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
Reservedꢀ Reserved
Reservedꢀ Reserved
Reservedꢀ Reserved
FullꢀPageꢀ Reserved
M3
0ꢀ
Type
ꢀ
BurstꢀTypeꢀ
Sequential
Interleavedꢀ
ꢀ
ꢀ
1ꢀ
M6 M5 M4 CAS Latency
ꢀ
LatencyꢀModeꢀ 0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
Reserved
Reserved
2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
3
Reserved
Reserved
Reserved
Reserved
M11
0ꢀ
M10
0ꢀ
M9
1ꢀ
M8
0ꢀ
M7
0ꢀ
Write Mode
ꢀ
ꢀ
BurstꢀReadꢀ&ꢀSingleꢀWrite
BurstꢀReadꢀ&ꢀBurstꢀWrite
0ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
Note:ꢀOtherꢀvaluesꢀforꢀtheseꢀbitsꢀareꢀreserved.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
27
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
BURST LENGTH AND COLUMN ADDRESS SEQUENCE
Column Address
A2 A1 A0
Address Sequence
Burst Length
Sequential
Interleaved
ꢀ
ꢀ
2ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
1ꢀ
0-1ꢀ
1-0ꢀ
0-1ꢀ
1-0
ꢀ
4ꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
0-1-2-3ꢀ
1-0-3-2ꢀ
2-3-0-1ꢀ
3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0ꢀ
1ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
2-3-4-5-6-7-0-1ꢀ
3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
0-1-2-3-4-5-6-7ꢀ
1-0-3-2-5-4-7-6ꢀ
2-3-0-1-6-7-4-5ꢀ
3-2-1-0-7-6-5-4ꢀ
4-5-6-7-0-1-2-3ꢀ
5-4-7-6-1-0-3-2ꢀ
6-7-4-5-2-3-0-1ꢀ
7-6-5-4-3-2-1-0
ꢀ
ꢀ
ꢀ
ꢀ
FullꢀPageꢀ
(256)ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
nꢀ
ꢀ
ꢀ
Cn,ꢀCn+1,ꢀCn+2ꢀ
Cn+3,ꢀCn+4.....ꢀ
...Cn-1(Cn+255),ꢀ
Cn(Cn+256).....ꢀ
Noneꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:ꢀ
1.ꢀTheꢀburstꢀlengthꢀinꢀfullꢀpageꢀmodeꢀisꢀ256.
28ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Rowꢀ
X0ꢀ
X1ꢀ
X2ꢀ
X3ꢀ
X4ꢀ
X5ꢀ
X6ꢀ
X7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X8ꢀ
—ꢀ
RowꢀAddress
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X9ꢀ
X10ꢀ
ꢀ
ꢀ
X11ꢀ
ꢀ
—ꢀ
—ꢀ
0ꢀ
1ꢀ
0ꢀ
RowꢀAddressꢀ
RowꢀAddressꢀ(ActiveꢀCommand)ꢀ
PrechargeꢀofꢀtheꢀSelectedꢀBankꢀ(PrechargeꢀCommand)ꢀ
PrechargeꢀofꢀBothꢀBanksꢀ(PrechargeꢀCommand)ꢀ
Bankꢀ0ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommands)ꢀ
Bankꢀ1ꢀSelectedꢀ(PrechargeꢀandꢀActiveꢀCommands)
ꢀ
ꢀ
ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Columnꢀ
Y0ꢀ
Y1ꢀ
Y2ꢀ
Y3ꢀ
Y4ꢀ
Y5ꢀ
Y6ꢀ
Y7ꢀ
Y8ꢀ
Y9ꢀ
Y10ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ColumnꢀAddressꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Don’tꢀCareꢀ
Don’tꢀCareꢀ
Auto-Prechargeꢀ-ꢀDisabledꢀ
Auto-Prechargeꢀ-ꢀEnablesꢀ
Bankꢀ0ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)ꢀ
Bankꢀ1ꢀSelectedꢀ(ReadꢀandꢀWriteꢀCommands)
1ꢀ
0ꢀ
1ꢀ
Y11ꢀ
ꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
29
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Burst Read
Theꢀreadꢀcycleꢀisꢀstartedꢀbyꢀexecutingꢀtheꢀreadꢀcommand.ꢀ
Theꢀaddressꢀprovidedꢀduringꢀreadꢀcommandꢀexecutionꢀisꢀ
usedꢀasꢀtheꢀstartingꢀaddress.ꢀFirst,ꢀtheꢀdataꢀcorrespondingꢀtoꢀ
thisꢀaddressꢀisꢀoutputꢀinꢀsynchronizationꢀwithꢀtheꢀclockꢀsignalꢀ
afterꢀtheꢀCASꢀlatencyꢀperiod.ꢀNext,ꢀdataꢀcorrespondingꢀtoꢀ
anꢀaddressꢀgeneratedꢀautomaticallyꢀbyꢀtheꢀdeviceꢀisꢀoutputꢀ
inꢀsynchronizationꢀwithꢀtheꢀclockꢀsignal.
isꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀInꢀthisꢀcaseꢀtheꢀoutputꢀbuffersꢀ
mustꢀbeꢀsetꢀtoꢀtheꢀhighꢀimpedanceꢀstateꢀbyꢀexecutingꢀaꢀ
burstꢀstopꢀcommand.
Noteꢀ thatꢀ upperꢀ byteꢀ andꢀ lowerꢀ byteꢀ outputꢀ dataꢀ canꢀ
beꢀmaskedꢀindependentlyꢀunderꢀcontrolꢀofꢀtheꢀsignalsꢀ
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tqmd)ꢀisꢀ
fixedꢀatꢀtwo,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting,ꢀwhenꢀ
thisꢀfunctionꢀisꢀused.
TheꢀoutputꢀbuffersꢀgoꢀtoꢀtheꢀLOWꢀimpedanceꢀstateꢀCASꢀ
latencyꢀminusꢀoneꢀcycleꢀafterꢀtheꢀreadꢀcommand,ꢀandꢀgoꢀtoꢀ
theꢀHIGHꢀimpedanceꢀstateꢀautomaticallyꢀafterꢀtheꢀlastꢀdataꢀ
isꢀoutput.ꢀHowever,ꢀtheꢀcaseꢀwhereꢀtheꢀburstꢀlengthꢀ
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
HI-Z
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Burst Write
Theꢀ writeꢀ cycleꢀ isꢀ startedꢀ byꢀ executingꢀ theꢀ command.ꢀ
Theꢀaddressꢀprovidedꢀduringꢀwriteꢀcommandꢀexecutionꢀ
isꢀusedꢀasꢀtheꢀstartingꢀaddress,ꢀandꢀatꢀtheꢀsameꢀtime,ꢀ
dataꢀforꢀthisꢀaddressꢀisꢀinputꢀinꢀsynchronizationꢀwithꢀtheꢀ
clockꢀsignal.
aꢀburstꢀꢀstopꢀcommand.ꢀꢀTheꢀlatencyꢀforꢀDQꢀpinꢀdataꢀinputꢀ
isꢀzero,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting.ꢀHowever,ꢀaꢀ
waitꢀperiodꢀ(writeꢀrecovery:ꢀtdpl)ꢀafterꢀtheꢀlastꢀdataꢀinputꢀisꢀ
requiredꢀforꢀtheꢀdeviceꢀtoꢀcompleteꢀtheꢀwriteꢀoperation.
Noteꢀthatꢀtheꢀupperꢀbyteꢀandꢀlowerꢀbyteꢀinputꢀdataꢀcanꢀ
beꢀ maskedꢀ independentlyꢀ underꢀ controlꢀ ofꢀ theꢀ signalsꢀ
appliedꢀtoꢀtheꢀU/LDQMꢀpins.ꢀTheꢀdelayꢀperiodꢀ(tdmd)ꢀisꢀ
fixedꢀatꢀzero,ꢀregardlessꢀofꢀtheꢀCASꢀlatencyꢀsetting,ꢀwhenꢀ
thisꢀfunctionꢀisꢀused.
Next,ꢀdataꢀisꢀinputꢀinꢀotherꢀinꢀsynchronizationꢀwithꢀtheꢀ
clockꢀ signal.ꢀ Duringꢀ thisꢀ operation,ꢀ dataꢀ isꢀ writtenꢀ toꢀ
addressꢀgeneratedꢀautomaticallyꢀbyꢀtheꢀdevice.ꢀThisꢀcycleꢀ
terminatesꢀautomaticallyꢀafterꢀaꢀnumberꢀofꢀclockꢀcyclesꢀ
determinedꢀbyꢀtheꢀstipulatedꢀburstꢀlength.ꢀHowever,ꢀtheꢀ
caseꢀwhereꢀtheꢀburstꢀlengthꢀisꢀaꢀfullꢀpageꢀisꢀanꢀexception.ꢀ
Inꢀthisꢀcaseꢀtheꢀwriteꢀcycleꢀmustꢀbeꢀterminatedꢀbyꢀexecutingꢀ
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
WRITE
DIN
0
DIN
1
DIN
2
DIN 3
BURST LENGTH
CAS ꢀlatencyꢀ=ꢀ2,3,ꢀburstꢀlengthꢀ=ꢀ4
30ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read With Auto-Precharge
Theꢀreadꢀwithꢀauto-prechargeꢀcommandꢀfirstꢀexecutesꢀaꢀ
burstꢀreadꢀoperationꢀandꢀthenꢀputsꢀtheꢀselectedꢀbankꢀinꢀ
theꢀprechargedꢀstateꢀautomatically.ꢀAfterꢀtheꢀprechargeꢀ
completes,ꢀ theꢀ bankꢀ goesꢀ toꢀ theꢀ idleꢀ state.ꢀ Thusꢀ thisꢀ
commandꢀperformsꢀaꢀreadꢀcommandꢀandꢀaꢀprechargeꢀ
commandꢀinꢀaꢀsingleꢀoperation.
three,ꢀtheꢀprechargeꢀoperationꢀstartsꢀonꢀtwoꢀclockꢀcyclesꢀ
beforeꢀtheꢀlastꢀburstꢀdataꢀisꢀoutputꢀ(tpqlꢀ=ꢀ–2).ꢀTherefore,ꢀ
theꢀselectedꢀbankꢀcanꢀbeꢀmadeꢀactiveꢀafterꢀaꢀdelayꢀofꢀtrpꢀ
fromꢀtheꢀstartꢀpositionꢀofꢀthisꢀprechargeꢀoperation.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
Duringꢀthisꢀoperation,ꢀtheꢀdelayꢀperiodꢀ(tpql)ꢀbetweenꢀtheꢀ
lastꢀburstꢀdataꢀoutputꢀandꢀtheꢀstartꢀofꢀtheꢀprechargeꢀopera-
tionꢀdiffersꢀdependingꢀonꢀtheꢀCASꢀlatencyꢀsetting.
Theꢀauto-prechargeꢀfunctionꢀisꢀinvalidꢀifꢀtheꢀburstꢀlengthꢀ
isꢀsetꢀtoꢀfullꢀpage.
WhenꢀtheꢀCASꢀlatencyꢀsettingꢀisꢀtwo,ꢀtheꢀprechargeꢀopera-
tionꢀstartsꢀonꢀoneꢀclockꢀcycleꢀbeforeꢀtheꢀlastꢀburstꢀdataꢀisꢀ
outputꢀ(tpqlꢀ=ꢀ–1).ꢀWhenꢀtheꢀCASꢀlatencyꢀsettingꢀisꢀ
CAS Latency
3
2
ꢀ
tpqlꢀ
–2ꢀ
–1ꢀ
CLK
COMMAND
DQ
READA 0
ACT 0
t
PQL
DOUT
0
D
OUT
1
D
OUT DOUT 3
2
tRP
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
COMMAND
DQ
ACT 0
READA 0
t
PQL
DOUT
0
D
OUT
1
D
OUT
2
DOUT 3
t
RP
READ WITH AUTO-PRECHARGE
(BANK 0)
PRECHARGE START
CAS latencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
31
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write With Auto-Precharge
The write with auto-precharge command first executes a
burst write operation and then puts the selected bank in
the precharged state automatically. After the precharge
completes the bank goes to the idle state. Thus this
command performs a write command and a precharge
command in a single operation.
Therefore, the selected bank can be made active after a
delay of tdal.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length
is set to full page.
During this operation, the delay period (tdal) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
The delay (tdal) is trp plus two CLK periods. That is, the
precharge operation starts two clock periods after the last
burst data input.
CAS Latency
3
2
tdal
2CLK
2CLK
+trp
+trp
CLK
ACT 0
COMMAND
DQ
WRITE A0
PRECHARGE START
DIN
0
D
IN
1
D
IN
2
DIN 3
t
RP
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tDAL
CAS latency = 2, burstlength = 4
CLK
ACT 0
COMMAND
DQ
WRITE A0
PRECHARGE START
DIN
0
D
IN
1
D
IN
2
DIN 3
t
RP
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tDAL
CAS latency = 3, burstlength = 4
32ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Interval Between Read Command
Aꢀ newꢀ commandꢀ canꢀ beꢀ executedꢀ whileꢀ aꢀ readꢀ cycleꢀ
isꢀinꢀprogress,ꢀi.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀWhenꢀ
theꢀsecondꢀreadꢀcommandꢀisꢀexecuted,ꢀafterꢀtheꢀCASꢀ
latencyꢀhasꢀelapsed,ꢀdataꢀcorrespondingꢀtoꢀtheꢀnewꢀreadꢀ
commandꢀisꢀoutputꢀinꢀplaceꢀofꢀtheꢀdataꢀdueꢀtoꢀtheꢀpreviousꢀ
readꢀcommand.
Theꢀintervalꢀbetweenꢀtwoꢀreadꢀcommandꢀ(tccd)ꢀmustꢀbeꢀ
atꢀleastꢀoneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
COMMAND
DQ
READ A0
READ B0
DOUT A0
DOUT B0
D
OUT B1
DOUT B3
DOUT B2
t
CCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Interval Between Write Command
Aꢀnewꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀisꢀinꢀ
progress,ꢀi.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀAtꢀtheꢀpointꢀtheꢀ
secondꢀwriteꢀcommandꢀisꢀexecuted,ꢀdataꢀcorrespondingꢀ
toꢀtheꢀnewꢀwriteꢀcommandꢀcanꢀbeꢀinputꢀinꢀplaceꢀofꢀtheꢀ
dataꢀforꢀtheꢀpreviousꢀwriteꢀcommand.
Theꢀintervalꢀbetweenꢀtwoꢀwriteꢀcommandsꢀ(tccd)ꢀmustꢀbeꢀ
atꢀleastꢀoneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITE A0 WRITE B0
DIN A0
D
IN B0
D
IN B1
D
IN B2
DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
33
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Interval Between Write and Read Commands
Aꢀnewꢀreadꢀcommandꢀcanꢀbeꢀexecutedꢀwhileꢀaꢀwriteꢀcycleꢀ
isꢀ inꢀ progress,ꢀ i.e.,ꢀ beforeꢀ thatꢀ cycleꢀ completes.ꢀ Dataꢀ
correspondingꢀtoꢀtheꢀnewꢀreadꢀcommandꢀisꢀoutputꢀafterꢀ
theꢀCASꢀlatencyꢀhasꢀelapsedꢀfromꢀtheꢀpointꢀtheꢀnewꢀreadꢀ
commandꢀwasꢀexecuted.ꢀTheꢀI/Onꢀpinsꢀmustꢀbeꢀplacedꢀinꢀ
theꢀHIGHꢀimpedanceꢀstateꢀatꢀleastꢀoneꢀcycleꢀbeforeꢀdataꢀ
isꢀoutputꢀduringꢀthisꢀoperation.
Theꢀintervalꢀ(tccd)ꢀbetweenꢀcommandꢀmustꢀbeꢀatꢀleastꢀ
oneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
CCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
34ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Interval Between Read and Write Commands
Aꢀreadꢀcommandꢀcanꢀbeꢀinterruptedꢀandꢀaꢀnewꢀwriteꢀ
commandꢀexecutedꢀwhileꢀtheꢀreadꢀcycleꢀisꢀinꢀprogress,ꢀ
i.e.,ꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀDataꢀcorrespondingꢀ
toꢀtheꢀnewꢀwriteꢀcommandꢀcanꢀbeꢀinputꢀatꢀtheꢀpointꢀ
newꢀwriteꢀcommandꢀisꢀexecuted.ꢀToꢀpreventꢀcollisionꢀ
betweenꢀinputꢀandꢀoutputꢀdataꢀatꢀtheꢀDQnꢀpinsꢀduringꢀ
thisꢀoperation,ꢀtheꢀ
outputꢀdataꢀmustꢀbeꢀmaskedꢀusingꢀtheꢀU/LDQMꢀpins.ꢀTheꢀ
intervalꢀ(tccd)ꢀbetweenꢀtheseꢀcommandsꢀmustꢀbeꢀatꢀleastꢀ
oneꢀclockꢀcycle.
Theꢀselectedꢀbankꢀmustꢀbeꢀsetꢀtoꢀtheꢀactiveꢀstateꢀbeforeꢀ
executingꢀthisꢀcommand.
CLK
tCCD
WRITE B0
COMMAND
U/LDQM
DQ
READ A0
HI-Z
DIN B0
D
IN B1
DIN B2
DIN B3
READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latencyꢀ=ꢀ2,ꢀ3,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
35
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Precharge
Read Cycle Interruption
Theꢀ prechargeꢀ commandꢀ setsꢀ theꢀ bankꢀ selectedꢀ byꢀ
pinꢀA11ꢀtoꢀtheꢀprechargedꢀstate.ꢀThisꢀcommandꢀcanꢀbeꢀ
executedꢀatꢀaꢀtimeꢀtras followingꢀtheꢀexecutionꢀofꢀanꢀactiveꢀ
commandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀselectedꢀbankꢀgoesꢀtoꢀ
theꢀidleꢀstateꢀatꢀaꢀtimeꢀtrpꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀ command,ꢀ andꢀ anꢀ activeꢀ commandꢀ canꢀ beꢀ
executedꢀagainꢀforꢀthatꢀbank.
Using the Precharge Command
Aꢀreadꢀcycleꢀcanꢀbeꢀinterruptedꢀbyꢀtheꢀexecutionꢀofꢀtheꢀ
prechargeꢀcommandꢀbeforeꢀthatꢀcycleꢀcompletes.ꢀTheꢀ
delayꢀtimeꢀ(trql)ꢀfromꢀtheꢀexecutionꢀofꢀtheꢀprechargeꢀ
commandꢀtoꢀtheꢀcompletionꢀofꢀtheꢀburstꢀoutputꢀisꢀtheꢀ
clockꢀcycleꢀofꢀCASꢀlatency.
IfꢀpinꢀA10ꢀisꢀlowꢀwhenꢀthisꢀcommandꢀisꢀexecuted,ꢀtheꢀbankꢀ
selectedꢀbyꢀpinꢀA11ꢀwillꢀbeꢀprecharged,ꢀandꢀifꢀpinꢀA10ꢀisꢀ
HIGH,ꢀbothꢀbanksꢀwillꢀbeꢀprechargedꢀatꢀtheꢀsameꢀtime.ꢀ
ThisꢀinputꢀtoꢀpinꢀA11ꢀisꢀignoredꢀinꢀtheꢀlatterꢀcase.
ꢀ
CAS Latency
3
2
ꢀ
trqlꢀ
3ꢀ
2
CLK
tRQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
RQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
36ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delaytime(twdl)fromtheprechargecommandtothepoint
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (tdpl) has elapsed. Therefore, the
precharge command must be executed two clock cycles
after the input of the last burst data item.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
CAS Latency
3
2
twdl
0
0
This precharge command and burst write command must
beofthesamebank, otherwiseitisnotprechargeinterrupt
but only another bank precharge of dual bank operation.
tdpl
2
2
CLK
tWDL=0
PRE 0
COMMAND
WRITE A0
DQM
DQ
DIN A0
DIN A1
DIN A2
DIN A3
MASKED BY DQM
PRECHARGE (BANK 0)
WRITE (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
DPL
COMMAND
DQ
WRITE A0
PRE 0
DIN A0
D
IN
A1 DIN A2
DIN A3
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
37
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
TheꢀSDRAMꢀcanꢀoutputꢀdataꢀcontinuouslyꢀfromꢀtheꢀburstꢀ
startꢀaddressꢀ(a)ꢀtoꢀlocationꢀa+255ꢀduringꢀaꢀreadꢀcycleꢀ
inꢀwhichꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀfullꢀpage.ꢀTheꢀSDRAMꢀ
repeatsꢀtheꢀoperationꢀstartingꢀatꢀtheꢀ256thꢀcycleꢀwithꢀtheꢀ
dataꢀoutputꢀreturningꢀtoꢀlocationꢀ(a)ꢀandꢀcontinuingꢀwithꢀa+1,ꢀ
a+2,ꢀa+3,ꢀetc.ꢀAꢀburstꢀstopꢀcommandꢀmustꢀbeꢀexecutedꢀ
toꢀterminateꢀthisꢀcycle.ꢀAꢀprechargeꢀcommandꢀmustꢀbeꢀ
executedꢀwithinꢀtheꢀACTꢀtoꢀPREꢀcommandꢀperiodꢀ(trasꢀ
max.)ꢀfollowingꢀtheꢀburstꢀstopꢀcommand.ꢀꢀ
Afterꢀtheꢀperiodꢀ(trbd)ꢀrequiredꢀforꢀburstꢀdataꢀoutputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀimpedanceꢀ
state.ꢀThisꢀperiodꢀ(trbd)ꢀisꢀtwoꢀclockꢀcycleꢀwhenꢀtheꢀ
CASꢀlatencyꢀisꢀtwoꢀandꢀthreeꢀclockꢀcycleꢀwhenꢀtheꢀCASꢀ
latencyꢀisꢀthree.
ꢀ
CAS Latency
3
2
ꢀ
trbdꢀ
3ꢀ
2
CLK
tRBD
BST
COMMAND
DQ
READ A0
D
OUT A0
DOUT A0
D
OUT A1
D
OUT A2
DOUT A3
HI-Z
BURST STOP
READ (CA=A, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
CLK
t
RBD
BST
COMMAND
DQ
READ A0
D
OUT A0
D
OUT A0
D
OUT A2
D
OUT A3
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
BURST STOP
CASꢀlatencyꢀ=ꢀ3,ꢀburstlengthꢀ=ꢀ4
38ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
mustꢀbeꢀexecutedꢀwithinꢀtheꢀACTꢀtoꢀPREꢀcommandꢀ
periodꢀ(trasꢀmax.)ꢀfollowingꢀtheꢀburstꢀstopꢀcommand.ꢀ
Afterꢀtheꢀperiodꢀ(twbd)ꢀrequiredꢀforꢀburstꢀdataꢀꢀinputꢀtoꢀ
stopꢀfollowingꢀtheꢀexecutionꢀofꢀtheꢀburstꢀstopꢀcommandꢀ
hasꢀelapsed,ꢀtheꢀwriteꢀcycleꢀterminates.ꢀThisꢀperiodꢀ
(twbd)ꢀisꢀzeroꢀclockꢀcycles,ꢀregardlessꢀofꢀtheꢀCASꢀ
latency.ꢀ
TheꢀSDRAMꢀcanꢀinputꢀdataꢀcontinuouslyꢀfromꢀtheꢀburstꢀ
startꢀaddressꢀ(a)ꢀtoꢀlocationꢀa+255ꢀduringꢀaꢀwriteꢀcycleꢀ
inꢀwhichꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀfullꢀpage.ꢀTheꢀSDRAMꢀ
repeatsꢀtheꢀoperationꢀstartingꢀatꢀtheꢀ256thꢀcycleꢀwithꢀ
dataꢀinputꢀreturningꢀtoꢀlocationꢀ(a)ꢀandꢀcontinuingꢀwithꢀ
a+1,ꢀa+2,ꢀa+3,ꢀetc.ꢀAꢀburstꢀstopꢀcommandꢀmustꢀbeꢀ
executedꢀtoꢀterminateꢀthisꢀcycle.ꢀAꢀprechargeꢀcommandꢀ
CLK
t
WBD=0
BST
INVALID DATA
tRP
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
DIN A1
DIN
A
DIN A1
DIN A2
READ (CA=A, BANK 0)
BURST STOP PRECHARGE (BANK 0)
Don't Care
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
outputꢀ controlꢀ operatesꢀ independentlyꢀ onꢀ aꢀ byteꢀ basisꢀ
withꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀoutputꢀ(pinsꢀ
DQ8-DQ15)ꢀ andꢀ theꢀ LDQMꢀ pinꢀ controllingꢀ lowerꢀ byteꢀ
outputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
Burstꢀdataꢀoutputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(masked)ꢀ
duringꢀaꢀreadꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀofꢀ
theꢀCASꢀlatency,ꢀtwoꢀclockꢀcyclesꢀ(tqmd)ꢀafterꢀoneꢀofꢀtheꢀ
U/LDQMꢀpinsꢀgoesꢀHIGH,ꢀtheꢀcorrespondingꢀoutputsꢀgoꢀ
toꢀtheꢀHIGHꢀimpedanceꢀstate.ꢀSubsequently,ꢀtheꢀoutputsꢀ
areꢀmaintainedꢀinꢀtheꢀhighꢀimpedanceꢀstateꢀasꢀlongꢀasꢀ
thatꢀU/LDQMꢀpinꢀremainsꢀHIGH.ꢀWhenꢀtheꢀU/LDQMꢀpinꢀ
goesꢀLOW,ꢀoutputꢀisꢀresumedꢀatꢀaꢀtimeꢀtqmdꢀlater.ꢀThisꢀ
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀoutputꢀbuffersꢀ
only,ꢀtheꢀreadꢀcycleꢀcontinuesꢀinternallyꢀand,ꢀinꢀparticular,ꢀ
incrementingꢀofꢀtheꢀinternalꢀburstꢀcounterꢀcontinues.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
39
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burstꢀdataꢀinputꢀcanꢀbeꢀtemporarilyꢀinterruptedꢀ(mutedꢀ)ꢀ
duringꢀaꢀwriteꢀcycleꢀusingꢀtheꢀU/LDQMꢀpins.ꢀRegardlessꢀ
ofꢀtheꢀCASꢀlatency,ꢀasꢀsoonꢀasꢀoneꢀofꢀtheꢀU/LDQMꢀpinsꢀ
goesꢀHIGH,ꢀtheꢀcorrespondingꢀexternallyꢀappliedꢀinputꢀ
dataꢀwillꢀnoꢀlongerꢀbeꢀwrittenꢀtoꢀtheꢀdeviceꢀinternalꢀcircuits.ꢀ
Subsequently,ꢀtheꢀcorrespondingꢀinputꢀcontinuesꢀtoꢀbeꢀ
mutedꢀasꢀlongꢀasꢀthatꢀU/LDQMꢀpinꢀremainsꢀHIGH.
thatꢀpinꢀisꢀdroppedꢀtoꢀLOWꢀandꢀdataꢀwillꢀbeꢀwrittenꢀtoꢀtheꢀ
device.ꢀThisꢀinputꢀcontrolꢀoperatesꢀindependentlyꢀonꢀaꢀbyteꢀ
basisꢀwithꢀtheꢀUDQMꢀpinꢀcontrollingꢀupperꢀbyteꢀinputꢀ(pinꢀ
DQ8ꢀtoꢀDQ15)ꢀandꢀtheꢀLDQMꢀpinꢀcontrollingꢀtheꢀlowerꢀ
byteꢀinputꢀ(pinsꢀDQ0ꢀtoꢀDQ7).
SinceꢀtheꢀU/LDQMꢀpinsꢀcontrolꢀtheꢀdeviceꢀinputꢀbuffersꢀ
only,ꢀ theꢀ cycleꢀ continuesꢀ internallyꢀ and,ꢀ inꢀ particular,ꢀ
incrementingꢀofꢀtheꢀinternalꢀburstꢀcounterꢀcontinues.
TheꢀSDRAMꢀwillꢀrevertꢀtoꢀacceptingꢀinputꢀasꢀsoonꢀasꢀ
CLK
COMMAND
UDQM
WRITE A0
t
DMD=0
LDQM
DQ8-DQ15
DQ0-DQ7
DIN A1
D
IN A3
DIN A2
D
IN A0
DIN A3
WRITE (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
Don't Care
DATA MASK (UPPER BYTE)
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Burst Read and Single Write
Theꢀburstꢀreadꢀandꢀsingleꢀwriteꢀmodeꢀisꢀsetꢀupꢀusingꢀtheꢀ
modeꢀregisterꢀsetꢀcommand.ꢀDuringꢀthisꢀoperation,ꢀtheꢀburstꢀ
readꢀcycleꢀoperatesꢀnormally,ꢀbutꢀtheꢀwriteꢀcycleꢀonlyꢀwritesꢀ
aꢀsingleꢀdataꢀitemꢀforꢀeachꢀwriteꢀcycle.ꢀTheꢀCASꢀlatencyꢀ
andꢀDQMꢀlatencyꢀareꢀtheꢀsameꢀasꢀinꢀnormalꢀmode.
CLK
COMMAND
DQ
WRITE A0
DIN A0
WRITE (CA=A, BANK 0)
CASꢀlatencyꢀ=ꢀ2,ꢀ3
40ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Bank Active Command Interval
thatꢀbankꢀwithinꢀtheACTꢀtoꢀPREꢀcommandꢀperiodꢀ(trasꢀmax).ꢀ
Alsoꢀnoteꢀthatꢀaꢀprechargeꢀcommandꢀcannotꢀbeꢀexecutedꢀ
forꢀanꢀactiveꢀbankꢀbeforeꢀtrasꢀ(min)ꢀhasꢀelapsed.
Whenꢀtheꢀselectedꢀbankꢀisꢀprecharged,ꢀtheꢀperiodꢀtrpꢀ
hasꢀelapsedꢀandꢀtheꢀbankꢀhasꢀenteredꢀtheꢀidleꢀstate,ꢀ
theꢀbankꢀcanꢀbeꢀactivatedꢀbyꢀexecutingꢀtheꢀactiveꢀ
command.ꢀIfꢀtheꢀotherꢀbankꢀisꢀinꢀtheꢀidleꢀstateꢀatꢀthatꢀ
time,ꢀtheꢀactiveꢀcommandꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbankꢀ
afterꢀtheꢀperiodꢀtrrdꢀhasꢀelapsed.ꢀAtꢀthatꢀpointꢀbothꢀ
banksꢀwillꢀbeꢀinꢀtheꢀactiveꢀstate.ꢀWhenꢀaꢀbankꢀactiveꢀ
commandꢀhasꢀbeenꢀexecuted,ꢀaꢀprechargeꢀcommandꢀ
mustꢀbeꢀexecutedꢀforꢀ
Afterꢀ aꢀ bankꢀ activeꢀ commandꢀ hasꢀ beenꢀ executedꢀ andꢀ
theꢀtrcdꢀperiodꢀhasꢀelapsed,ꢀreadꢀwriteꢀ(includingꢀauto-
precharge)ꢀcommandsꢀcanꢀbeꢀexecutedꢀforꢀthatꢀbank.
CLK
tRRD
COMMAND
ACT 0
ACT 1
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
CLK
COMMAND
tRCD
ACT 0
READ 0
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
CASꢀlatencyꢀ=ꢀ3
Clock Suspend
WhenꢀtheꢀCKEꢀpinꢀisꢀdroppedꢀfromꢀHIGHꢀtoꢀLOWꢀduringꢀaꢀ
readꢀorꢀwriteꢀcycle,ꢀtheꢀSDRAMꢀentersꢀclockꢀsuspendꢀmodeꢀ
onꢀtheꢀnextꢀCLKꢀrisingꢀedge.ꢀThisꢀcommandꢀꢀreducesꢀtheꢀ
deviceꢀpowerꢀdissipationꢀbyꢀstoppingꢀtheꢀdeviceꢀinternalꢀ
clock.ꢀClockꢀsuspendꢀmodeꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀ
pinꢀremainsꢀlow.ꢀInꢀthisꢀstate,ꢀallꢀinputsꢀotherꢀthanꢀCKEꢀ
pinꢀareꢀinvalidꢀandꢀnoꢀotherꢀcommandsꢀcanꢀbeꢀexecuted.ꢀ
Also,ꢀtheꢀdeviceꢀinternalꢀstatesꢀareꢀmaintained.ꢀWhenꢀtheꢀ
CKEꢀpinꢀgoesꢀfromꢀLOWꢀtoꢀHIGHꢀclockꢀsuspendꢀmodeꢀ
isꢀ terminatedꢀ onꢀ theꢀ nextꢀ CLKꢀ risingꢀ edgeꢀ andꢀ deviceꢀ
operationꢀresumes.
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀrecoveryꢀ
periodꢀ(tcka)ꢀhasꢀelapsed.
Sinceꢀthisꢀcommandꢀdiffersꢀfromꢀtheꢀself-refreshꢀcommandꢀ
describedꢀpreviouslyꢀinꢀthatꢀtheꢀrefreshꢀoperationꢀisꢀnotꢀ
performedꢀautomaticallyꢀinternally,ꢀtheꢀrefreshꢀoperationꢀ
mustꢀbeꢀperformedꢀwithinꢀtheꢀrefreshꢀperiodꢀ(tref).ꢀThusꢀ
theꢀmaximumꢀtimeꢀthatꢀclockꢀsuspendꢀmodeꢀcanꢀbeꢀheldꢀ
isꢀjustꢀunderꢀtheꢀrefreshꢀcycleꢀtime.
CLK
CKE
COMMAND
DQ
READ 0
D
OUT
0
DOUT
1
DOUT
2
DOUT 3
READ (BANK 0)
CLOCK SUSPEND
CAS latencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
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41
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
T0
T1
T2
T3
T10
T17
T18
T19
T20
CLK
tCHI
tCK
tCL
HIGH
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
ROW
CODE
CODE
CODE
A0-A9
A10
t
t
AS
AS
tAH
tAS
tAH
ROW
BANK 0 & 1
t
AH
BANK 1
A11
BANK 0
HIGH
DQM
DQ
WAIT TIME
T=100 µs
t
RAS
t
MCD
t
RP
tRC
tRC
t
RC
Undefined
Don't Care
CASꢀlatencyꢀ=ꢀ2,ꢀ3
42ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Power-Down Mode Cycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
t
CHI
t
CKH
tCKS
t
CK
t
CL
tCKS
CKE
CS
t
CKA
t
CKA
tCS
t
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
ROW
A0-A9
A10
tAS
tAH
BANK 0 & 1
BANK 0 OR 1
BANK 1
ROW
BANK 1
A11
BANK 0
BANK 0
DQM
DQ
EXIT
t
RAS
t
RP
POWER DOWN MODE
POWER DOWN MODE
t
RC
<
PRE
>
<SBY>
<ACT>
Undefined
Don't Care
CASꢀlatencyꢀ=ꢀ2,ꢀ3
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43
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Auto-Refresh Cycle
T0
T1
T2
T3
Tl
Tm
Tn
Tn+1
CLK
t
CHI
t
CK
tCKS
tCL
CKE
CS
t
CS
tCH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
ROW
A0-A9
A10
t
AS
tAH
ROW
BANK 0 & 1
BANK 1
A11
BANK 0
DQM
DQ
t
RC
t
RAS
RC
t
RP
t
RC
tRC
t
Undefined
Don't Care
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
44ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Self-Refresh Cycle
T0
T1
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
t
CHI
t
CKS
tCK
tCKS
t
CKS
tCL
CKE
CS
t
CKA
t
CKA
t
CS
t
CH
t
CS
tCH
RAS
t
CS
CS
tCH
CAS
WE
t
t
CH
A0-A9
A10
t
AS
tAH
BANK 0 & 1
A11
DQM
DQ
EXIT
SELF
REFRESH
t
RC
SELF REFRESH MODE
t
RC
t
RP
Undefined
Don't Care
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
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45
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
tAH
t
AS
BANK 1
BANK 1
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
BANK 0
tCH
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
RAS
t
RCD
t
CAC
tRQL
t
t
RAS
RC
t
RP
t
RC
t
<
PRE>
<
ACT>
<ACT
>
<READ>
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
46ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
COLUMN m
ROW
ROW
ROW
A0-A9
A10
tAS
tAH
AUTO PRE
ROW
tAH
tAS
BANK 1
BANK 1
BANK 1
A11
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
tRCD
tCAC
t
PQL
t
RAS
t
RAS
RC
t
RP
t
RC
t
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
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47
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T260
T261
T262
T263
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
t
AH
t
AS
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
tRCD
t
CAC
t
RBD
(BANK 0)
t
RP
t
RAS
(BANK 0)
t
RC
(BANK 0)
BST
PRE 0
ACT 0
READ0
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
48ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
ROW
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
AS
t
AH
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
BANK 0 OR 1
BANK 1
NO PRE
BANK 0
t
AH
t
AS
BANK 0
BANK 0
BANK 1
tCH
tCS
tQMD
DQM
t
AC
t
AC
t
AC
t
AC
tOH
tOH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
DQ
t
LZ
t
LZ
t
HZ
tHZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
t
CAC
t
CAC
t
RCD
(BANK 1)
t
RCD
(BANK 0)
RAS
(BANK 0)
(BANK 1)
(BANK 1)
t
RP
(BANK 0)
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<
ACT 0>
<ACT1>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<
PRE 0
>
<
ACT 0>
<PRE 1>
<
>
<
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
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49
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
tAS
tAH
ROW
ROW
COLUMN m
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
A10
A11
t
AH
tAS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
tDS
tDH
D
IN m+2
D
IN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
tRP
t
t
t
t
<
PRE
>
<
ACT>
<WRIT
>
<ACT>
PALL
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
50ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMN m
ROW
A0-A9
t
AS
t
AH
ROW
AUTO PRE
A10
A11
t
AH
tAS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
t
CH
DQM
DQ
t
DH
t
DS
DS
tDH
t
DS
t
DH
tDS
tDH
D
IN m+2
DIN
m
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
tRP
t
t
t
t
Undefined
CASꢀlatencyꢀ=ꢀ2,ꢀburstlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
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51
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CLK
t
CHI
tCKS
tCL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
COLUMN m
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
tAH
t
AS
BANK 0
BANK 0
t
CH
tCS
DQM
DQ
t
DH
tDS
tDS
t
DH
tDS
t
DH
t
DS
tDH
D
IN 0m+2
D
IN 0m
D
IN 0m-1
D
IN 0m
D
IN 0m+1
t
DPL
tRCD
t
RAS
RC
tRP
t
BST
PRE 0
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
52ꢀ
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Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Ping-Pong Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
t
AS
AUTO PRE
AUTO PRE
t
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
tAH
t
AS
BANK 0
BANK 0
BANK 1
tCH
t
CS
DQM
DQ
t
DS
t
DS
tDS
tDS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
t
DH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
tDPL
t
DPL
t
t
RCD
tRCD
(BANK 1)
(BANK 0)
t
RP
t
RAS
t
RAS
(BANK 0)
(BANK 0)
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<
ACT 0>
<ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1
>
<PRE 0
>
<ACT 0>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
53
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
tAH
NO PRE
NO PRE
BANK 1
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
tAH
tAS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
tCH
tCS
tQMD
DQM
DQ
tAC
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
tLZ
tHZ
tRCD
tRAS
tCAC
tCAC
tCAC
tRQL
tRP
tRC
<ACT>
<READ>
<READ>
<READ>
<PRE>
READA
PALL
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
54ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
NO PRE
CH
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
tQMD
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
LZ
tLZ
t
HZ
t
HZ
tRCD
t
CAC
t
CAC
t
CAC
t
RQL
tRAS
t
RP
tRC
<
ACT>
<READ
>
<
MASK>
<
READ, ENB
>
<
PRE>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
55
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
t
AS
t
AH
NO PRE
NO PRE
A10
A11
NO PRE
BANK 0 OR 1
BANK 1
t
AH
BANK 1
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
BANK 0
t
CH
tCS
DQM
DQ
t
DH
t
DS
tDS
t
DH
tDH
t
DS
t
DH
m
t
DS
t
DH
t
DS
tDH
t
DS
D
IN
D
IN n
D
IN n+1
D
IN
o
D
IN o+1
D
IN m+1
tRCD
t
DPL
t
RAS
tRP
t
RC
<ACT>
<WRIT
>
<
WRIT>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
56ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
t
AS
tAH
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 1OR 0
t
AS
t
AH
NO PRE
BANK 1
NO PRE
A10
A11
NO PRE
tAH
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
tCH
DQM
DQ
t
DH
t
DH
tDH
t
DS
tDS
t
DH
tDS
t
DH
tDS
tDS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
tRCD
t
DPL
tRAS
tRP
t
RC
<
ACT>
<
WRIT>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
57
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCKS
tCKH
tCL
tCK
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
AUTO PRE
tAH
ROW
A10
A11
NO PRE
BANK 1
tAH
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tAC
tCS
tQMD
DQM
DQ
tAC
tOH
tOH
D
OUT
m
DOUT m+1
tLZ
tHZ
tRCD
tCAC
tRAS
tRAS
tRP
tRC
tRC
<SPND>
<SPND>
<PRE>
<ACT 0>
<READ>
READ A
<ACT >
<PALL>
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
58ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCKS
CL
tCKH
t
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 1
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
tCS
DQM
DQ
t
DS
tDS
tDH
tDH
DIN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<
ACT>
<
WRIT, SPND
>
<ACT >
WRITA, SPND
PALL
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
59
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
NO PRE
BANK 1
tAH
t
AS
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
tCS
tCH
tQMD
DQM
DQ
tAC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
tLZ
t
RCD
t
CAC
t
RQL
RP
tCAC
t
RCD
RAS
RC
t
RAS
RC
t
t
t
t
<PRE 0
>
<
READ
>
<
ACT 0>
<
READ 0
>
<ACT >
READA
Undefined
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
60ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
t
AH
ROW
A10
A11
NO PRE
BANK 0 OR 1
BANK 0
NO PRE
BANK 1
t
AH
t
AS
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
tCH
BANK 0
CS
tCS
tCH
t
DQM
DQ
t
DH
DS
t
DH
DS
t
DH
tDH
t
DS
t
t
tDS
DIN 0m+2
D
IN 0m+1
D
IN 0m
D
IN 0n
t
RCD
t
RCD
RAS
RC
t
t
RAS
t
t
RP
RC
t
<
PRE 0>
<
WRIT
>
<ACT 0
>
<
WRIT 0
>
<ACT >
WRITA
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
61
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN m
ROW
ROW
ROW
A0-A9
AUTO PRE
t
AS
BANK 0 AND 1
BANK 0 OR 1
t
AH
ROW
A10
A11
NO PRE
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
UDQM
t
QMD
tCS
t
CH
LDQM
t
AC
t
HZ
tAC
t
AC
t
OH
tOH
t
LZ
t
OH
t
LZ
DQ8-15
DOUT
m
D
OUT m+2
DOUT m+3
t
AC
t
AC
t
OH
tOH
t
LZ
D
OUT m+1
DOUT m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
RAS
RC
t
RAS
t
RP
t
t
RC
t
<
PRE>
<
ACT>
<
READ
READA
>
<MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
62ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
t
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
ROW
A10
A11
NO PRE
t
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tCS
UDQM
tCS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
tDH
t
DH
t
DS
DH
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
DIN m+3
t
RCD
t
DPL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<ENB>
<
>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
63
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
(1)
(1)
t
AS
tAH
COLUMN m
COLUMN n
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
AUTO PRE
t
AH
NO PRE
BANK 1
A10
A11
NO PRE
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCS
t
CH
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
DS
t
OH
t
OH
t
OH
tOH
t
DH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
DIN
n
t
LZ
t
HZ
t
RCD
t
CAC
tDPL
t
RAS
RC
tRP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<ACT
>
<READ>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
64ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AH
NO PRE
BANK 1
ROW
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
tRCD
t
CAC
t
RQL
t
RAS
t
RAS
RC
t
RP
tRC
t
<
PRE>
<
ACT>
<READ>
<ACT>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
65
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Auto-Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
tCL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
AS
tAH
COLUMN
ROW
ROW
ROW
A0-A9
A10
AUTO PRE
t
AS
t
AH
ROW
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
A11
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
tLZ
t
HZ
tRCD
tRCD
tCAC
t
PQL
RP
t
RAS
t
RAS
RC
t
t
RC
t
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
66ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN
ROW
ROW
A0-A9
t
AS
t
AH
NO PRE
A10
A11
BANK 0 OR 1
BANK 0
tAH
t
AS
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
(BANK 0)
RAS
(BANK 0)
t
CAC
tRBD
(BANK 0)
t
RP
t
(BANK 0)
t
RC
(BANK 0)
BST
PRE 0
ACT 0
READ0
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
67
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Ping Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
tCK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CAS
WE
CS
t
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
COLUMN
ROW
ROW
ROW
A0-A9
AUTO PRE
AUTO PRE
t
AS
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
AS
BANK 0
BANK 0
BANK 1
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 1m
D
OUT 1m+1
t
CAC
t
RCD
t
HZ
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
(BANK 1)
(BANK 1)
t
CAC
t
t
RQL
(BANK 0)
RP
(BANK 0)
t
RCD
(BANK 0)
RAS
(BANK 0)
(BANK 0)
t
t
t
RAS
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
t
RP
(BANK 1)
(BANK1)
t
RC
(BANK 1)
<ACT 0>
<
ACT1>
<
READ 0
READA 0
>
<
READ 1
READA 1>
>
<
PRE 0>
<
PRE 1>
<
ACT 0>
<
>
<
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
68ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
t
CHI
tCKS
t
CK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
ROW
A10
A11
tAH
tAS
BANK 1
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
t
DS
t
DH
tDS
tDH
D
IN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
t
RP
t
t
t
t
<
PRE
>
<ACT>
<
WRIT>
<ACT>
PALL
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
69
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Auto-Precharge
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
A10
AUTO PRE
t
AS
t
AH
ROW
t
AH
t
AS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
t
CS
t
t
CH
DQM
DQ
t
DH
tDS
DS
t
DH
t
DS
t
DH
t
DS
tDH
DIN
m
DIN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DAL
t
RCD
RAS
RC
t
RP
t
t
t
t
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
70ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CLK
tCHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN
NO PRE
BANK 0
ROW
ROW
A0-A9
t
AS
t
AH
A10
A11
BANK 0 OR 1
BANK 0
t
AH
t
AS
BANK 0
t
CH
tCS
DQM
DQ
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
D
IN 0m
D
IN 0m+2
D
IN 0m-1
DIN 0m
D
IN 0m+1
t
RCD
tDPL
t
RAS
RC
tRP
t
BST
PRE 0
ACT 0
WRIT0
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
71
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
tCKS
tCK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
ROW
COLUMN
COLUMN
A0-A9
t
AS
AUTO PRE
AUTO PRE
t
AH
ROW
A10
A11
NO PRE
BANK 1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
tAH
t
AS
BANK 0
BANK 1
BANK 0
BANK 1
t
CH
tCS
DQM
DQ
t
DS
tDS
tDS
t
DS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
DPL
tDPL
(BANK 0)
t
t
RCD
t
RCD
RAS
RC
(BANK 1)
t
RP
t
RAS
t
(BANK 0)
(BANK 0)
t
RC
t
(BANK 0)
tRAS
(BANK 1)
t
RC
(BANK 1)
<ACT 0
>
<
ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1
>
<PRE 0
>
<ACT 0>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
72ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
tAS
tAH
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
NO PRE
BANK 1
NO PRE
NO PRE
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
t
CH
tCS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT n+1
D
OUT
o
D
OUT o+1
t
CAC
t
HZ
t
CAC
t
RCD
t
CAC
tRQL
t
RAS
t
RP
tRC
<
ACT>
<
READ>
<
READ>
<
READ
>
<
PRE>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
73
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Page Mode; Data Masking
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
tAH
NO PRE
NO PRE
NO PRE
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
t
CH
tQMD
t
CS
t
QMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
AC
t
OH
tLZ
t
OH
t
OH
t
OH
t
OH
D
OUT
m
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
HZ
t
CAC
t
CAC
tRCD
t
CAC
t
RQL
t
RAS
tRP
t
RC
<ACT>
<READ
>
<
READ>
<
READ, MASK
>
<ENB>
<
PRE
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
74ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Page Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
COLUMN n
COLUMN o
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
AUTO PRE
t
AH
ROW
NO PRE
BANK 1
NO PRE
A10
A11
NO PRE
t
AH
BANK 1
t
AS
BANK 1
BANK 0
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
DQM
DQ
t
DH
t
DS
t
DH
tDH
tDS
t
DH
tDS
t
DH
tDS
tDS
D
IN
m
D
IN n
D
IN
o
D
IN o+1
D
IN m+1
tRCD
t
DPL
tRAS
tRP
t
RC
<
ACT>
<
WRIT>
<WRIT
>
<MASK
>
<
WRIT
WRITA
>
<
PRE
PALL
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
75
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
tAS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 1OR 0
tAS
t
AH
ROW
NO PRE
NO PRE
NO PRE
t
AH
BANK 1
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
A11
BANK 0
BANK 0
tCS
tCH
DQM
DQ
t
DH
t
DH
t
DH
tDS
tDS
t
DH
t
DS
t
DH
tDS
t
DS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
t
RCD
t
DPL
tRAS
t
RP
t
RC
<
ACT>
<WRIT
>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
76ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
t
CKS
tCKH
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
t
AH
(1)
COLUMN m
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
AUTO PRE
t
AH
NO PRE
t
AH
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
tCS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
OH
t
OH
D
OUT
m
D
OUT m+1
t
LZ
t
HZ
t
RCD
t
CAC
t
RAS
RC
tRP
t
<
SPND>
<
SPND>
<
PRE
PALL
>
<ACT>
<
READ
>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
77
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Clock Suspend
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCKS
tCKH
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
ROW
NO PRE
BANK 1
tAH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CH
t
CS
DQM
DQ
tDS
tDS
tDH
tDH
D
IN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<ACT
>
<
WRIT, SPND
>
<ACT >
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
78ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Precharge Termination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
AS
t
AH
ROW
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
t
AH
t
AS
BANK 1
BANK 0
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
t
LZ
t
RCD
t
CAC
t
RQL
RP
t
RCD
RAS
RP
t
RAS
RC
t
t
t
t
<
PRE 0>
ACT 0
READ 0
ACT
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
79
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Precharge Termination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
tAH
(1)
COLUMN m
ROW
ROW
A0-A9
A10
t
AS
tAH
ROW
ROW
BANK 0 OR 1
BANK 0
NO PRE
tAH
t
AS
BANK 1
BANK 0
BANK 0
A11
t
CS
BANK 0
t
CS
t
CH
t
CH
DQM
DQ
t
DH
DS
t
DH
DS
tDH
tDS
t
t
DIN 0m+2
D
IN 0m+1
D
IN 0m
tRCD
tRCD
tRAS
t
RAS
t
RP
t
RC
tRP
ACT
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
80ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle / Byte Operation
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CAS
WE
t
CS
t
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
AS
AUTO PRE
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0
BANK 0
BANK 0
tCH
t
CS
t
QMD
QMD
UDQM
t
tCS
t
CH
LDQM
t
AC
t
HZ
t
AC
tAC
t
HZ
t
OH
t
LZ
tOH
tLZ
DQ8-15
DOUT
m
D
OUT m+2
D
OUT m+3
t
AC
t
AC
t
HZ
t
LZ
t
OH
t
OH
DOUT m+1
D
OUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
RP
t
RCD
RAS
RP
t
RAS
RC
t
t
t
t
<
PRE>
<ACT>
<
READ
READA
>
<
MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
81
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Write Cycle / Byte Operation
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
tCH
UDQM
t
CS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
DH
tDH
t
DH
t
DS
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
D
IN m+3
t
RCD
t
DPL
t
RCD
RAS
RP
t
RAS
RC
tRP
t
t
t
<
PRE
PALL
>
<ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<
ENB>
<
>
Undefined
Don't Care
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ4
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
82ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Read Cycle, Write Cycle / Burst Read, Single Write
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CAS
WE
t
CS
t
t
AS
AS
t
AH
(1)
(1)
COLUMN m
COLUMN n
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
AUTO PRE
t
AH
AH
NO PRE
BANK 1
NO PRE
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
DS
t
OH
t
OH
t
DH
D
OUT
m
D
OUT m+1
DIN
n
t
LZ
t
HZ
tRC
tCAC
t
DPL
t
RAS
RC
t
RP
t
<
WRIT
>
<
PRE
>
<
ACT>
<
READ>
Undefined
CAS ꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
Noteꢀ1:ꢀꢀA8,A9ꢀ=ꢀDon’tꢀCare.
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
83
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to 70°C
Frequency Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
200MHzꢀ
ꢀ
5ꢀ
ꢀ
IS42S16100F-5TLꢀ
IS42S16100F-5BLꢀ
50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
ꢀ
166MHzꢀ
ꢀ
6ꢀ
ꢀ
IS42S16100F-6TLꢀ
IS42S16100F-6BLꢀ
50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
143MHzꢀ
ꢀ
7ꢀ
ꢀ
IS42S16100F-7TLꢀ
IS42S16100F-7BLꢀ
50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballs
Industrial Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
166MHzꢀ
ꢀ
6ꢀ
ꢀ
IS42S16100F-6TLIꢀ
IS42S16100F-6BLIꢀ
50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
143MHzꢀ
ꢀ
7ꢀ
ꢀ
IS42S16100F-7TLIꢀ
IS42S16100F-7BLIꢀ
50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
60-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
Automotive Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
166MHzꢀ
ꢀ
6ꢀ
ꢀ
IS45S16100F-6TLA1ꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS45S16100F-6BLA1ꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
ꢀ
143MHzꢀ
7ꢀ
ꢀ
ꢀ
IS45S16100F-7CTLA1ꢀ 50-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ ꢀ
IS45S16100F-7TLA1ꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS45S16100F-7BLA1ꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
ꢀ
ORDERING INFORMATION - VDD = 1.8V
Commercial Range: 0°C to 70°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
133MHzꢀ
ꢀ
7.5ꢀ
ꢀ
IS42VS16100F-75TLꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS42VS16100F-75BLꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
100MHzꢀ
ꢀ
10ꢀ
ꢀ
IS42VS16100F-10TLꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS42VS16100F-10BLꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
Industrial Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
133MHzꢀ
ꢀ
7.5ꢀ
ꢀ
IS42VS16100F-75TLIꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS42VS16100F-75BLIꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballs
ꢀ
ꢀ
100MHzꢀ
ꢀ
10ꢀ
ꢀ
IS42VS16100F-10TLIꢀ 50-pinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS42VS16100F-10BLIꢀ 60-ballꢀBGA,ꢀSnAgCuꢀballs
84ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
85
Rev. A
06/13/2012
IS42/45S16100F, IS42VS16100F
86ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
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