IS42VS16400C1-12TLI [ISSI]
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM; 1梅格位×16位× 4银行( 64兆位)同步动态RAM型号: | IS42VS16400C1-12TLI |
厂家: | INTEGRATED SILICON SOLUTION, INC |
描述: | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
文件: | 总56页 (文件大小:491K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
IS42VS16400C1
ISSI
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
OCTOBER 2005
FEATURES
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42VS16400C1 is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance.ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
• Clock frequency: 100, 83, 66 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
• Programmable burst length
– (1, 2, 4, 8, full page)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
VDDQ
DQ12
DQ11
GNDQ
DQ10
DQ9
VDDQ
DQ8
GND
NC
• Programmable burst sequence:
Sequential/Interleave
2
3
4
5
• Self refresh modes
6
7
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
• Burst read/write and burst read/single write
operations capability
UDQM
CLK
CKE
NC
CAS
RAS
CS
• Burst termination by burst stop and precharge
command
BA0
BA1
A10
A11
A9
A8
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available
A0
A7
A1
A6
A2
A5
A3
A4
VDD
GND
PIN DESCRIPTIONS
WE
WriteEnable
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
Address Input
LDQM
UDQM
VDD
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Bank Select Address
Data I/O
System Clock Input
Clock Enable
GND
VDDQ
GNDQ
NC
Ground
CKE
Power Supply for DQ Pin
Ground for DQ Pin
NoConnection
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
CAS
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liabilityarisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingon
anypublishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
1
10/06/05
®
IS42VS16400C1
ISSI
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-accessmemorydesignedtooperatein1.8Vmemory
systems containing 67,108,864 bits. Internally configured
asaquad-bankDRAMwithasynchronousinterface. Each
16,777,216-bit bank is organized as 4,096 rows by 256
columns by 16 bits.
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation,theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
A10
12
V
DD/VDDQ
SELF
DATA OUT
BUFFER
REFRESH
GND/GNDQ
A11
CONTROLLER
16
16
A9
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
256K
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
8
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
PIN FUNCTIONS
Symbol
Pin No.
Type
Function (In Detail)
A0-A11
23 to 26
29 to 34
22, 35
Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
command(row-addressA0-A11)andREAD/WRITEcommand(A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
BA0, BA1
CAS
20, 21
17
Input Pin
Input Pin
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
37
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK
38
19
Input Pin
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
CS
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to
DQ15
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
DQ Pin
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM,
UDQM
15, 39
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
inconventionalDRAMs. Inwritemode, LDQMandUDQMcontroltheinputbuffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
RAS
WE
18
16
Input Pin
Input Pin
RAS,inconjunctionwithCASandWE,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
WE,inconjunctionwithRASandCAS,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
VDDQ
VDD
3, 9, 43, 49
1, 14, 27
Power Supply Pin VDDQ is the output buffer power supply.
Power Supply Pin VDD is the device internal power supply.
Power Supply Pin GNDQ is the output buffer ground.
Power Supply Pin GNDisthedeviceinternalground.
GNDQ
GND
6, 12, 46, 52
28, 41, 54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
3
10/06/05
®
IS42VS16400C1
ISSI
FUNCTION (In Detail)
READ
A0-A11 are address inputs sampled during the ACTIVE
(row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto PRECHARGE). A10 is sampled during
a PRECHARGE command to determine if all banks are to
be PRECHARGED (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A7 provides the starting column location. When
A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on
the DQM inputs two clocks earlier. When a given DQM
signal was registered HIGH, the corresponding DQ’s will
be High-Z two clocks later. DQ’s will provide valid data
when the DQM signal was registered LOW.
BankSelectAddress(BA0andBA1) defineswhichbankthe
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
CAS, in conjunction with the RAS and WE, forms the
device command. See the “Command Truth Table” for
details on device commands.
WRITE
The CKE input determines whether the CLK input is
enabled. The next rising edge of the CLK signal will be
valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down
mode, CLOCK SUSPEND mode, or SELF-REFRESH
mode. CKE is an asynchronous input.
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A7.
Whether or not AUTO-PRECHARGE is used is deter-
mined by A10.
CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroni-
zation with the rising edge of this pin.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
The CS input determines whether command input is
enabled within the device. Command input is enabled
when CS is LOW, and disabled with CS is HIGH. The
deviceremainsinthepreviousstatewhenCSisHIGH.DQ0
to DQ15 are DQ pins. DQ through these pins can be
controlled in byte units using the LDQM and UDQM pins.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
LDQMandUDQMcontrolthelowerandupperbytesofthe
DQ buffers. In read mode, LDQM and UDQM control the
output buffer. When LDQM or UDQM is LOW, the corre-
sponding buffer byte is enabled, and when HIGH, dis-
abled. The outputs go to the HIGH Impedance State when
LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM
control the input buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After executing
thiscommand,thenextcommandfortheselectedbanks(s)
is executed after passage of the period tRP, which is the
period required for bank precharging. Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
RAS, in conjunction with CAS and WE , forms the device
command. See the “Command Truth Table” item for
details on device commands.
AUTOPRECHARGE
WE , in conjunction with RAS and CAS , forms the device
command. See the “Command Truth Table” item for
details on device commands.
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 to enables the
AUTO PRECHARGE function in conjunction with a spe-
cific READ or WRITE command. For each individual
READ or WRITE command, auto precharge is either
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
4
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Rev. A
10/06/05
®
IS42VS16400C1
ISSI
BURST TERMINATE
enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.
TheBURSTTERMINATEcommandforciblyterminatesthe
burst read and write operations by truncating either fixed-
length or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMI-
NATE.
AUTO REFRESH COMMAND
COMMAND INHIBIT
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC)
is required for a single refresh operation, and no other
commands can be executed during this period. This com-
mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are “Don’t
Care”. This command corresponds to CBR Auto-refresh.
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
SELFREFRESH
LOAD MODE REGISTER
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become “Don’t
Care”. The device must remain in self refresh mode for a
minimum period equal to tRAS or may remain in self refresh
mode for an indefinite period beyond that. The SELF-
REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
anyotherpins.Thenextcommandcannotbeexecuteduntil
thedeviceinternalrecoveryperiod(tRC)haselapsed.Once
CKE goes HIGH, the NOP command must be issued
(minimum of two clocks) to provide time for the completion of
anyinternalrefreshinprogress.Aftertheself-refresh,since
it is impossible to determine the address of the last row to
berefreshed,anAUTO-REFRESHshouldimmediatelybe
performed for all addresses.
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
5
10/06/05
®
IS42VS16400C1
ISSI
TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
CS
H
L
RAS CAS
WE DQM
ADDR
DQs
X
COMMAND INHIBIT (NOP)
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
NO OPERATION (NOP)
X
ACTIVE (Select bank and activate row)(3)
READ (Select bank/column, start READ burst)(4)
WRITE(Selectbank/column, startWRITEburst)(4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)(5)
AUTO REFRESH or SELF REFRESH(6,7)
(Enter self refresh mode)
L
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
L
H
H
H
L
L/H(8)
L/H(8)
X
L
L
Valid
L
H
H
L
L
Active
L
L
X
Code
X
X
L
L
H
X
X
LOAD MODE REGISTER(2)
Write Enable/Output Enable(8)
Write Inhibit/Output High-Z(8)
L
L
L
L
X
L
Op-Code
X
—
—
—
—
—
—
—
—
—
—
Active
High-Z
H
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
TRUTH TABLE – CKE (1-4)
CURRENT STATE
Power-Down
COMMANDn
ACTIONn
CKEn-1
CKEn
X
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
L
L
L
L
Self Refresh
X
Clock Suspend
Power-Down(5)
Self Refresh(6)
Clock Suspend(7)
All Banks Idle
All Banks Idle
Reading or Writing
X
L
L
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
L
H
H
H
L
L
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
L
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
H
H
H
H
L
L
SeeTRUTHTABLE–CURRENTSTATEBANKn,COMMANDTOBANKn
H
NOTES:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tCKS is met)
.
6. Exiting self refresh at clock edge n will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands
should be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENT STATE
Any
COMMAND (ACTION)
CS RAS CAS WE
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
Idle
AUTO REFRESH(7)
L
LOAD MODE REGISTER(7)
L
L
PRECHARGE(11)
L
H
L
L
Row Active
READ (Select column and start READ burst)(10)
WRITE (Select column and start WRITE burst)(10)
PRECHARGE (Deactivate row in bank or banks)(8)
READ (Select column and start new READ burst)(10)
WRITE (Select column and start WRITE burst)(10)
PRECHARGE (Truncate READ burst, start PRECHARGE)(8)
BURST TERMINATE(9)
H
H
L
H
L
L
H
L
L
Read
H
H
L
H
L
(Auto
L
Precharge
Disabled)
Write
H
H
L
L
H
H
H
L
L
READ (Select column and start READ burst)(10)
WRITE (Select column and start new WRITE burst)(10)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8)
BURST TERMINATE(9)
H
L
(Auto
L
Precharge
Disabled)
H
H
L
H
L
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Rev. A
7
10/06/05
®
IS42VS16400C1
ISSI
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after tXSR has been met (if the
previous state was SELF REFRESH).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Currentstatedefinitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to
the other bank are determined by its current state and CURRENT STATE BANK n truth tables.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will
be in the row active state.
Readw/Auto
PrechargeEnabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.
Writew/Auto
PrechargeEnabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the
SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once
tMRD is met, the SDRAM will be in the all banks idle state.
PrechargingAll: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs
or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
8
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Rev. A
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®
IS42VS16400C1
ISSI
(1-6)
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m
CURRENT STATE
Any
COMMAND (ACTION)
CS RAS CAS WE
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)(7)
WRITE (Select column and start WRITE burst)(7)
PRECHARGE
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
Idle
Row
Activating,
Active, or
Precharging
Read
H
H
L
L
H
H
L
L
ACTIVE (Select and activate row)
L
H
H
L
(Auto
READ (Select column and start new READ burst)(7,10)
WRITE (Select column and start WRITE burst)(7,11)
PRECHARGE(9)
H
H
L
Precharge
Disabled)
Write
L
H
H
L
L
ACTIVE (Select and activate row)
L
H
H
L
(Auto
READ (Select column and start READ burst)(7,12)
WRITE (Select column and start new WRITE burst)(7,13)
PRECHARGE(9)
H
H
L
Precharge
Disabled)
Read
L
H
H
L
L
ACTIVE (Select and activate row)
L
H
H
L
(With Auto
Precharge)
READ (Select column and start new READ burst)(7,8,14)
WRITE (Select column and start WRITE burst)(7,8,15)
PRECHARGE(9)
H
H
L
L
H
H
L
L
Write
ACTIVE (Select and activate row)
L
H
H
L
(With Auto
Precharge)
READ (Select column and start READ burst)(7,8,16)
WRITE (Select column and start new WRITE burst)(7,8,17)
PRECHARGE(9)
H
H
L
L
H
L
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after tXSR has been met (if the previous
state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown
are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are
covered in the notes below.
3. Currentstatedefinitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Readw/Auto
PrechargeEnabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.
Writew/Auto
PrechargeEnabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been
met. Once tRP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
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7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
rupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later (Consecutive READ Bursts).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
buscontention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m (Fig CAP 3).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where t WR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).
10
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®
IS42VS16400C1
ISSI
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameters
Rating
Unit
VDD MAX
VDDQ MAX
VIN
Maximum Supply Voltage
–0.5 to +2.6
–0.5 to +2.6
–0.5 to +2.6
1
V
V
Maximum Supply Voltage for Output Buffer
Input Voltage
V
PD MAX
ICS
AllowablePowerDissipation
OutputShortedCurrent
W
mA
50
TOPR
OperatingTemperature
Com
Ind.
0 to +70
-40 to +85
°C
°C
TSTG
StorageTemperature
–55 to +150
°C
(2)
DC RECOMMENDED OPERATING CONDITIONS
Commercial (TA = 0°C to +70°C), Industrial (TA = -40°C to +85°C)
Symbol
VDD,VDDQ
VIH
Parameter
Min.
1.7
Typ.
1.8
—
Max.
Unit
V
Supply Voltage
InputHighVoltage(3)
InputLowVoltage(4)
1.9
VDDQ + 0.3
+0.3
0.8 x VDDQ
-0.3
V
VIL
—
V
(1,2)
CAPACITANCE CHARACTERISTICS
(VDD = 1.8V, TA = +25°C, f = 1 MHz)
Symbol
CIN1
Parameter
Min.
2.5
Max.
Unit
pF
Input Capacitance: CLK
4.0
5.0
6.5
CIN2
Input Capacitance: (A0-A11, CKE, CS, RAS, CAS, WE, LDQM, UDQM) 2.5
DataInput/OutputCapacitance:DQ0-DQ15 4.0
pF
CI/O
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to Vss.
3. VIH (max) = 2.2V with a pulse width ≤ 3 ns.
4. VIL (min) = -1.0V with a pulse width ≤ 3 ns.
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IS42VS16400C1
ISSI
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Continued on next page.
Symbol Parameter
TestCondition
Min.
Max.
Unit
IIL
InputLeakageCurrent
0V ≤ VIN ≤ VDD, with pins other than
the tested pin at 0V
–1.0
1.0
µA
IOL
OutputLeakageCurrent
Output is disabled, 0V ≤ VOUT ≤ VDD
–1.5
0.9 x VDDQ
—
1.5
—
µA
V
VOH
VOL
Output High Voltage Level(1)
Output Low Voltage Level(1)
IOH = –0.1 mA
IOL = 0.1 mA
0.2
V
12
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IS42VS16400C1
ISSI
DC ELECTRICAL CHARACTERISTICS(4) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
TestCondition
Min.
Max.
Unit
ICC1
OperatingCurrent(1,2)
OneBankOperation,
BurstLength=1
CAS Latency = 3
CAS Latency = 2
tCK = 10 ns
tCK = ∞
—
35
mA
tRC ≥ tRC (min.)
IOUT = 0mA
—
—
—
—
—
—
—
—
—
40
0.3
0.3
7
ICC2P
PrechargeStandbyCurrent
(InPower-DownMode)
CKE ≤ VIL (MAX)
mA
mA
mA
mA
mA
mA
mA
mA
ICC2PS
ICC2N
PrechargeStandbyCurrent
(InPower-DownMode)
Active Standby Current(3)
(InNonPower-DownMode)
CKE ≤ VIL (MAX)
CLK ≤ VIL (MAX)
CKE ≥ VIH (MIN)
CS ≥ VIH (MIN),
tCK = 10 ns
tCK = ∞
ICC2NS
ICC3P
Active Standby Current
(InNonPower-DownMode)
CKE ≥ VIH (MIN)
Inputs are stable
2
Active Standby Current
(InNonPower-DownMode)
CKE ≤ VIL (MAX)
tCK = 10 ns
tCK = ∞
6
ICC3PS
ICC3N
Active Standby Current
(InNonPower-DownMode)
Active Standby Current(3)
(InNonPower-DownMode)
CKE ≤ VIL (MAX)
CLK ≤ VIL (MAX)
5
CKE ≥ VIH (MIN)
CS ≥ VIH (MIN)
tCK = 10 ns
tCK = ∞
12
10
ICC3NS
Active Standby Current
(InNonPower-DownMode)
Inputs are stable
CKE ≥ VIH (MIN)
CLK ≤ VIL (MAX)
ICC4
OperatingCurrent
(In Burst Mode)(1,3)
tCK = tCK (MIN)
IOUT = 0mA
CAS latency = 2, 3
CAS latency = 2, 3
—
50
mA
Page Burst
All Banks activated
ICC5
Auto-RefreshCurrent
Self-RefreshCurrent
tRC = tRC (MIN)
—
—
40
mA
µA
ICC6
CKE ≤ 0.2V
170
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between VDD and Vss for each memory
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
3. Inputs changed once every two clocks.
4. Not all parameters are tested at the wafer level, but the parameters have been characterized previously.
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(1,2,3,6)
AC CHARACTERISTICS
-10
-12
Symbol Parameter
Min. Max.
Min.
Max.
Units
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
10
12
—
—
12
15
—
—
ns
ns
tAC3
tAC2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
—
—
8
9
—
—
9
10
ns
ns
tCHI
tCL
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
3
3
—
—
3
3
—
—
ns
ns
tOH3
tOH2
CAS Latency = 3
CAS Latency = 2
2
2
—
—
2
2
—
—
ns
ns
tLZ
Output LOW Impedance Time
Output HIGH Impedance Time(5)
0
—
0
—
ns
tHZ3
tHZ2
CAS Latency = 3
CAS Latency = 2
—
—
8
9
—
—
9
10
ns
ns
tDS
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
2
—
—
—
—
—
—
—
—
—
—
2
1
3
1
3
1
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
1
tAS
3
tAH
1
tCKS
tCKH
tCKA
tCS
CKE Setup Time
3
CKE Hold Time
1
CKE to CLK Recovery Delay Time
1CLK+3
1CLK+3
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
3
1
3
1
tCH
tRC
94
94
tRAS
tRP
50 100,000
50 100,000
Command Period (PRE to ACT)
30
30
—
—
—
—
30
30
—
—
—
—
tRCD
tRRD
tDPL3
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
18
18
Input Data To Precharge
Command Delay time
CAS Latency = 3
2CLK
2CLK
tDPL2
tDAL3
CAS Latency = 2
CAS Latency = 3
2CLK
—
2CLK
—
—
ns
ns
Input Data To Active / Refresh
2CLK+tRP —
2CLK+tRP
Command Delay time (During Auto-Precharge)
CAS Latency = 2
tDAL2
tT
2CLK+tRP —
2CLK+tRP
—
5
ns
ns
Transition Time
0.5
—
5
0.5
—
tREF
Refresh Cycle Time (4096)
64
64
ms
Notes:
1. Thepower-on sequence must be executed before starting memory operation.
2. Measured with t = 0.5 ns.
T
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to become high impedance.
6. Not all parameters are tested at the wafer level, but the parameters have been characterized previously.
14
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IS42VS16400C1
ISSI
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-10
10
-10
12
-12
12
-12
15
UNITS
—
—
Clock Cycle Time
ns
Operating Frequency
100
83
83
66
MHz
tCAC
tRCD
tRAC
CAS Latency
3
3
2/3
3
3
3
2/3
2
cycle
cycle
cycle
Active Command To Read/Write Command Delay Time
RAS Latency (tRCD + tCAC)
CAS Latency = 3
CAS Latency = 2
6
—
6
5
6
—
5
4
tRC
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
10
5
8
5
3
2
1
8
3
3
2
1
7
2
2
2
1
cycle
cycle
cycle
cycle
cycle
tRAS
tRP
Command Period (PRE to ACT)
3
tRRD
tCCD
Command Period (ACT[0] to ACT [1])
2
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
tDPL
tDAL
Input Data To Precharge Command Delay Time
2
5
2
5
2
5
2
4
cycle
cycle
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
tRBD
tWBD
tRQL
tWDL
tPQL
Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 3
3
—
3
2
3
—
3
2
cycle
cycle
cycle
cycle
cycle
(Read)
CAS Latency = 2
Burst Stop Command To Input in Invalid Delay Time
(Write)
0
0
0
0
Precharge Command To Output in HIGH-Z Delay Time CAS Latency = 3
3
—
3
2
3
—
3
2
(Read)
CAS Latency = 2
Precharge Command To Input in Invalid Delay Time
(Write)
0
0
0
0
Last Output To Auto-Precharge Start Time (Read)
CAS Latency = 3
CAS Latency = 2
-2
—
-2
-1
-2
—
-2
-1
tQMD
tDMD
tMRD
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
2
0
2
2
0
2
2
0
2
2
0
2
cycle
cycle
cycle
Mode Register Set To Command Delay Time
AC TEST CONDITIONS (Input/Output Reference Level: 0.9V)
Output Load
Input
t
CK
t
CL
t
CHI
1.8V
0.9V
50 Ω
CLK
0.0V
0.5 x VDDQ V
t
CS
I/O
t
CH
1.8V
0.9V
0.0V
INPUT
30 pF
t
AC
t
OH
0.9V
0.9V
OUTPUT
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IS42VS16400C1
ISSI
Initialization
FUNCTIONALDESCRIPTION
SDRAMs must be powered up and initialized in a
predefined manner.
The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank
DRAMs which operate at 1.8V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 4,096 rows by 256 columns by 16 bits.
The 64M SDRAM is initialized after the power is applied
to VDD and VDDQ (simultaneously), and the clock is stable
with DQM High and CKE High.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
androwtobeaccessed(BA0andBA1selectthebank,A0-A11
select the row). The address bits (A0-A7) registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or aNOP. The COMMAND
INHIBITorNOPmaybeappliedduringthe100µsperiodand
continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
havingbeenapplied,aPRECHARGEcommandshouldbe
appliedoncethe100µsdelayhasbeensatisfied. Allbanks
must be precharged. This will leave all banks in an idle
state, after which at least two AUTO REFRESH cycles must
be performed. After the AUTO REFRESH cycles are com-
plete, the SDRAM is then ready for mode register program-
ming.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
The mode register should be loaded prior to applying any
operational command because it will power up in an
unknownstate.AftertheLoadModeRegistercommand,at
least two NOP commands must be asserted prior to any
command.
16
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REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operatingmodeandawriteburstmode,asshowninMODE
REGISTERDEFINITION.
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst (sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
All Other States Reserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
1
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Burst Length
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A7 (x16) when the burst length is set to two; by A2-A7
(x16) when the burst length is set to four; and by A3-A7
(x16) when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in MODE REGISTER DEFINITION. The burst
length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary
burst lengths.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
BURST DEFINITION
Burst
StartingColumn
Address
Order of Accesses Within a Burst
Length
Type=Sequential
Type=Interleaved
A0
2
4
0
1
0-1
1-0
0-1
1-0
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A2
A1
0
A0
0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotSupported
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
1
0
1
1
Full
Page
(y)
n = A0-A7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
(location0-y)
Cn…
18
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®
IS42VS16400C1
ISSI
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registrationofaREADcommandandtheavailabilityofthefirst
pieceofoutputdata.Thelatencycanbesettotwoorthreeclocks.
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid
by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as shown
in CAS Latency diagrams. The Allowable Operating
Frequency table indicates the operating frequencies at
which each CAS latency setting can be used.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
appliestobothREADandWRITEbursts;whenM9=1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
10
CAS Latency = 2
CAS Latency = 3
83
66
100
83
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
12
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8
to zero; the other combinations of values for M7 and M8 are
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
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IS42VS16400C1
ISSI
ActivatingSpecificRowWithinSpecificBank
CLK
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
HIGH - Z
CKE
CS
RAS
CAS
WE
Afteropeningarow(issuinganACTIVEcommand), aREAD
or WRITE command may be issued to that row, subject to
the tRCD specification. Minimum tRCD should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which
covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The
same procedure is used to convert other specification
limits from time units to clock cycles).
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by tRRD.
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
tRCD
DON'T CARE
20
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IS42VS16400C1
ISSI
READS
READ COMMAND
READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram.
CLK
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled
or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ commands
used in the following illustrations, auto precharge is disabled.
HIGH-Z
CKE
CS
RAS
During READ bursts, the valid data-out element from the
starting column address will be available following the
CAS latency after the READ command. Each subsequent
data-out element will be valid by the next positive clock
edge. The CAS Latency diagram shows general timing
for each possible CAS latency setting.
CAS
WE
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8, A9, A11
A10
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page
burst will continue until terminated. (At the end of the page,
it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst or
the last desired data element of a longer burst which is
being truncated.
NO PRECHARGE
BANK ADDRESS
BA0, BA1
The DQM input is used to avoid I/O contention, as shown
in Figures RW1 and RW2. The DQM signal must be
asserted (HIGH) at least three clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal,
provided the DQM was active on the clock just prior to the
WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For
example, if DQM was LOW during T4 in Figure RW2, then
the WRITEs at T5 and T7 would be valid, while the WRITE
at T6 would be invalid.
The new READ command should be issued x cycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Consecutive READ Bursts for CAS
latencies of two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer burst.
The 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated
on any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to the
same bank, as shown in Random READ Accesses, or each
subsequent READ may be performed to a different bank.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediately following the last (or last desired) data
element from the READ burst, provided that I/O contention
can be avoided. In a given system design, there may be
a possibility that the device driving the input data will go
Low-Z before the SDRAM DQs go High-Z. In this case, at
least a single-cycle delay should occur between the last
read data and the WRITE command.
Afixed-lengthREADburstmaybefollowedby, ortruncated
with, aPRECHARGEcommandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the
samebank.ThePRECHARGEcommandshouldbeissued
xcyclesbeforetheclockedgeatwhichthelastdesireddata
elementisvalid,wherexequalstheCASlatencyminusone.
ThisisshownintheREADtoPRECHARGEdiagramforeach
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IS42VS16400C1
ISSI
possible CAS latency; data elementn + 3 is either the last of
a burst of four or the last desired of a longer burst. Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met. Note that part
of the row precharge time is hidden during the access of the
last data element(s).
fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The
BURSTTERMINATEcommandshouldbeissuedxcycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in the READ Burst Termination
diagram for each possible CAS latency; data element n +
3 is the last desired data element of a longer burst.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
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IS42VS16400C1
ISSI
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
x=1 cycle
BANK,
COL n
BANK,
COL b
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 3
DON'T CARE
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IS42VS16400C1
ISSI
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
24
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IS42VS16400C1
ISSI
RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
DOUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
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IS42VS16400C1
ISSI
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
x = 1 cycle
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
26
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IS42VS16400C1
ISSI
READ Burst Termination
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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IS42VS16400C1
ISSI
WRITEs
An example is shown in WRITE to WRITE diagram. Data n
+ 1 is either the last of a burst of two or the last desired of
alongerburst.The64MbSDRAMusesapipelinedarchitec-
ture and therefore does not require the 2n rule associated
with a prefetch architecture. A WRITE command can be
initiated on any clock cycle following a previous WRITE
command.Full-speedrandomwriteaccesseswithinapage
can be performed to the same bank, as shown in Random
WRITE Cycles, or each subsequent WRITE may be per-
formed to a different bank.
WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.
WRITE Command
CLK
HIGH - Z
CKE
Data for any WRITE burst may be truncated with a subse-
quentREADcommand, anddataforafixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be ex-
ecuted. An example is shown in WRITE to READ. Data n +
1 is either the last of a burst of two or the last desired of a
longerburst.
CS
RAS
CAS
WE
Dataforafixed-lengthWRITEburstmaybefollowedby, or
truncatedwith,aPRECHARGEcommandtothesamebank
(providedthatautoprechargewasnotactivated),andafull-
page WRITE burst may be truncated with a PRECHARGE
commandtothesamebank.ThePRECHARGEcommand
should be issued tWR after the clock edge at which the last
desiredinputdataelementisregistered.Theautoprecharge
mode requires a tWR of at least one clock plus time,
regardless of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask input
datafortheclockedgepriorto,andtheclockedgecoincident
with, the PRECHARGE command. An example is shown in
theWRITEtoPRECHARGEdiagram.Datan+1iseitherthe
last of a burst of two or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent com-
mand to the same bank cannot be issued until tRP is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8, A9, A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
The starting column and bank addresses are provided with
theWRITEcommand,andautoprechargeiseitherenabled
ordisabledforthataccess. Ifautoprechargeisenabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
In the case of a fixed-length burst being executed to comple-
tion, a PRECHARGE command issued at the optimum time
(as described above) provides the same operation that would
result from the same fixed-length burst with auto precharge.
The disadvantage of the PRECHARGE command is that it
requiresthatthecommandandaddressbusesbeavailableat
theappropriatetimetoissuethecommand;theadvantageof
thePRECHARGEcommandisthatitcanbeusedtotruncate
fixed-lengthorfull-pagebursts.
During WRITE bursts, the first valid data-in element will be
registeredcoincidentwiththeWRITEcommand. Subsequent
data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated,
theDQswillremainHigh-Zandanyadditionalinputdatawill
be ignored (see WRITE Burst). A full-page burst will
continueuntilterminated. (Attheendofthepage, itwillwrap
to column 0 and continue.)
Fixed-length or full-page WRITE bursts can be truncated
withtheBURSTTERMINATEcommand.Whentruncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
data written (provided that DQM is LOW at that time) will
be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data n is the last desired data element
of a longer burst.
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITEcommand.ThenewWRITEcommandcanbeissued
on any clock following the previous WRITE command, and
the data provided coincident with the new command applies
to the new command.
28
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IS42VS16400C1
ISSI
WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE to WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
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IS42VS16400C1
ISSI
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
ACTIVE
NOP
NOP
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
t
WR
DIN
n
DIN n+1
CAS Latency - 2
DON'T CARE
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IS42VS16400C1
ISSI
WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
t
WR
DIN
n
DIN n+1
CAS Latency - 3
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
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IS42VS16400C1
ISSI
PRECHARGECommand
PRECHARGE
The PRECHARGE command (see figure) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after
the PRECHARGE command is issued. Input A10 deter-
mines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Onceabankhasbeenprecharged,itisintheidlestateand
must be activated prior to any READ or WRITE com-
mands being issued to that bank.
CLK
HIGH - Z
CKE
CS
RAS
CAS
WE
POWER-DOWN
A0-A9, A11
ALL BANKS
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings
while in standby. The device may not remain in the power-
down state longer than the refresh period (64ms) since no
refresh operations are performed in this mode.
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See figure below.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
t
t
t
RCD
RAS
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
DON'T CARE
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IS42VS16400C1
ISSI
CLOCKSUSPEND
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
presentontheDQpinsremainsdriven;andburstcounters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
33
10/06/05
®
IS42VS16400C1
ISSI
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaREADonbankn, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
CONCURRENT AUTO PRECHARGE
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
t
RP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DOUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
DOUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
WRITE with Auto Precharge
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
WRITE to bank m will interrupt a WRITE on bank n when
3. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaWRITEonbanknwhen
registered, with the data-out appearing CAS latency later.
The PRECHARGE to bank n will begin after tWR is met,
wheretWR beginswhentheREADtobankmisregistered.
The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
A
registered. The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
tRP - BANK n
Internal States
t
RP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
WR - BANK n
Precharge
t
t
RP - BANK n
Internal States
t
RP - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
35
10/06/05
®
IS42VS16400C1
ISSI
INITIALIZE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
tCH
To+1
tCL
Tp+1
Tp+2
Tp+3
tCK
CLK
CKE
tCKS tCKH
tCMH tCMS
tCMH tCMS
PRECHARGE
tCMH tCMS
AUTO
AUTO
Load MODE
REGISTER
COMMAND
NOP
NOP
NOP
NOP
ACTIVE
REFRESH
REFRESH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
tAS tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
BA0, BA1
DQ
tRP
tRC
tRC
tMRD
T
Power-up: VCC
and CLK stable all banks
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
DON'T CARE
At least 2 Auto-Refresh Commands
T = 100µs Min.
Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.
36
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
t
CKS
t
CKH
t
CKS
t
CKS
CKE
t
CMS
t
CMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
t
AH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
Precharge all
active banks
All banks idle, enter
power-down mode
power-down mode
DON'T CARE
Exit power-down mode
CAS latency = 2, 3
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Rev. A
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®
IS42VS16400C1
ISSI
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
t
CH
CLK
CKE
t
CKS
t
CKH
t
CKS
t
CKH
t
CMS
tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
CMS tCMH
DQM/
DQML, DQMH
t
AS
tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
t
AS
t
AH
t
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
tDH
t
AC
t
AC
t
HZ
DQ
DOUT
m
DOUT m+1
DOUT e
DOUT e+1
t
LZ
tOH
DON'T CARE
UNDEFINED
CAS latency = 3, burst length = 2
38
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
AUTO-REFRESHCYCLE
T0
T1
T2
Tn+1
To+1
t
CK
t
CL
t
CH
CLK
t
CKS CKH
t
CKE
t
CMS
t
CMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
t
AS
t
AH
High-Z
t
RP
t
RC
t
RC
DON'T CARE
CAS latency = 2, 3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
39
10/06/05
®
IS42VS16400C1
ISSI
SELF-REFRESHCYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
t
CH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
≥ tRAS
t
CKS
t
CMS
t
CMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
t
AH
BA0, BA1
DQ
BANK
High-Z
t
XSR
t
RP
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
CAS latency = 2, 3
40
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Rev. A
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®
IS42VS16400C1
ISSI
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
DOUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
t
OH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
UNDEFINED
t
RP
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Rev. A
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®
IS42VS16400C1
ISSI
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
t
OH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
UNDEFINED
t
RP
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Rev. A
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®
IS42VS16400C1
ISSI
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
t
AC
D
OUT m
t
LZ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
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Rev. A
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®
IS42VS16400C1
ISSI
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
OH
t
AC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
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Rev. A
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®
IS42VS16400C1
ISSI
ALTERNATINGBANKREADACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
tLZ
tOH
tOH
tOH
tOH
tOH
DQ
DOUT
m
D
OUT m+
1
DOUT m+
2
DOUT m+
3
DOUT b
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
t
t
t
t
RCD - BANK 0
RRD
CAS Latency - BANK 0
t
RP - BANK 0
tRCD - BANK 0
t
RCD - BANK 3
CAS Latency - BANK 3
RAS - BANK 0
RC - BANK 0
DON'T CARE
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Rev. A
45
10/06/05
®
IS42VS16400C1
ISSI
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
AC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+1
DQ
t
LZ
t
OH
t
OH
t
OH
t
OH
t
OH
tOH
t
RCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
46
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Rev. A
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®
IS42VS16400C1
ISSI
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
t
AC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
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Rev. A
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®
IS42VS16400C1
ISSI
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(3)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ALL BANKS
ROW
AS
t
AH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
DIN m+
2
DIN m+3
t
t
t
RCD
RAS
RC
t
WR(2)
t
RP
DON'T CARE
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Rev. A
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IS42VS16400C1
ISSI
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
DIN m+
1
DIN m+
2
DIN m+3
t
t
t
RCD
RAS
RC
t
WR
tRP
DON'T CARE
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Rev. A
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®
IS42VS16400C1
ISSI
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
NOP(4)
NOP(4)
PRECHARGE
NOP
ACTIVE
NOP
COMMAND
ACTIVE
NOP
WRITE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(3)
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ALL BANKS
ROW
ROW
SINGLE BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
WR(3)
tRP
DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
SINGLE WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
NOP(3)
NOP(3)
NOP(3)
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
WR
tRP
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
51
10/06/05
®
IS42VS16400C1
ISSI
ALTERNATING BANK WRITE ACCESS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
DIN m+
2
DIN m+
3
DIN
b
D
IN b+
1
DIN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
WR - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tWR - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
DIN m+
1
DIN m+
2
DIN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
53
10/06/05
®
IS42VS16400C1
ISSI
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
t
AH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
DIN
m
D
IN m+
2
DIN m+3
DQ
t
RCD
DON'T CARE
54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
®
IS42VS16400C1
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency
Speed(ns)
Order Part No.
Package
100 MHz
100 MHz
10
10
IS42VS16400C1-10T
IS42VS16400C1-10TL
400-mil TSOP II
400-mil TSOP II, Lead-free
83 MHz
83 MHz
12
12
IS42VS16400C1-12T
IS42VS16400C1-12TL
400-mil TSOP II
400-mil TSOP II, Lead-free
Industrial Range: -40°C to 85°C
Frequency
Speed(ns)
Order Part No.
Package
100 MHz
10
IS42VS16400C1-10TLI
400-mil TSOP II, Lead-free
83 MHz
83 MHz
12
12
IS42VS16400C1-12TI
IS42VS16400C1-12TLI
400-mil TSOP II
400-mil TSOP II, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
55
10/06/05
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Plastic TSOP (T - Type II)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Symbol Min
Max
Min
Max
Ref. Std.
Ref. Std.
No. Leads (N)
54
No. Leads (N)
86
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
A
A1
A2
b
C
D
E1
E
e
—
1.20
0.05 0.15
0.95 1.05
0.17 0.27
0.12 0.21
22.02 22.42
10.16 BSC
11.56 11.96
0.50 BSC
—
0.047
0.05 0.15
—
0.002 0.006
—
0.002 0.006
0.037 0.041
0.007 0.011
0.005 0.008
0.867 0.8827
0.400 BSC
—
—
0.30 0.45
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.80 BSC
0.012 0.018
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.031 BSC
0.455 0.471
0.020 BSC
L
0.40 0.60
0.016 0.024
L
0.40 0.60
0.80 REF
0.61 REF
0.016 0.024
0.031 REF
0.024 BSC
L1
ZD
α
—
—
—
—
L1
ZD
α
0.71 REF
0° 8°
0°
8°
0°
8°
0°
8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
1
01/28/02
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