IS43R83200F-6TLI-TR [ISSI]
IC DRAM 256M PARALLEL 66TSOP II;型号: | IS43R83200F-6TLI-TR |
厂家: | INTEGRATED SILICON SOLUTION, INC |
描述: | IC DRAM 256M PARALLEL 66TSOP II 动态存储器 |
文件: | 总32页 (文件大小:756K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IS43/46R83200F
IS43/46R16160F
IS43/46R32800F
8Mx32, 16Mx16, 32Mx8
256Mb DDR SDRAM
FEATURES
• VDD and VDDQ: 2.5V 0.2V
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
®
Long-term Support
World Class Quality
AUGUST 2020
DEVICE OVERVIEW
ISSI’s 256-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 268,435,456-bit memory
array is internally organized as four banks of 64Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit, 16-bit and 32-bit data word size
Input data is registered on the I/O pins on both edges
of Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
ADDRESS TABLE
• Four internal banks for concurrent operation
Parameter
8M x 32
16M x 16
32M x 8
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
Configuration 2M x 32 x 4
banks
4M x 16 x 4
banks
8M x 8 x 4
banks
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Concurrent Auto Precharge supported
• TRAS Lockout supported (tRAP = tRCD)
Bank Address BA0, BA1
Pins
BA0, BA1
BA0, BA1
Autoprecharge A8/AP
Pins
A10/AP
A10/AP
Row Address 4K(A0 – A11) 8K(A0 – A12) 8K(A0 – A12)
Column
Address
512(A0 – A7, 512(A0 – A8) 1K(A0 – A9)
A9)
OPTIONS
Refresh Count
Com./Ind./A1 4K / 64ms
A2 4K / 16ms
• Configuration(s): 8Mx32, 16Mx16, 32Mx8
8K / 64ms
8K / 16ms
8K / 64ms
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
• Lead-free package
• Temperature Range:
KEY TIMING PARAMETERS
Speed Grade
-5
-6
Units
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
FCk Max CL = 3
FCk Max CL = 2.5
FCk Max CL = 2
200
167
133
167
167
133
MHz
MHz
MHz
Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. C1
08/26/2020
®
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
FUNCTIONAL BLOCK DIAGRAM (x32)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
DM0-DM3
4
DATA IN
BUFFER
&
CLOCK
GENERATOR
32
32
I/O 0-31
REFRESH
CONTROLLER
DQS0-DQS3
4
Mode Registers and
Ext. Mode Registers
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
CONTROLLER
14
32
32
A11
A10
A9
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
4096
4096
12
MEMORY CELL
ARRAY
4096
4096
12
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
12
12
12
SENSE AMP I/O GATE
2
512
(x 32)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc.
Rev. C1
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
FUNCTIONAL BLOCK DIAGRAM (x16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
LDM, UDM
2
DATA IN
BUFFER
&
CLOCK
GENERATOR
16
16
I/O 0-15
REFRESH
CONTROLLER
LDQS, UDQS
2
Mode Registers and
Ext. Mode Registers
VDD/VDDQ
SELF
DATA OUT
BUFFER
REFRESH
Vss/VssQ
A12
A11
A10
A9
CONTROLLER
15
16
16
A8
A7
A6
REFRESH
COUNTER
2
A5
A4
A3
A2
8192
8192
13
MEMORY CELL
ARRAY
8192
8192
13
A1
BANK 0
ROW
A0
ROW
ADDRESS
LATCH
BA0
BA1
ADDRESS
BUFFER
13
13
13
SENSE AMP I/O GATE
2
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
Integrated Silicon Solution, Inc.
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Rev. C1
08/26/2020
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATIONS
66 pin TSOP - Type II for x8
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ7
V
DD
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VDDQ
NC
DQ2
7
NC
DQ5
8
V
DD
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC
DQ4
V
SS
Q
VDDQ
NC
NC
DDQ
NC
NC
NC
NC
V
V
SSQ
DQS
NC
VDD
NC
VREF
VSS
DM
CK
NC
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTION: x8
A0-A12
Row Address Input
Column Address Input
Bank Select Address
Data I/O
DM
Data Write Mask
Data Strobe
A0-A9
DQS
VDD
VDDQ
VSS
BA0, BA1
DQ0 – DQ7
CK, CK
CKE
Power
Power Supply for I/O Pins
Ground
System Clock Input
Clock Enable
VSSQ
VREF
NC
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
WE
Row Address Strobe
Command
Write Enable
4
Integrated Silicon Solution, Inc.
Rev. C1
08/26/2020
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Long-term Support
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x8
(8mm x 13mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the Package)
: Ball Existing
1
2
3
7
8
9
: Depopulated Ball
Top View
(See the balls through the Package)
VSSQ DQ7
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 4 5 6 7 8 9
NC
NC
VDDQ DQ6
VSSQ DQ5
DQ1 VSSQ
DQ2 VDDQ
NC
NC
NC
NC
A
B
C
D
E
F
NC
VDDQ DQ4
DQ3 VSSQ
DQS
NC
VSSQ
NC
NC
VDDQ
VDD
CAS
CS
E
F
VREF
DM
NC
VSS
CK
CKE
A9
WE
RAS
BA1
CK
A12
A11
A8
G
H
J
G
H
J
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x8 Device Ball Pattern
PIN DESCRIPTION: x8
A0-A12
A0-A9
Row Address Input
DQS
Data Strobe
Power
Column Address Input
Bank Select Address
Data I/O
VDD
VDDQ
VSS
BA0, BA1
DQ0 – DQ7
CK, CK
CKE
Power Supply for I/O Pins
Ground
System Clock Input
Clock Enable
VSSQ
VREF
NC
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
WE
DM
Row Address Strobe Command
Write Enable
Data Write Mask
Integrated Silicon Solution, Inc.
5
Rev. C1
08/26/2020
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ0
2
DQ15
V
DD
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DD
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ10
DQ9
V
SS
Q
VDDQ
DQ7
NC
DQ8
NC
V
DDQ
LDQS
NC
VSSQ
UDQS
NC
VDD
NC
VREF
VSS
UDM
CK
LDM
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
PIN DESCRIPTION: x16
A0-A12
Row Address Input
Column Address Input
Bank Select Address
Data I/O
LDM, UDM
Data Write Mask
Data Strobe
A0-A8
LDQS, UDQS
VDD
BA0, BA1
DQ0 – DQ15
CK, CK
CKE
Power
VDDQ
VSS
Power Supply for I/O Pins
Ground
System Clock Input
Clock Enable
VSSQ
VREF
NC
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
WE
Row Address Strobe
Command
Write Enable
6
Integrated Silicon Solution, Inc.
Rev. C1
08/26/2020
®
Long-term Support
World Class Quality
IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x16
(8mm x 13mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the Package)
: Ball Existing
1
2
3
7
8
9
: Depopulated Ball
Top View
(See the balls through the Package)
VSSQ DQ15
VSS
VDD
DQ0 VDDQ
A
B
C
D
1
2 3 6 7 8 9
4 5
DQ14 VDDQ DQ13
DQ12 VSSQ DQ11
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
A
B
C
D
E
F
DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
DQ8 VSSQ UDQS
VREF
E
F
NC
VSS
UDM
CK
LDM
WE
VDD
CAS
CS
CK
A12
A11
A8
G
H
J
G
H
J
RAS
BA1
CKE
A9
BA0
K
L
A7
A0 A10/AP
K
A6
A4
A5
A2
A1
A3
L
M
VSS
VDD
M
BGA Package Ball Pattern
Top View
x16 Device Ball Pattern
PIN DESCRIPTION: x16
A0-A12
A0-A8
Row Address Input
LDQS, UDQS
Data Strobe
Power
Column Address Input
Bank Select Address
Data I/O
VDD
VDDQ
VSS
BA0, BA1
DQ0 – DQ15
CK, CK
CKE
Power Supply for I/O Pins
Ground
System Clock Input
Clock Enable
VSSQ
VREF
NC
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
CS
Chip Select
CAS
Column Address Strobe
Command
RAS
Row Address Strobe Command
Write Enable
WE
LDM, UDM
Data Write Mask
Integrated Silicon Solution, Inc.
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Rev. C1
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATION
Package Code B: 144-ball FBGA (top view)
(12mm x 12mm Body, 0.8mm Ball Pitch)
Top View (Balls seen through the package)
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
DQ28 VSSQ DM3 DQS3
VDDQ NC VDDQ DQ27
VSSQ VSSQ DQ26 DQ25
VSS VDD VDDQ DQ24
VSSQ VDDQ DQ15 DQ14
VSSQ VDDQ DQ13 DQ12
DQ2 DQ0 DQ31 DQ29
DQ1 VDDQ VDDQ DQ30
VSSQ VDD VDD VSSQ
VSSQ VSS VSS VSSQ
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS
DQS0 DM0 VSSQ DQ3
DQ4 VDDQ NC VDDQ
DQ6 DQ5 VSSQ VSSQ
DQ7 VDDQ VDD VSS
DQ17 DQ16 VDDQ VSSQ
DQ19 DQ18 VDDQ VSSQ
G
H
J
VSSQ NC
DM1 DQS1
DQS2 DM2
NC VSSQ
VSSQ VDDQ DQ11 DQ10
VSSQ VDDQ DQ9 DQ8
DQ21 DQ20 VDDQ VSSQ
DQ22 DQ23 VDDQ VSSQ
K
L
NC
NC
A10 VDD VDD
NC
A5
A6
VSS VDD
NC
CAS
RAS
CS
WE VDD VSS
CK
A8
CK
NC
BA1
A0
A2
A1
A11
A3
A9
A4
NC
A7
NC
NC
M
CKE VREF
BA0
Note: Vss balls inside the dotted box are optional for purposes of thermal dissipation.
PIN DESCRIPTION: for x32
A0-A11
A0-A7, A9
BA0, BA1
DQ0 – DQ31
CK, CK
CKE
Row Address Input
Column Address Input
Bank Select Address
Data I/O
WE
Write Enable
DM0-DM3
DQS0-DQS3
VDD
Data Write Mask
Data Strobe
Power
System Clock Input
Clock Enable
VDDQ
VREF
VSS
Power Supply for I/O Pins
SSTL_2 reference voltage
Ground
CS
Chip Select
CAS
Column Address Strobe
Command
VSSQ
NC
Ground for I/O Pins
No Connection
RAS
Row Address Strobe
Command
8
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Rev. C1
08/26/2020
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN FUNCTIONAL DESCRIPTIONS
Symbol
Type Description
CK, CK
Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Input and output data is
referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are
derived from CK/ CK.
CKE
Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any
bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved
asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during power-down and
self refresh mode which are contrived for low standby power consumption.
CS
Input Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
RAS, CAS,
WE
DM: x8;
LDM, UDM:
x16;
Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.
DM0-DM3:
x32
For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on
DQ8-DQ15.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on
DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on
DQ24-DQ31.
BA0, BA1
A [12:0]
Input Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Input Address Inputs: provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of the memory
array in the respective bank. The address inputs also provide the opcode during a MODE
REGISTER SET command. A12 is not used for x32.
DQ:
DQ0-DQ7: x8;
DQ0-DQ15:
x16
I/O
Data Bus: Input / Output
DQ0-DQ31:
x32
DQS: x8:
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data.
LDQS, UDQS
x16:
DQS0-DQS3:
x32
For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the data on
DQ8-DQ15.
For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on
DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data
on DQ24-DQ31.
NC
--
No Connect: Should be left unconnected.
VREF
VDDQ
VSSQ
VDD
Supply SSTL_2 reference voltage.
Supply I/O Power Supply.
Supply I/O Ground.
Supply Power Supply.
Supply Ground.
VSS
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IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
COMMANDS TRUTH TABLES
All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high
and CK going low). Truth Table shows basic timing parameters for all commands.
TRUTH TABLE - COMMANDS
NAME (FUNCTION)
CS
H
L
RAS CAS WE
BA
X
AP
X
Address Notes
DESELECT (NOP)
X
H
L
X
H
H
L
X
H
H
H
X
X
2
2
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
X
X
L
Valid
Valid
X
Row
Column
READ (select bank and column and start read
burst)
L
H
L
READ with AP (read burst with Auto Precharge)
L
L
H
H
L
L
H
L
Valid
Valid
H
L
Column
Column
3
3
WRITE (select bank and column and start write
burst)
WRITE with AP (write burst with Auto
Precharge)
L
H
L
L
Valid
H
Column
BURST TERMINATE
L
L
H
L
H
H
L
L
X
X
L
X
X
4
5
PRECHARGE (deactivate row in selected
bank)
Valid
PRECHARGE ALL (deactivate rows in all
banks)
L
L
H
L
X
H
X
X
X
5
AUTO REFRESH or enter SELF REFRESH
MODE REGISTER SET
L
L
L
L
L
L
H
L
X
6,7,8
9
Valid
Op-code
Notes:
1. All states and sequences not shown are illegal or reserved.
2. DESELECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. AP High enables Auto Precharge, while AP Low disables Autoprecharge. Concurrent Auto-
precharge is supported.
4. Burst Terminate applies to only Read bursts with Auto Precharge disabled. This command is undefined and should not be
used for Read with Auto Precharge enabled, and for Write bursts.
5. If AP is Low, bank address determines which bank is to be precharged. If AP is High, all banks are precharged and BA0-
BA1are don’t care.
6. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
7. All address inputs and I/O are ‘don't care’ except for CKE. Internal refresh counters control bank and row addressing.
8. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
9. BA0 and BA1 value select between MRS and EMRS.
10. CKE is HIGH for all commands shown except SELF REFRESH.
ADDRESSING
TRUTH TABLE - DM Operations
x32
x16
x8
FUNCTION
Write Enable
Write Inhibit
DM
L
DQ
Valid
X
Auto Precharge (AP)
Row Address (RA)
A8
A10
A10
A0-A11 A0-A12 A0-A12
H
Column Address (CA) A0-A7,
A9
A0-A8
A0-A9
Note: Used to mask write data, provided coincident with the
corresponding data.
10
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IS43/46R16160F, IS43/46R32800F
TRUTH TABLE - CKE
CKE n-1 CKE n Current State
COMMAND n
ACTION n
NOTES
L
L
L
L
Power Down
Self Refresh
Power Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
X
Maintain Power Down
Maintain Self Refresh
Exit Power Down
X
L
H
H
L
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
AUTO REFRESH
6
L
Exit Self Refresh
6, 7
H
H
H
H
Precharge Power Down Entry
Active Power Down Entry
Self Refresh entry
6
6
L
L
H
See Truth Tables - Commands
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of DDR immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not go LOW during a Read or Write, and must stay HIGH until after tRPSt or twR, respectively.
6. DESELECT and NOP are functionally interchangeable.
7. NOPs or Deselects must be issued for at least tSnR after Self-Refresh exit before any other command. After DLL Reset, at
least txSRD must elapse before any Read commands occur.
Basic Timing Parameters for Commands
tCK
tCH
tCL
CK
CK
tIS tIH
Valid
Input
Valid
Valid
= Don't Care
NOTE: Input = A0 - An, BA0, BA1, CKE, CS, RAS, CAS, WE;
An = Address bus MSB
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SIMPLIFIED STATE DIAGRAM
Power
Applied
Power
On
Precharge
PREALL
Self
Refresh
REFS
REFSX
MRS
EMRS
MRS
REFA
Auto
Refresh
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Read
Write
Write
Read
Write A
Read A
Read
Read
Write
Read A
Write A
Read
A
PRE
Write
Read
A
A
PRE
PRE
Precharge
PREALL
PRE
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
CKEL = Enter Power Down
MRS = Mode Register Set
CKEH = Exit Power Down
REFS = Enter Self Refresh
Write A = Write with Autoprecharge
REFSX = Exit Self Refresh
Read A = Read with Autoprecharge
REFA = Auto Refresh
EMRS = Extended Mode Register Set
ACT = Active
PRE = Precharge
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FUNCTIONAL DESCRIPTION
The DDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank
DRAM. The 256Mb devices contains: 268,435,456 bits.
The DDR SDRAM uses double data rate architecture to achieve high speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit wide,
one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The
address bits registered coincident with the READ or WRITE command are used to select the bank and the starting
column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following section provides detailed information
covering device initialization, register definition, command description and device operation
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than those
specified may result in undefined operation. If there is any interruption to the device power, the initialization routine
should be followed. The steps to be followed for device initialization are listed below. The Initialization Flow diagram
and the Initialization Flow sequence are shown in the following figures.
The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the
initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has
been properly initialized from Step 1 through 13.
• Step 1: Apply VDD before or at the same time as VDDQ.
• Step 2: CKE must maintain LVCMOS Low until VREF is stable. Apply VDDQ before applying VTT and VREF.
• Step 3: There must be at least 200 μs of valid clocks before any command may be given to the DRAM. During this
time NOP or DESELECT commands must be issued on the command bus and CKE should be brought HIGH.
• Step 4: Issue a PRECHARGE ALL command.
• Step 5: Provide NOPs or DESELECT commands for at least tRP time.
• Step 6: Issue EMRS command
• Step 7: Issue MRS command, load the base mode register and to reset the DLL. Set the desired operating modes.
• Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
• Step 9: Issue a PRECHARGE ALL command
• Step 10: Issue 2 or more AUTO REFRESH cycles
• Step 11: Issue MRS command with the reset DLL bit deactivated to program operating parameters without resetting
the DLL
• Step 12: Provide NOP or DESELECT commands for at least tMRD time.
• Step 13: The DRAM has been properly initialized and is ready for any valid command.
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Initialization Waveform Sequence
VDD
tVDT≥ 0
VDDQ
VTT
(system1)
VREF
t
CK
t
tCL
CH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CK
CK
( (
) )
( (
) )
( (
( (
) )
( (
) )
( (
) )
) )
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
LVCMOS LOW LEVEL
CKE
((
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
NOP
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
COMMAND
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DM
( (
) )
( (
) )
( (
) )
( (
) )
( (
( (
) )
)
)
tIS tIH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
CODE
CODE
CODE
CODE
RA
( (
) )
( (
( (
) )
Address
AP4
( (
) )
( (
) )
( (
) )
)
)
t
IS
tIH
ALL BANKS
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
RA
BA
( (
) )
( (
( (
) )
( (
) )
( (
) )
( (
) )
) )
tIS tIH
tIS tIH
t
tIH
IS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
BA0=H,
BA1=L
BA0=L,
BA1=L
BA0=L,
BA1=L
BA0, BA1
( (
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
)
)
High-- Z
((
((
((
((
((
((
DQS
)
)
)
)
)
)
)
)
)
)
)
)
High-- Z
((
)
((
((
((
((
((
DQ
)
)
)
)
)
)
)
)
)
)
)
T = 200 µs
tMRD2
tMRD2
tRP
tRFC
tRFC
tMRD2
Power--up:
VDD and
CLK stable
Extended
Mode
Register
Set
200 cycles of CK**
Load
Mode
Register
(with AP= L)
Load
Mode
Register,
Reset DLL
(with AP = H)
DON’T CARE
Notes:
1. VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch--up.
2. tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command
can be applied
3. The two Auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL com-
mand.
4. AP is A8 for x32, and A10 for x8/x16. Address is A0 to A12 except AP.
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MODE REGISTER (MR) DEFINITION
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the definition of a burst length, a burst type, and a CAS latency. The Mode Register is programmed via the MODE
REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed,
or the device loses power. Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or
interleave), A4-A6 the CAS latency, and A8 DLL reset. A logic 0 should be programmed to all the undefined addresses
bits to ensure future compatibility. The Mode Register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating
either of these requirements will result in unspecified operation. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result
MODE REGISTER
BA1 BA0 A121 A11
Address Bus (Ax)
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Reg. (Ex)
A2 A1 A0 Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
A3 Burst Type
0
1
Sequential
Interleave
A6 A5 A4 CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
A12 A11 A10 A9 A8 A7 DLL
3
0
0
0
0
0
0
0
0
0
1
0
0
Normal operation
Reset DLL
Reserved
Reserved
2.5
Reserved
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
Notes:
1. A12 is not used in x32 and should be ignored for this option.
2. A logic 0 should be programmed to all unused / undefined
address bits to ensure future compatibility.
Reserved
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BURST LENGTH
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being set and the burst order
as in Burst Definition. The burst length determines the maximum number of column locations that can be accessed for
a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
BURST DEFINITION
Burst
Starting Column Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A 0
0
2
4
0-1
1-0
0-1
1-0
1
A 1
0
A 0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0
1
1
0
1
1
A 2
0
A 1
0
A 0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Notes:
1. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block.
2. For a burst length of four, A2-An selects the four data element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block.
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When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
The block is uniquely selected by A1-An when the burst length is set to two, by A2-An when the burst length is set
to 4, by A3-An when the burst length is set to 8. An is the most significant column address bit, which depends if the
device is x8, x16 or x32. An = A9 for x8, An = A8 for x16 and An = A9 for x32. The programmed burst length applies to
both read and write bursts.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address.
READ LATENCY
The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of
the first piece of output data.
If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at
n + 2tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data element
will be valid at n + tCK + tAC.
OPERATING MODE
The normal operating mode is selected by issuing a Mode Register Set command with bits A7 to An each set to zero,
and bits A0 to A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9 to An each set to zero, bit A8 set to one, and bits A0 to A6 set to the desired values. A Mode Register
Set command issued to reset the DLL must always be followed by a Mode Register Set command to select normal
operating mode (A8=0).
All other combinations of values for A7 to An are reserved for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
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CAS LATENCIES
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EXTENDED MODE REGISTER (EMR) DEFINITION
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, and output drive strength selection. The Extended Mode Register is
programmed via the MODE REGISTER SET command (with BA1=0 and BA0=1) and will retain the stored information
until it is reprogrammed, or the device loses power. The Extended Mode Register must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any
subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self
Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled a DLL Reset must follow and 200 clock
cycles must occur before any executable command can be issued.
OUTPUT DRIVE STRENGTH (DS)
The normal drive strength for all outputs is specified to be SSTL_2, Class II. This DRAM also supports a reduced
driver strength option, intended for lighter load and/or point-to-point environments.
EXTENDED MODE REGISTER
BA1 BA0 A122 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Ext. Mode Reg. (Ex)
Reserved(1)
Reserved(1)
A0 DLL
0
1
Enable
Disable
A6 A1 Drive Strength
0
0
1
1
0
1
0
1
Full (100%)
Weak (60%)
Reserved
Matched (30%)
BA1 BA0 Mode Register Definition
NOTES:
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
1. A logic 0 should be programmed to all unused/undefined ad-
dress bits to ensure future compatibility
2. A12 is not used for x32 and should be ignored for this option.
Reserved
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Absolute Maximum Rating
Parameter
Symbol
Vin, Vout
VDD, VDDq
TStg
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.5
Unit
V
Voltage on any pin relative to VSS
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
V
oC
Power dissipation
PD
W
Short circuit current
IoS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
AC/DC Electrical Characteristics and Operating Conditions
Recommended operating conditions (Voltage referenced to VSS=0V; TA=0 to 70oC for Commercial, TA = -40oC to +85oC for Industrial and A1,
TA = -40oC to +105oC for A2)
Parameter
Symbol
Min
Max
Unit
V
Note
Supply voltage (with a nominal VDD of 2.5V)
I/O Supply voltage (with a nominal VDD of 2.5V)
I/O Reference voltage
V
DD
DDq
Ref
tt
DC
2.3
2.7
V
2.3
2.7
V
V
0.49*VDDQ
0.51*VDDQ
V
1
2
I/O Termination voltage (system)
V
VREF-0.04
VREF+0.04
V
Input logic high voltage
V
ih
(
)
VREF+0.15
VDDQ+0.3
V
Input logic low voltage
V
il
(
DC
)
-0.3
-0.3
0.36
0.71
-2
VREF-0.15
V
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
V
V
in
(
DC
)
)
VDDQ+0.3
V
iD
(
DC
VDDQ+0.6
V
3
4
V
i
(Ratio)
1.4
2
–
I
l
uA
uA
mA
mA
mA
mA
Output leakage current
I
oz
oh
ol
ohR
olR
-5
5
Output High Current (Normal strength driver) ; VOUT = VTT + 0.84V
Output Low Current (Normal strength driver) ; VOUT = VTT - 0.84V
Output High Current (Half strength driver); VOUT = VTT + 0.45V
Output Low Current (Half strength driver); VOUT = VTT - 0.45V
Ambient Operating Temperature
I
-16.8
16.8
-9
–
I
–
I
–
I
9
–
Commercial
T
TA
TA
TA
A
0
+70
+85
+85
oC
oC
oC
oC
Industrial
A1
-40
-40
-40
A2
+105
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to
peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tem-
perature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maxi-
mum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to
minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
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CAPACITANCE CHARACTERISTICS(1, 2)
(VDD = VDDq = 2.5V + 0.2V, unless otherwise noted)
Symbol Parameter
Test Condition
Limits
Units
Min Max
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
VI=1.25v
1.3
1.3
2
3
3
4
5
pF
pF
pF
pF
f=100MHz
VI=25mVrms
I/O Capacitance, I/O, DQS, DM pin
3
Notes:
1. This parameter is characterized.
2. Conditions: Frequency = 100MHz; Vout(DC) = VDD/2; Vout(peak-to-peak) = 0.2V; VRef = Vss.
THERMAL RESISTANCE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)
TSOP2(66)
BGA(60)
4-layer
4-layer
4-layer
73.3
43.5
TBD
66.3
39.9
TBD
62.4
37.7
TBD
12.2
12.2
TBD
C/W
C/W
C/W
BGA(144)
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IDD Specification Parameters and Test Conditions: x8, x16
(VDD = VDDq = 2.5V 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol Parameter/ Test Condition
-5
-6
Units
IDD0
Operating current for one bank active-precharge; tRC = tRC(min);
tCK = tCK(min); DQ, DM and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles; CS = high between valid commands.
90
75
mA
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operating current for one bank operation; one bank open, BL = 4,
tRC = tRC(min), tCK = tCK(min), Iout=0mA, Address and control
inputs changing once per clock cycle.
110
30
80
30
80
95
30
70
30
70
mA
mA
mA
mA
mA
Precharge power-down standby current; all banks idle; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
Precharge floating standby current; CS VIH(min); all banks idle; CKE
VIH(min); tCK = tCK(min); address and other control inputs changing
once per clock cycle; VIN = VREF for DQ, DQS and DM
Active power-down standby current; one bank active; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
Active standby current; CS VIH(min); CKE VIH(min); one bank
active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs
changing twice per clock cycle; address and other control inputs
changing once per clock cycle
IDD4R
Operating current for burst read; burst length = 2; reads; continuous
burst; one bank active; address and control inputs changing once per
clock cycle; tCK = tCK(min); 50% of data changing on every transfer;
lOUT = 0mA
190 160
200 170
110 110
mA
mA
IDD4W Operating current for burst write; burst length = 2; writes; continuous
burst; one bank active address and control inputs changing once per
clock cycle; tCK = tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every transfer
IDD5
IDD6
IDD7
Auto refresh current; tRC = tRFC(min);
Self refresh current; CKE 0.2V;
mA
mA
mA
6
6
Operating current for four bank operation; four bank interleaving
READs (BL=4) with auto precharge; tRC = tRC(min), tCK = tCK(min);
Address and control inputs change only during ACTIVE, READ, or
WRITE commands
220 190
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IDD Specification Parameters and Test Conditions: x32
(VDD = VDDq = 2.5V 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol Parameter/ Test Condition
-5
-6 Units
IDD0
Operating current for one bank active-precharge; tRC = tRC(min);
tCK = tCK(min); DQ, DM and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles; CS = high between valid commands.
130 105
mA
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
Operating current for one bank operation; one bank open, BL = 4,
tRC = tRC(min), tCK = tCK(min), Iout=0mA, Address and control
inputs changing once per clock cycle.
160 140
mA
mA
mA
mA
mA
Precharge power-down standby current; all banks idle; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
35
90
35
90
35
80
35
80
Precharge floating standby current; CS VIH(min); all banks idle; CKE
VIH(min); tCK = tCK(min); address and other control inputs changing
once per clock cycle; VIN = VREF for DQ, DQS and DM
Active power-down standby current; one bank active; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
Active standby current; CS VIH(min); CKE VIH(min); one bank
active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs
changing twice per clock cycle; address and other control inputs
changing once per clock cycle
IDD4R
Operating current for burst read; burst length = 2; reads; continuous
burst; one bank active; address and control inputs changing once per
clock cycle; tCK = tCK(min); 50% of data changing on every transfer;
lOUT = 0mA
260 210
280 240
180 180
mA
mA
IDD4W Operating current for burst write; burst length = 2; writes; continuous
burst; one bank active address and control inputs changing once per
clock cycle; tCK = tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every transfer
IDD5
IDD6
IDD7
Auto refresh current; tRC = tRFC(min);
Self refresh current; CKE 0.2V;
mA
mA
mA
6
6
Operating current for four bank operation; four bank interleaving
READs (BL=4) with auto precharge; tRC = tRC(min), tCK = tCK(min);
Address and control inputs change only during ACTIVE, READ, or
WRITE commands
340 300
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AC TIMING REQUIREMENTS
Absolute Specifications (VDD, VDDQ = +2.5 V 0.2 V)
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
-0.7
-0.6
0.45
0.45
min
MAX
0.7
MIN
MAX
0.7
DQ output access time for CLK,/CLK
DQS output access time for CLK,/CLK
CLK high-level width
tAC
-0.7
-0.6
0.45
0.45
min
ns
ns
tDQSCK
tCH
0.6
0.6
0.55
0.55
–
0.55
0.55
–
tCK
tCK
ns
CLK low-level width
tCL
CLK half period
tHP
(tCL,tCH)
(tCL,tCH)
CLK cycle time CL=3
CL=2.5
tCK(3)
tCK(2.5)
tCK(2)
tDH
5
10
10
10
–
6
10
10
10
–
ns
ns
ns
ns
ns
ns
6
6
CL=2
7.5
0.4
0.4
2.2
7.5
0.45
0.45
2.2
DQ and DM input hold time
DQ and DM input setup time
tDS
–
–
Control & Address input pulse width (for each
input)
tIPW
–
–
DQ and DM input pulse width (for each input)
DQ & DQS high-impedance time from CLK,/CLK
DQ & DQS low--impedance time from CLK,/CLK
tDIPW
tHZ
1.75
–
–
1.75
–
–
0.7
–
ns
ns
ns
ns
0.7
–
tLZ
-0.7
–
-0.7
–
DQS--DQ Skew, DQS to last DQ valid, per group, tDQSQ
per access
0.4
0.45
DQ/DQS output hold time from DQS
tQH
tHP-tQHS
–
tHP-
–
ns
tQHS
Data Hold Skew Factor
tQHS
–
0.5
1.28
–
–
0.55
1.28
–
ns
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
tDQSS
tDQSH
tDQSL
tDSS
0.72
0.35
0.35
0.2
0.2
2
0.75
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
–
–
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
MODE REGISTER SET command cycle time
Write preamble setup time
–
–
tDSH
–
–
tMRD
–
–
tWPRES
tWPST
tWPRE
tIHF
0
–
0
–
Write postamble
0.4
0.25
0.6
0.6
–
0.4
0.25
0.75
0.6
–
tCK
tCK
ns
Write preamble
Address and Control input hold time (fast slew
rate)
–
–
Address and Control input setup time (fast slew
rate)
tISF
tIH
0.6
0.7
0.7
–
–
–
0.75
0.8
–
-–
–
ns
ns
ns
Address and Control input hold time (slow slew
rate)
Address and Control input setup time (slow slew
rate)
tIS
0.8
Read preamble
tRPRE
tRPST
tRAS
0.9
0.4
40
1.1
0.6
0.9
0.4
42
1.1
0.6
tCK
tCK
ns
Read postamble
ACTIVE to PRECHARGE command
70,000
120,000
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AC TIMING REQUIREMENTS
Absolute Specifications (VDD, VDDQ = +2.5 V 0.2 V)
PARAMETER
SYMBOL
-5
-6
UNITS
MIN
MAX
MIN
MAX
ACTIVE to ACTIVE/Auto Refresh command
period
tRC
55
–
60
–
ns
Auto Refresh to Active/Auto
tRFC
tRCD
tRP
70
15
15
15
10
15
–
–
72
15
15
15
12
15
–
–
ns
ns
ACTIVE to READ or WRITE delay
PRECHARGE command period
–
–
ns
Active to Autoprecharge Delay
tRAP
tRRD
tWR
–
–
ns
ACTIVE bank A to ACTIVE bank B command
Write recovery time
–
–
ns
–
–
ns
Auto Precharge write recovery + precharge time
Internal Write to Read Command Delay
Exit self refresh to non-READ
tDAL
tWR+tRP
–
tWR+tRP
–
tCK
tCK
ns
tWTR
tXSNR
tXSRD
tREFI
tREFI
2
70
200
–
–
1
75
200
–
–
–
–
Exit self refresh to READ command
Average Periodic Refresh Interval TA ≤ 85 ºC
–
–
tCK
µs
7.8
1.9
7.8
1.9
(x8/x16)
TA > 85 ºC,
A2 only
–
–
µs
Average Periodic Refresh Interval TA ≤ 85 ºC
tREFI
tREFI
–
–
15.6
3.9
–
–
15.6
3.9
µs
µs
(x32)
TA > 85 ºC,
A2 only
Output Load Condition
VREF
DQS
V
TT=VREF
DQ
50
VREF
Ω
V
OUT
Zo=50
Ω
V
REF
30pF
OutputTiming
Measurement
ReferencePoint
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AC Input Operating Conditions
(VDD = VDDQ = 2.5 0.2V, VSS= VSSQ= 0V, output open, unless otherwise noted.)
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF(AC)
Min
Max
1.5
1.5
Units
V
V
V
V
Input high (logic 1) voltage, DQ, DQS, and DM signals
Input low (logic 0) voltage, DQ, DQS, and DM signals
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
I/O reference voltage
VREF+0.310
-
0.7
VDDQ+0.6
0.5*VDDQ-0.2 0.5+VDDQ+0.2
0.51*VDDQ 4.5
V-ns
Notes:
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels un-
der normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a
result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of the
same.
9. IDD specifications are tested after the device is properly initialized.
10. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input
reference level for signals other than CLK//CLK, is VREF.
11. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE< 0.3VddQ
is recognized as LOW.
12. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not refer-
enced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
13. The maximum limit for tWPRES is not a device limit. The device will operate with a greater value for this parameter, but sys-
tem performance (bus turnaround) will degrade accordingly.
14. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK
edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in prog-
ress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
15. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
16. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
17. For command/address and CK & /CK slew rate > 1.0V/ns.
18. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be
derated: tiS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500 mV/ns. tih has nothing added. If
the slew rate exceeds 4.5 V/ns, functionality is uncertain. For operation at 166mHz or faster, slew rates must be greater than
or equal to 0.5 V/ns.
19. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
20. VIH overshoot: VIH, max = VDDO+1.5V for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle
rate. VII undershoot: VIL, min= -1.5V for a pulse width ≤ 3ns, and the pulse wifth can not be greater than 1/3 of the cycle rate.
21. Min (tCL,tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
22. For A2 temperature grade with TA > 85°C: IDD2F, IDD3N, and IDD7 are derated to 10% above these values; IDD2P and
IDD6 are derated to 20% above these values.
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OUTPUT SLEW RATE CHARACTERISTICS
Slew Rate Characteristic
Typical Range
(V/ns)
Min
(V/ns) (V/ns)
Max
Pullup Slew Rate
1.2-2.5
1.2-2.5
0.7
0.7
5.0
5.0
Pulldown Slew Rate
AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS AND CONTROL PINS
Parameter
Peak amplitude allowed for overshoot
Peak amplitude allowed for undershoot
Area between the overshoot signal and VDD must be less than or equal to (see figure below)
Area between the undershoot signal and GND must be less than or equal to (see figure below)
Max
Units
V
V
V-ns
V-ns
1.5
1.5
4.5
4.5
+5
+4
Max. amplitude = 1.5 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 4.5 V-ns
0
1
2
3
4
5
6
Time (ns)
Address and Control AC Overshoot and Undershoot Definition
OVERSHOOT/UNDERSHOOT SPECIFICATION FOR DATA, STROBE, AND MASK PINS
Parameter
Peak amplitude allowed for overshoot
Peak amplitude allowed for undershoot
Area between the overshoot signal and VDD must be less than or equal to (see figure below)
Area between the undershoot signal and GND must be less than or equal to (see figure below)
Max
1.2
1.2
2.4
2.4
Units
V
V
V-ns
V-ns
+5
+4
Max. amplitude = 1.2 V
Overshoot
+3
V
DD
+2
+1
0
Volts
(V)
Ground
-1
-2
-3
Undershoot
Max. area = 2.4 V--ns
0
1
2
3
4
5
6
Time (ns)
DQ/DM/DQS AC Overshoot and Undershoot Definition
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32Mx8 ORDERING INFORMATION - VDD = 2.5V
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
166 MHz
5
6
IS43R83200F-5TL
IS43R83200F-6TL
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
166 MHz
5
6
IS43R83200F-5TLI
IS43R83200F-6TLI
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
Automotive (A2) Range: -40°C to +105°C
Frequency Speed (ns)
166 MHz
Order Part No.
Package
6
IS46R83200F-6BLA2
60-ball BGA, Lead-free
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16Mx16 ORDERING INFORMATION - VDD = 2.5V
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
5
IS43R16160F-5BL
IS43R16160F-5TL
60-ball BGA, Lead-free
66-pin TSOP-II, Lead-free
166 MHz
6
IS43R16160F-6BL
IS43R16160F-6TL
60-ball BGA, Lead-free
66-pin TSOP-II, Lead-free
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
5
IS43R16160F-5BLI
IS43R16160F-5BI
IS43R16160F-5TLI
60-ball BGA, Lead-free
60-ball BGA
66-pin TSOP-II, Lead-free
166 MHz
6
IS43R16160F-6BLI
IS43R16160F-6BI
IS43R16160F-6TLI
60-ball BGA, Lead-free
60-ball BGA
66-pin TSOP-II, Lead-free
Automotive (A1) Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
5
IS46R16160F-5BLA1
IS46R16160F-5TLA1
60-ball BGA, Lead-free
66-pin TSOP-II, Lead-free
166 MHz
6
IS46R16160F-6BLA1
IS46R16160F-6TLA1
60-ball BGA, Lead-free
66-pin TSOP-II, Lead-free
Automotive (A2) Range: -40°C to +105°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
166 MHz
5
6
IS46R16160F-5BLA2
60-ball BGA, Lead-free
IS46R16160F-6BLA2
IS46R16160F-6TLA2
60-ball BGA, Lead-free
66-pin TSOP-II, Lead-free
8Mx32 ORDERING INFORMATION - VDD = 2.5V
Commercial Range: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
166 MHz
5
6
IS43R32800F-5BL
IS43R32800F-6BL
144-ball BGA, Lead-free
144-ball BGA, Lead-free
Industrial Range: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Package
200 MHz
166 MHz
5
6
IS43R32800F-5BLI
IS43R32800F-5BI
IS43R32800F-6BLI
144-ball BGA, Lead-free
144-ball BGA
144-ball BGA, Lead-free
Automotive (A1) Range: -40°C to +85°C
Frequency Speed (ns)
166 MHz
Order Part No.
Package
6
IS46R32800F-6BLA1
144-ball BGA, Lead-free
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Mini Ball Grid Array
Package Code: B (60-Ball) 8mm x 13mm
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