IS45RM16800H-6BLA1 [ISSI]
2M x 16Bits x 4Banks Mobile Synchronous DRAM;
| 型号： | IS45RM16800H-6BLA1 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 2M x 16Bits x 4Banks Mobile Synchronous DRAM 动态存储器 |
| 文件： | 总34页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42/45SM/RM/VM16800H
2M x 16Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM16800H are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 2,097,152 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
. JEDEC standard 3.3V, 2.5V, 1.8V power supply
• Auto refresh and self refresh
• Internal 4 banks operation
• Burst Read Single Write operation
• Special Function Support
• All pins are compatible with LVCMOS interface
• 4K refresh cycle / 64ms
• PASR(Partial Array Self Refresh)
• Programmable Burst Length and Burst Type
• 1, 2, 4, 8 or Full Page for Sequential Burst
• 4 or 8 for Interleave Burst
• Auto TCSR(Temperature Compensated Self Refresh)
• Programmable Driver Strength Control
• Full Strength or 1/2, 1/4, of Full Strength
• Deep Power Down Mode
• Programmable CAS Latency : 2,3 clocks
• All inputs and outputs referenced to the positive edge of the
system clock
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge
• Data mask function by DQM
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Figure1: 54Ball FBGA Ball Assignment
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
DQ15 VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BA0
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BA1
A1
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10
DQ8
UDQM
NC
DQ9
NC
VDDQ
VSS
CKE
A9
CLK
A11
A7
G
H
J
A8
A6
A0
A10
VDD
VSS
A5
A4
A3
A2
[Top View]
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table2: Pin Descriptions
Pin
Pin Name
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CLK
System Clock
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
CKE
Clock Enable
Chip Select
/CS
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
BA0~BA1
Bank Address
Address
Row Address
: RA0~RA11
: CA0~CA8
: A10
A0~A11
Column Address
Auto Precharge
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
/RAS, /CAS, /WE
LDQM,UDQM
Controls output buffers in read mode and masks input data in
write mode.
Data Input/Output Mask
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output
Data input/output pin.
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
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IS42/45SM/RM/VM16800H
Figure2: Functional Block Diagram
EXTENDED
MODE
REGISTER
CLK
CKE
CLOCK
GENERATOR
TCSR
PASR
BANK D
BANK C
ADDRESS
BANK B
ROW
BANK A
ADDRESS
BUFFER &
REFRESH
COUNTER
MODE
REGISTER
SENSE AMPLIFIER
COLUMN DECODER
/CS
/RAS
/CAS
/WE
&
LATCH CIRCUIT
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
LATCH CIRCUIT
DQM
INPUT & OUTPUT
BUFFER
DQ
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Figure3: Simplified State Diagram
EXTENDED
MODE
SELF
REGISTER
SET
REFRESH
MRS
MODE
REGISTER
SET
CBR
REF
IDLE
REFRESH
DEEP
POWER
DOWN
POWER
DOWN
CKE
ACTIVE
POWER
DOWN
ROW
CKE
ACTIVE
READ
WRITE
CKE
CKE
READ
WRITE
WRITE
SUSPEND
CKE
READ
READ
SUSPEND
CKE
WRITE
CKE
CKE
WRITE A
WRITE A
SUSPEND
READ A
READ A
SUSPEND
CKE
CKE
PRECHARGE
POWER
ON
PRE-
CHARGE
Automatic Sequence
Manual Input
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Figure4: Mode Register Definition
BA1
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
Address Bus
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0
0
WB
CAS Latency
BT
Burst Length
0
0
0
0
M9
0
Write Burst Mode
M6 M5 M4 CAS Latency
M3 Burst Type
Burst Length
M3 = 0 M3 = 1
M2 M1 M0
Burst Read and Burst Write
Burst Read and Single Write
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
1
Sequential
Interleave
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
3
4
4
Reserved
Reserved
Reserved
Reserved
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Note: M13(BA1) and M12 (BA0) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Table 3: Burst Definition
Starting Column Order of Access Within a Burst
Burst
Length
Address
Note :
Sequential
Interleaved
A2
A1 A0
1. For full-page accesses: y = 512
0
1
0-1
1-0
0-1
1-0
2. For a burst length of two, A1-A8 select the block-
of-two burst; A0 selects the starting column within the
block.
2
0
0
1
1
0
0
1
0
1
0
0-1-2-3
1-2-3-0
0-1-2-3
1-0-3-2
3. For a burst length of four, A2-A8 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4
2-3-0-1
3-0-1-2
2-3-0-1
3-2-1-0
4. For
a burst length of eight, A3-A8 select the
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn, Cn+1. Cn+2,
block-of-eight burst; A0-A2 select the starting column
within the block.
0
1
1
0
0
1
1
1
0
1
0
1
0
1
5. For a full-page burst, the full row is selected and A0-A8
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
8
7. For a burst length of one, A0-A8 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Full
n=A0-8
Cn+3, Cn+4…
…Cn-1, Cn...
Not Supported
Page
(Location 0-511)
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Figure5: Extended Mode Register
BA1
A11
A10
A9
A8
A7
A6
DS
A5
A4
A3
A2
A1
A0
BA0
Address Bus
11
10
9
8
7
6
5
4
3
2
1
0
13
12
Extended Mode Register (Ex)
0
0
0
0
0
0
0
PASR
1
0
E2
0
E1
E0
0
Self Refresh Coverage
E6
0
E5
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
Reserved
0
0
1
1
0
0
1
1
All Banks
0
1
0
1
0
1
Two Banks (BA1=0)
0
0
0
One Bank (BA1=BA0=0)
1
0
1
Reserved
1
1
0
Reserved
1
1
Half of One Bank (BA1=BA0=0, Row Address MSB=0)
Quarter of One Bank (BA1=BA0=0, Row Address 2 MSB=0)
Reserved
1
0
1
1
Note: E13(BA1) must be set to “1” and E12(BA0) must be set to “0” to select Extended Mode Register (vs. the base Mode
Register)
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IS42/45SM/RM/VM16800H
Functional Description
In general, this 128Mb SDRAM (2M x 16Bits x 4banks) is a multi-bank DRAM that operates at 3.3V/2.5V/1.8V and includes a
synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is
organized as 4,096 rows by 512 columns by 16-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (BA0-BA1 select the bank, A0-A11 select the row). The address bits (BA0-BA1 select the bank, A0-A8 select the
column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the PRECHARGE command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying any operational command. And a extended mode register set command will be issued to program specific mode of self
refresh operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10-M11 should be set to zero. M12 and M13
should be set to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the mobile DRAM device. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command and retains the stored information until it is
programmed again or the device loses power.
The Extended Mode Register must be programmed with E7 through E11 set to “0”. Also, E12(BA0) must be set to “0”, and E13(BA1)
must be set to “1”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in
unspecified operation.
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IS42/45SM/RM/VM16800H
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when
the burst length is set to two; by A2-A8 when the burst length is set to four; and by A3-A8 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and
deasserting CAS, WE at the positive edge of the clock. The value on the BA0-BA1 selects the bank, and the value on the A0-A11 selects
the row.
This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be
initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at
the positive edge of the clock. BA0-BA1 input select the bank, A0-A8 address inputs select the starting column location. The value on input
A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the
end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the
CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS
at the positive edge of the clock. BA0-BA1 input select the bank, A0-A8 address inputs select the starting column location. The value on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at
the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
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IS42/45SM/RM/VM16800H
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m
clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m -
1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Figure6: CAS Latency
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
NOP
tOH
Dout
tLZ
DQ
tAC
CAS Latency=2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
tOH
tLZ
DQ
Dout
tAC
CAS Latency=3
DON’T CARE
UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
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IS42/45SM/RM/VM16800H
Table4: Command Truth Table
Function
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
ADDR
A10
Note
Device Deselect (NOP)
No Operation (NOP)
Mode Register Set
H
H
H
H
X
X
X
X
H
L
L
L
X
H
L
X
H
L
X
H
L
X
X
X
X
X
X
OP CODE
OP CODE
4
4
Extended Mode Register Set
L
L
L
Active (select bank and
activate row)
H
X
L
L
H
H
X
Bank/Row
Read
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
H
H
L
L/H
L/H
L/H
L/H
X
Bank/Col
L
H
L
5
5
5
5
Read with Autoprecharge
Write
Bank/Col
Bank/Col
Bank/Col
X
L
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
L
L
H
H
L
H
H
H
L
L
L
L
X
Bank
H
L
L
X
X
Auto Refresh
H
H
X
H
X
H
X
H
X
V
X
X
X
3
3
Self Refresh Entry
L
L
X
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
Self Refresh Exit
L
H
L
H
L
X
X
X
X
X
X
X
X
2
Precharge Power Down Entry
Precharge Down Exit
Clock Suspend Entry
H
L
H
Clock Suspend Exit
L
H
L
H
L
X
X
X
X
X
X
X
Deep Power Down Entry
Deep Power Down Exit
L
H
H
L
6
H
X
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A11 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended
mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
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IS42/45SM/RM/VM16800H
Table5: Function Truth Table
Command
BA
Current
State
Action
Note
/CS
/RAS
/CAS
/WE
A0-A11
Description
L
L
L
L
OP CODE
Mode Register Set
Set the Mode Register
14
5
Start Auto or Self
Refresh
L
L
L
L
L
L
L
H
L
X
X
X
Auto or Self Refresh
Precharge
H
H
BA
BA
No Operation
Activate the Specified
Bank and Row
H
Row Add.
Bank Activate
L
L
H
H
L
L
L
BA
BA
Col Add./ A10
Col Add./ A10
Write/WriteAP
Read/ReadAP
ILLEGAL
ILLEGAL
4
4
Idle
H
No Operation or Power
Down
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
3
3
3
No Operation or Power
Down
No Operation or Power
Down
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
13,14
X
X
X
13
7
H
H
BA
BA
H
Row Add.
Bank Activate
4
Start Write : Optional
AP(A10=H)
L
L
H
H
L
L
L
BA
BA
Col Add./A10
Col Add./A10
Write/Write AP
Read/Read AP
6
6
Row
Active
Start Read : Optional
AP(A10=H)
H
L
H
L
H
X
H
L
H
X
H
L
H
X
L
X
X
X
X
X
X
No Operation
No Operation
No Operation
No Operation
ILLEGAL
Device Deselect
Burst Stop
L
L
OP CODE
Mode Register Set
Auto or Self Refresh
13,14
13
L
L
L
H
X
X
X
ILLEGAL
Termination Burst :
Start the Precharge
L
L
L
L
L
H
H
L
L
H
L
BA
BA
BA
Precharge
Row Add.
Col Add./A10
Bank Activate
Write/WriteAP
ILLEGAL
4
Termination Burst :
Start Write(AP)
Read
H
8,9
Terimination Burst :
Start Read(AP)
L
H
L
H
BA
Col Add./A10
Read/Read AP
8
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
Continue the Burst
Continue the Burst
Burst Stop, Row Active
H
H
12
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table5: Function Truth Table
Command
BA
Current
State
Action
ILLEGAL
Note
/CS
/RAS
/CAS
/WE
A0-A11
Description
L
L
L
L
L
L
L
OP CODE
Mode Register Set
Auto or Self Refresh
13,14
13
H
X
X
X
ILLEGAL
Termination Burst :
Start the Precharge
L
L
L
L
L
H
H
L
L
H
L
BA
BA
BA
Precharge
10
4
Row Add.
Col Add./A10
Bank Activate
Write/WriteAP
ILLEGAL
Termination Burst :
Start Write(AP)
Write
H
8
Terimination Burst :
Start READ(AP)
L
H
L
H
BA
Col Add./A10
Read/ReadAP
8,9
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
X
H
L
H
X
H
L
H
X
L
X
X
X
X
No Operation
Device Deselect
Burst Stop
Continue the Burst
Continue the Burst
Burst Stop, Row Active
ILLEGAL
X
X
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
13,14
13
L
L
H
L
X
BA
BA
BA
BA
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
4,12
4,12
12
L
H
L
Row Add.
Bank Activate
Write/WriteAP
Read/ReadAP
No Operation
Device Deselect
Burst Stop
ILLEGAL
Read
with
Auto
H
H
H
X
H
L
Col Add./A10
ILLEGAL
L
H
H
X
L
Col Add./A10
ILLEGAL
12
Precharge
H
X
H
L
X
Continue the Burst
Continue the Burst
ILLEGAL
X
X
X
X
13
13,14
13
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
L
L
H
L
X
BA
BA
BA
BA
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
4,12
4,12
12
Write
with
Auto
L
H
L
Row Add.
Bank Activate
Write/WriteAP
Read/ReadAP
No Operation
Device Deselect
Burst Stop
ILLEGAL
H
H
H
X
H
Col Add./A10
ILLEGAL
L
H
H
X
L
Col Add./A10
ILLEGAL
12
Precharge
H
X
H
X
X
X
Continue the Burst
Continue the Burst
ILLEGAL
X
X
13
13
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table5: Function Truth Table
Command
BA
Current
State
Action
ILLEGAL
Note
/CS
/RAS
/CAS
/WE
A0-A11
Description
L
L
L
L
L
L
L
OP CODE
Mode Register Set
Auto or Self Refresh
13,14
13
H
X
X
X
ILLEGAL
No Operation : Bank(s)
Idle after tRP
L
L
H
L
BA
Precharge
L
L
L
L
H
L
H
L
BA
BA
BA
Row Add.
Bank Activate
Write/WriteAP
Read/ReadAP
ILLEGAL
ILLEGAL
ILLEGAL
4,12
4,12
4,12
H
H
Col Add./ A10
Col Add./ A10
Precharging
L
H
No Operation : Bank(s)
Idle after tRP
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
No Operation : Bank(s)
Idle after tRP
No Operation : Bank(s)
Idle after tRP
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
X
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
L
H
H
L
BA
BA
BA
BA
X
4,12
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
4,11,12
4,12
H
H
Write/Write AP
Read/Read AP
Row
Activating
L
H
4,12
No Operation : Row
Active after tRCD
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
No Operation : Row
Active after tRCD
No Operation : Row
Active after tRCD
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
X
X
H
H
BA
BA
4,13
4,12
H
Row Add.
Bank Activate
Start Write : Optional
AP(A10=H)
L
L
H
H
H
X
L
L
L
H
H
X
L
BA
BA
X
Col Add./A10
Write/WriteAP
Read/Read AP
No Operation
Device Deselect
Burst Stop
Write
Recovering
Start Write : Optional
AP(A10=H)
Col Add./A10
9
No Operation : Row
Active after tDPL
L
H
X
H
X
X
X
No Operation : Row
Active after tDPL
H
L
X
No Operation : Row
Active after tDPL
H
X
14
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table5: Function Truth Table
Command
BA
Current
State
Action
ILLEGAL
Note
/CS
/RAS
/CAS
/WE
A0-A11
Description
Mode Register Set
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
13,14
13
X
X
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
H
H
L
BA
BA
BA
BA
X
4,13
4,12
4,12
4,9,12
L
H
L
Row Add.
Col Add./ A10
Col Add./ A10
Bank Activate
Write
Recovering
with
Auto
Precharge
H
H
Write/WriteAP
Read/ReadAP
L
H
No Operation :
Precharge after tDPL
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
No Operation :
Precharge after tDPL
No Operation :
Precharge after tDPL
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
X
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
L
H
H
L
BA
BA
BA
BA
X
13
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
13
H
H
Write/Write AP
Read/Read AP
13
Refreshing
L
H
13
No Operation : Idle
after tRC
L
H
L
H
X
H
X
H
X
L
X
X
X
X
X
X
No Operation
Device Deselect
Burst Stop
No Operation : Idle
after tRC
No Operation : Idle
after tRC
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
X
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
L
H
H
L
BA
BA
BA
BA
X
13
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
13
Mode
Register
Accessing
H
H
Write/WriteAP
Read/Read AP
13
L
H
13
No Operation : Idle
after 2 Clock Cycle
L
H
H
H
X
X
No Operation
No Operation : Idle
after 2 Clock Cycle
H
L
X
X
X
L
X
X
X
X
Device Deselect
Burst Stop
H
H
ILLEGAL
13
15
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA.
16
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table6: CKE Truth Table
CKE
Command
Current
State
Action
Note
Prev
Cycle
Current
Cycle
/CS
X
/RAS
/CAS
/WE
BA
X
A0-A11
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
2
3
Exit Self Refresh with Device
Deselect
H
H
X
Exit Self Refresh with No
Operation
L
H
L
H
H
H
X
3
Self
Refresh
L
L
H
H
H
L
L
L
H
H
L
H
L
L
X
X
X
X
X
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
3
3
3
ILLEGAL
L
L
X
X
X
X
H
X
L
ILLEGAL
L
X
X
H
L
X
X
X
H
L
Maintain Self Refresh
INVALID
H
X
2
3
Power Down Mode Exit, All
Banks Idle
L
H
Power
Down
ILLEGAL
L
H
L
X
X
X
X
X
X
3
X
X
X
X
X
L
H
L
L
X
H
L
X
X
X
X
X
X
X
X
Maintain Power Down Mode
INVALID
2
6
Deep
Power
Down
Deep Power Down Mode Exit
L
Maintain Deep Power Down
Mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
L
L
L
H
L
L
L
L
X
X
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State
section of the Current State
Truth Table
4
4
4
L
X
X
X
Auto Refresh
L
L
OP CODE
Mode Register Set
5
4
4
4
5
All
Banks
Idle
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State
section of the Current State
Truth Table
L
L
L
L
X
Entry Self Refresh
Mode Register Set
Power Down
L
L
L
OP CODE
X
H
X
X
X
X
X
X
X
X
X
X
5
H
Refer to Operations of the
Current State Truth Table
Any
State
other
than
listed
above
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next
cycle
Exit Clock Suspend next
cycle
L
Maintain Clock Suspend
17
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes
high and is maintained for a minimum 100usec.
18
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table7A: 3.3V Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Ambient Temperature (Industrial)
Ambient Temperature (Automotive, A1)
Ambient Temperature (Automotive, A2)
Storage Temperature
-40 ~ 85
-40 ~ 85
-40 ~ 105
-55 ~ 150
-1.0 ~ 4.6
-1.0 ~ 4.6
50
TA
C
TSTG
VIN, VOUT
VDD, VDDQ
IOS
C
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
V
mA
W
PD
1
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8A: 3.3V Capacitance (TA=25 C, f=1MHz, VDD= 3.3V)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
Input Capacitance
A0~A11, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE, LDQM, UDQM
CI2
CIO
2
3
4
5
pF
pF
Data Input/Output Capacitance
DQ0~DQ15
Table9A: 3.3V DC Operating Condition (Voltage referenced to VSS=0V, TA= -40 ~ 105 C)
Parameter
Symbol
VDD
VDDQ
VIH
Min
2.7
2.7
2.2
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Power Supply Voltage
3.3
3.6
V
1
Input High Voltage
Input Low Voltage
-
0
-
VDDQ+0.3
V
2
VIL
0.5
-
V
3
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
VOH
V
IOH= -0.1mA
VOL
-
0.4
1
V
IOL= +0.1mA
ILI
-1
-
uA
uA
4
5
ILO
-1.5
1.5
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = 5.3V AC. The overshoot voltage duration is 3ns.
3. VIL(min) = -2.0V AC. The overshoot voltage duration is 3ns.
4. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. DOUT is disabled, 0V VOUT VDDQ.
19
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table10A: 3.3V AC Operating Condition (TA= -40 ~ 105 C, VDD = 2.7V-3.6V, VSS=0V)
Parameter
AC Input High/Low Level Voltage
Symbol
VIH / VIL
VTRIP
Typ
2.4 / 0.4
0.5 x VDDQ
1 / 1
Unit
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
V
tR / tF
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
VOUTREF
CL
0.5 x VDDQ
30
pF
VDDQ
VTT=0.5 x VDDQ
1200
50
Output
Output
Z0=50
30pF
30pF
870
DC Output Load Circuit
AC Output Load Circuit
20
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table11A: 3.3V DC Characteristic (DC operating conditions unless otherwise noted)
Speed
Parameter
Sym
Test Condition
Unit
mA
Note
-6
50
-75
Burst Length=1, One Bank Active,
tRC tRC(min) IOL = 0 mA
Operating Current
IDD1
45
1
IDD2P
CKE VIL(max), tCK = 10ns
0.3
0.3
Precharge Standby Current
in Power Down Mode
mA
IDD2PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2
clks.
IDD2N
10
4
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD2NS
IDD3P
CKE VIL(max), tCK = 10ns
1
1
Active Standby Current
in Power Down Mode
IDD3PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2
clks.
IDD3N
20
15
Active Standby Current
in Non Power Down Mode
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD3NS
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
Burst Mode Operating Current
Auto Refresh Current (4K Cycle)
IDD4
IDD5
60
55
mA
mA
1
2
tRC tRFC(min), All Banks Active
70
PASR
TCSR
85C
45C
85C
45C
85C
45C
300
230
250
200
220
180
20
4 banks
Self
Refresh
Current
IDD6
IDD7
CKE 0.2V
uA
uA
2 Bank
1 Bank
Deep Power Down Mode Current
3
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Typical value at room temperature.
4. Self Refresh mode and Deep Power Down are not supported for A2 grade with TA > 85°C
21
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table7B: 2.5V Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Ambient Temperature (Industrial)
Ambient Temperature (Automotive, A1)
Ambient Temperature (Automotive, A2)
Storage Temperature
-40 ~ 85
-40 ~ 85
-40 ~ 105
-55 ~ 150
-1.0 ~ 3.6
-1.0 ~ 3.6
50
TA
C
TSTG
VIN, VOUT
VDD, VDDQ
IOS
C
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
V
mA
W
PD
1
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8B: 2.5V Capacitance (TA=25 C, f=1MHz, VDD=2.5V)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
Input Capacitance
A0~A11, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE, LDQM, UDQM
CI2
CIO
2
3
4
5
pF
pF
Data Input/Output Capacitance
DQ0~DQ15
Table9B: 2.5V DC Operating Condition (Voltage referenced to VSS=0V, TA= -40 ~ 105 C)
Parameter
Symbol
VDD
VDDQ
VIH
Min
Typ
Max
Unit
V
Note
2.3
2.5
3.0
Power Supply Voltage
2.3
2.5
3.0
V
1
Input High Voltage
Input Low Voltage
0.8 x VDDQ
-
0
-
VDDQ+0.3
V
2
VIL
-0.3
0.3
-
V
3
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
VOH
0.9 x VDDQ
V
IOH= -0.1mA
VOL
-
-
0.2
1
V
IOL= +0.1mA
ILI
-1
-
uA
uA
4
5
ILO
-1.5
1.5
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = VDDQ+1.5V AC. The overshoot voltage duration is 3ns.
3. VIL(min) = -1.0V AC. The overshoot voltage duration is 3ns.
4. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. DOUT is disabled, 0V VOUT VDDQ.
22
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table10B: 2.5V AC Operating Condition (TA= -40 ~ 105 C, VDD = 2.3V – 3.0V, VSS=0V)
Parameter
AC Input High/Low Level Voltage
Symbol
VIH / VIL
VTRIP
Typ
0.9 x VDDQ / 0.2
0.5 x VDDQ
1 / 1
Unit
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
V
tR / tF
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
VOUTREF
CL
0.5 x VDDQ
30
pF
VDDQ
VTT=0.5 x VDDQ
500
50
Output
Output
Z0=50
30pF
30pF
500
DC Output Load Circuit
AC Output Load Circuit
23
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IS42/45SM/RM/VM16800H
Table11B: 2.5V DC Characteristic (DC operating conditions unless otherwise noted)
Speed
Parameter
Sym
Test Condition
Unit
mA
Note
-6
50
-75
Burst Length=1, One Bank Active,
tRC tRC(min) IOL = 0 mA
Operating Current
IDD1
45
1
IDD2P
CKE VIL(max), tCK = 10ns
0.3
0.3
Precharge Standby Current
in Power Down Mode
mA
IDD2PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2
clks.
IDD2N
10
4
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD2NS
IDD3P
CKE VIL(max), tCK = 10ns
1
1
Active Standby Current
in Power Down Mode
IDD3PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2
clks.
IDD3N
20
15
Active Standby Current
in Non Power Down Mode
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD3NS
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
Burst Mode Operating Current
Auto Refresh Current (4K Cycle)
IDD4
IDD5
60
55
mA
mA
1
2
tRC tRFC(min), All Banks Active
70
PASR
TCSR
85C
45C
85C
45C
85C
45C
300
230
250
200
220
180
20
4 banks
Self
Refresh
Current
IDD6
IDD7
CKE 0.2V
uA
uA
2 Bank
1 Bank
Deep Power Down Mode Current
3
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Typical value at room temperature.
4. Self Refresh mode and Deep Power Down are not supported for A2 grade with TA > 85°C
24
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IS42/45SM/RM/VM16800H
Table7C: 1.8V Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Ambient Temperature (Industrial)
Ambient Temperature (Automotive, A1)
Ambient Temperature (Automotive, A2)
Storage Temperature
-40 ~ 85
-40 ~ 85
-40 ~ 105
-55 ~ 150
-1.0 ~ 2.6
-1.0 ~ 2.6
50
TA
C
TSTG
VIN, VOUT
VDD, VDDQ
IOS
C
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
V
mA
W
PD
1
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8C: 1.8V Capacitance (TA=25 C, f=1MHz, VDD=1.8V)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
Input Capacitance
A0~A11, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE, LDQM, UDQM
CI2
CIO
2
3
4
5
pF
pF
Data Input/Output Capacitance
DQ0~DQ15
Table9C: 1.8V DC Operating Condition (Voltage referenced to VSS=0V, TA= -40 ~ 105 C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD
1.7
1.8
1.95
V
Power Supply Voltage
VDDQ
VIH
1.7
1.8
1.95
V
V
1
Input High Voltage
Input Low Voltage
0.8 x VDDQ
-
0
-
VDDQ+0.3
2
VIL
-0.3
0.3
-
V
3
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
VOH
VOL
ILI
0.9 x VDDQ
V
IOH= -0.1mA
-
-
0.2
1
V
IOL= +0.1mA
-1
-
uA
uA
4
5
ILO
-1.5
1.5
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = VDDQ+1.5V AC. The overshoot voltage duration is 3ns.
3. VIL(min) = -1.0V AC. The overshoot voltage duration is 3ns.
4. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. DOUT is disabled, 0V VOUT VDDQ.
25
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IS42/45SM/RM/VM16800H
Table10C: 1.8V AC Operating Condition (TA= -40 ~ 105 C, VDD = 1.7V-1.95V, VSS=0V)
Parameter
AC Input High/Low Level Voltage
Symbol
VIH / VIL
VTRIP
Typ
0.9 x VDDQ / 0.2
0.5 x VDDQ
1 / 1
Unit
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
V
tR / tF
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
VOUTREF
CL
0.5 x VDDQ
30
pF
VDDQ
VTT=0.5 x VDDQ
500
50
Output
Output
Z0=50
30pF
30pF
500
DC Output Load Circuit
AC Output Load Circuit
26
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Table11C: 1.8V DC Characteristic (DC operating conditions unless otherwise noted)
Speed
Parameter
Sym
Test Condition
Unit
mA
Note
-6
50
-75
Burst Length=1, One Bank Active,
tRC tRC(min) IOL = 0 mA
Operating Current
IDD1
45
1
IDD2P
CKE VIL(max), tCK = 10ns
0.3
0.3
Precharge Standby Current
in Power Down Mode
mA
IDD2PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
IDD2N
10
4
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD2NS
IDD3P
CKE VIL(max), tCK = 10ns
1
1
Active Standby Current
in Power Down Mode
IDD3PS
CKE & CLK VIL(max), tCK =
CKE VIH(min), /CS VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
IDD3N
20
10
Active Standby Current
in Non Power Down Mode
CKE VIH(min), CLK VIL(max), tCK =
Input signals are stable.
IDD3NS
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
Burst Mode Operating Current
Auto Refresh Current (4K Cycle)
IDD4
IDD5
60
55
mA
mA
1
2
tRC tRFC(min), All Banks Active
70
PASR
TCSR
85C
45C
85C
45C
85C
45C
300
230
250
200
220
180
10
4 banks
Self
Refresh
Current
IDD6
IDD7
CKE 0.2V
uA
uA
2 Bank
1 Bank
Deep Power Down Mode Current
3
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Typical value at room temperature
4. Self Refresh mode and Deep Power Down are not supported for A2 grade with TA > 85°C
27
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IS42/45SM/RM/VM16800H
Table12: AC Characteristic (AC operation conditions unless otherwise noted)
-6
-75
Parameter
Sym
Unit
Note
Min
6.0
10
Max
Min
7.5
10
Max
CL = 3
CL = 2
tCK3
tCK2
CLK Cycle Time
1000
1000
1
CL = 3
CL = 2
tAC3
5.5
8
6
8
Access time from CLK (pos. edge)
2
tAC2
tCH
CLK High-Level Width
CLK Low-Level Width
CKE Setup Time
2.5
2.5
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
2.5
2.5
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
3
3
tCL
tCKS
tCKH
tCMS
tCMH
tAS
CKE Hold Time
/CS, /RAS, /CAS, /WE, DQM Setup Time
/CS, /RAS, /CAS, /WE, DQM Hold Time
Address Setup Time
Address Hold Time
tAH
ns
Data-In Setup Time
tDS
Data-In Hold Time
tDH
CL = 3
CL = 2
tHZ3
tHZ2
tLZ
5.5
8
6
8
Data-Out High-Impedance Time
from CLK (pos.edge)
4
Data-Out Low-Impedance Time
Data-Out Hold Time (load)
1.0
2.5
1.8
42
1.0
2.5
1.8
45
tOH
Data-Out Hold Time (no load)
ACTIVE to PRECHARGE command
PRECHARGE command period
tOHN
tRAS
tRP
100K
100K
18
19
ACTIVE bank a to ACTIVE bank a command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
tRC
60
67.5
15
5
6
tRRD
tRCD
12
18
19
READ/WRITE command to READ/WRITE
command
tCCD
1
1
CLK
ns
WRITE command to input data delay
Data-in to PRECHARGE command
Data-in to ACTIVE command
tDWD
tDPL
0
12
30
2
0
15
37.5
2
6
7
7
6
6
tDAL
tDQZ
tDQM
DQM to data high-impedance during READs
DQM to data mask during WRITEs
0
0
LOAD MODE REGISTER command to ACTIVE
or REFRESH command
tMRD
2
2
8
6
CLK
CL = 3
CL = 2
tROH3
tROH2
tBDL
3
2
1
1
3
2
1
1
Data-out to high-impedance from
PRECHARGE command
Last data-in to burst STOP command
6
6
Last data-in to new READ/WRITE command
tCDL
CKE to clock disable or power-down entry
mode
tCKED
tPED
1
1
1
1
9
9
CLK
CKE to clock enable or power-down exit
setup mode
Refresh period (4,096 rows)
AUTO REFRESH period
tREF
tRFC
tXSR
tT
64
64
ms
ns
80
80
80
80
5
5
Exit SELF REFRESH to ACTIVE command
Transition time
0.5
1.2
0.5
1.2
28
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
11. The specification in the table for tREF is applicable for all temperature grades with TA ≤ +85°C. Only A2 automotive temperature
grade supports operation with TA > +85°C, and this value must be further constrained with a maximum tREF of 16ms.
29
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Special Operation for Low Power Consumption
Temperature Compensated Self Refresh
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Mobile SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are All Banks, Two Banks (bank a and b), One Bank (bank a), Half of One Bank
(1/2 of bank a), or Quarter of One Bank (1/4 of bank a). WRITE and READ commands can still occur during standard operation, but
only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
while CKE is low. This mode is exited by asserting CKE high.
30
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Figure7: Deep Power Down Mode Entry
CLK
CKE
/CS
/RAS
/CAS
/WE
tRP
DON’T CARE
Deep Power Down Entry
Precharge if needed
Figure8: Deep Power Down Mode Exit
CLK
CKE
/CS
/RAS
/CAS
/WE
100 µ s
tRP
Auto Refresh
tRFC
Deep Power Down Exit
All Banks Precharge
Mode Register Set
Extended Mode Register Set
New Command
Auto Refresh
DON’T CARE
31
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Ordering Information – VDD = 3.3V
Industrial Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
133
6
IS42SM16800H-6BLI
IS42SM16800H-75BLI
IS42SM16800H-75BI
54-ball BGA, Lead-free
54-ball BGA, Lead-free
54-ball BGA
7.5
7.5
Ordering Information – VDD = 2.5V
Industrial Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
133
6
IS42RM16800H-6BLI
IS42RM16800H-75BLI
IS42RM16800H-75BI
54-ball BGA, Lead-free
54-ball BGA, Lead-free
54-ball BGA
7.5
7.5
Ordering Information – VDD = 1.8V
Industrial Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
133
6
IS42VM16800H-6BLI
IS42VM16800H-75BLI
IS42VM16800H-75BI
54-ball BGA, Lead-free
54-ball BGA, Lead-free
54-ball BGA
7.5
7.5
32
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
Ordering Information – VDD = 3.3V
Automotive (A1) Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
6
IS45SM16800H-6BLA1
IS45SM16800H-75BLA1
54-ball BGA, Lead-free
54-ball BGA, Lead-free
7.5
Ordering Information – VDD = 2.5V
Automotive (A1) Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
6
IS45RM16800H-6BLA1
IS45RM16800H-75BLA1
54-ball BGA, Lead-free
54-ball BGA, Lead-free
7.5
Ordering Information – VDD = 1.8V
Automotive (A1) Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
8Mx16
166
133
6
IS45VM16800H-6BLA1
IS45VM16800H-75BLA1
54-ball BGA, Lead-free
54-ball BGA, Lead-free
7.5
33
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Rev. A | November 2015
IS42/45SM/RM/VM16800H
34
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Rev. A | November 2015
相关型号：
IS45RM32200M-6BLA1
Synchronous DRAM, 2MX32, 5.5ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-207, TFBGA-90
ISSI
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