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IS45S16800F-6BLA1 [ISSI]

IC DRAM 128M PARALLEL 54TFBGA;
IS45S16800F-6BLA1
型号： IS45S16800F-6BLA1
厂家： INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述：

IC DRAM 128M PARALLEL 54TFBGA

动态存储器
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IS42/45S81600F  
IS42/45S16800F  
16Mx8, 8Mx16  
SEPTEMBER 2019  
128Mb SYNCHRONOUS DRAM  
OVERVIEW  
FEATURES  
ISSI's 128Mb Synchronous DRAM achieves high-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
The 128Mb SDRAM is organized as follows.  
• Clock frequency: 200, 166, 143 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Power supply  
Vdd Vddq  
IS42/45S81600F IS42/45S16800F  
IS42/45S81600F  
IS42/45S16800F  
• LVTTL interface  
3.3V 3.3V  
4M x8 x4 Banks  
54-pin TSOPII  
2M x16 x4 Banks  
54-pin TSOPII  
54-ball BGA  
3.3V 3.3V  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
• Programmable burst sequence:  
Sequential/Interleave  
KEY TIMING PARAMETERS  
• Auto Refresh (CBR)  
• Self Refresh  
Parameter  
-5  
-6  
-7  
Unit  
Clk Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
• 4096 refresh cycles every 16 ms (A2 grade) or  
64 ms (Commercial, Industrial, A1 grade)  
5
10  
6
10  
7
7.5  
ns  
ns  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2  
• Random column address every clock cycle  
200  
100  
166  
100  
143  
133  
Mhz  
Mhz  
• Programmable CAS latency (2, 3 clocks)  
• Burst read/write and burst read/single write  
operations capability  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
5
6.5  
5.4  
6.5  
5.4  
5.4  
ns  
ns  
• Burst termination by burst stop and precharge  
command  
• Temperature Ranges:  
Commercial (0oC to +70oC)  
Industrial (-40oC to +85oC)  
Automotive, A1 (-40oC to +85oC)  
Automotive, A2 (-40oC to +105oC)  
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-  
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain  
the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be  
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated  
Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
1
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
DEVICE OVERVIEW  
Aself-timed row precharge initiated at the end of the burst  
sequence is available with theAUTO PRECHARGE func-  
tion enabled. Precharge one bank while accessing one of  
the other three banks will hide the precharge cycles and  
provide seamless, high-speed, random-access operation.  
The 128Mb SDRAM is a high speed CMOS, dynamic  
random-access memory designed to operate in 3.3V Vdd  
and 3.3V Vddq memory systems containing 134,217,728  
bits. Internally configureꢀ as a ꢁuaꢀ-bank DRAM with  
a synchronous interface. Each 33,554,432-bit bank is  
organized as 4,096 rows by 512 columns by 16 bits or  
4,096 rows by 1,024 columns by 8 bits.  
SDRAMreadandwriteaccessesareburstorientedstarting  
at a selected location and continuing for a programmed  
number of locations in a programmed sequence. The  
registration of an ACTIVE command begins accesses,  
followed by a READ or WRITE command. The ACTIVE  
command in conjunction with address bits registered are  
used to select the bank and row to be accessed (BA0,  
BA1 select the bank; A0-A11 select the row). The READ  
or WRITE commands in conjunction with address bits  
registered are used to select the starting column location  
for the burst access.  
The128MbSDRAMincludesanAUTOREFRESHMODE,  
and a power-saving, power-down mode. All signals are  
registered on the positive edge of the clock signal, CLK.  
All inputs and outputs are LVTTL compatible.  
The 128Mb SDRAM has the ability to synchronously burst  
data at a high data rate with automatic column-address  
generation,theabilitytointerleavebetweeninternalbanks  
to hide precharge time and the capability to randomly  
change column addresses on each clock cycle during  
burst access.  
Programmable READ or WRITE burst lengths consist of  
1, 2, 4 and 8 locations or full page, with a burst terminate  
option.  
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQML  
DQMH  
DATA IN  
BUFFER  
COMMAND  
DECODER  
&
CLOCK  
GENERATOR  
16  
16  
REFRESH  
CONTROLLER  
MODE  
REGISTER  
2
DQ 0-15  
12  
V
DD/VDDQ  
ss/Vss  
SELF  
DATA OUT  
BUFFER  
REFRESH  
V
Q
A10  
A11  
A9  
CONTROLLER  
16  
16  
A8  
A7  
A6  
REFRESH  
COUNTER  
A5  
A4  
4096  
A3  
A2  
A1  
A0  
BA0  
BA1  
4096  
MEMORY CELL  
ARRAY  
4096  
4096  
12  
BANK 0  
ROW  
ADDRESS  
LATCH  
ROW  
ADDRESS  
BUFFER  
12  
12  
SENSE AMP I/O GATE  
512  
(x 16)  
COLUMN  
ADDRESS LATCH  
BANK CONTROL LOGIC  
9
BURST COUNTER  
COLUMN DECODER  
COLUMN  
ADDRESS BUFFER  
9
2
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
PIN CONFIGURATIONS  
54 pin TSOP - Type II for x8  
V
DD  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
DQ0  
2
DQ7  
V
DD  
Q
3
VSSQ  
NC  
DQ1  
4
NC  
DQ6  
5
V
SS  
Q
6
VDDQ  
NC  
DQ2  
7
NC  
DQ5  
8
V
DD  
Q
9
VSSQ  
NC  
DQ3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
NC  
DQ4  
V
SS  
Q
VDDQ  
NC  
NC  
V
DD  
NC  
WE  
VSS  
NC  
DQM  
CLK  
CKE  
NC  
A11  
A9  
CAS  
RAS  
CS  
BA0  
BA1  
A10  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
V
DD  
V
SS  
PIN DESCRIPTIONS  
A0-A11  
A0-A9  
BA0, BA1  
DQ0 to DQ7  
CLK  
Row Address Input  
WE  
Write Enable  
Column Address Input  
Bank Select Address  
Data I/O  
DQM  
Vdd  
Vss  
Data Input/Output Mask  
Power  
Ground  
System Clock Input  
Clock Enable  
Vddq  
Vssq  
NC  
Power Supply for I/O Pin  
Ground for I/O Pin  
No Connection  
CKE  
CS  
Chip Select  
RAS  
Row Address Strobe Command  
Column Address Strobe Command  
CAS  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
3
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
PIN CONFIGURATIONS  
54 pin TSOP - Type II for x16  
V
DD  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
DQ0  
2
DQ15  
V
DD  
Q
3
VSSQ  
DQ1  
DQ2  
4
DQ14  
DQ13  
5
V
SS  
Q
6
VDDQ  
DQ3  
DQ4  
7
DQ12  
DQ11  
8
V
DD  
Q
9
VSSQ  
DQ5  
DQ6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
DQ10  
DQ9  
V
SS  
Q
VDDQ  
DQ7  
DQ8  
VDD  
VSS  
DQML  
WE  
CAS  
RAS  
CS  
NC  
DQMH  
CLK  
CKE  
NC  
BA0  
BA1  
A10  
A0  
A11  
A9  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
V
DD  
V
SS  
PIN DESCRIPTIONS  
A0-A11  
A0-A8  
BA0, BA1  
DQ0 to DQ15  
CLK  
Row Address Input  
WE  
Write Enable  
Column Address Input  
Bank Select Address  
Data I/O  
DQML x16 Lower Byte, Input/Output Mask  
DQMH x16 Upper Byte, Input/Output Mask  
Vdd  
Vss  
Power  
System Clock Input  
Clock Enable  
Ground  
CKE  
Vddq  
Vssq  
NC  
Power Supply for I/O Pin  
Ground for I/O Pin  
No Connection  
CS  
Chip Select  
RAS  
Row Address Strobe Command  
Column Address Strobe Command  
CAS  
4
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
PIN CONFIGURATION  
54-ball BGA for x16 (Top View) (8.00 mm x 8.00 mm Body, 0.8 mm Ball Pitch)  
PACKAGE CODE: 54B (8x8)  
1 2 3 4 5 6 7 8 9  
A
VSS DQ15 VSSQ  
DQ14 DQ13 VDDQ  
DQ12 DQ11 VSSQ  
DQ10 DQ9 VDDQ  
VDDQ DQ0 VDD  
VSSQ DQ2 DQ1  
VDDQ DQ4 DQ3  
VSSQ DQ6 DQ5  
VDD DQML DQ7  
CAS RAS WE  
BA0 BA1 CS  
B
C
D
E
F
DQ8 NC  
VSS  
DQMH CLK CKE  
G
H
J
NC  
A8  
A11  
A7  
A9  
A6  
A4  
A0  
A3  
A1  
A10  
VSS  
A5  
A2 VDD  
PIN DESCRIPTIONS  
A0-A11  
A0-A8  
BA0, BA1  
DQ0 to DQ15  
CLK  
Row Address Input  
WE  
Write Enable  
Column Address Input  
Bank Select Address  
Data I/O  
DQML x16 Lower Byte Input/Output Mask  
DQMH x16 Upper Byte Input/Output Mask  
Vdd  
Vss  
Power  
System Clock Input  
Clock Enable  
Ground  
CKE  
Vddq  
Vssq  
NC  
Power Supply for I/O Pin  
Ground for I/O Pin  
No Connection  
CS  
Chip Select  
RAS  
Row Address Strobe Command  
Column Address Strobe Command  
CAS  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
5
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
PIN FUNCTIONS  
Symbol  
Type  
Function (In Detail)  
A0-A11  
Input Pin  
Address Inputs: A0-A11 are sampled during the ACTIVE  
command (row-address A0-A11) and READ/WRITE command (column address A0-  
A9 (x8), or A0-A8 (x16); with A10 ꢀefining auto precharge) to select one location out  
of the memory array in the respective bank. A10 is sampled during a PRECHARGE  
command to determine if all banks are to be precharged (A10 HIGH) or bank se-  
lected by BA0, BA1 (LOW). The address inputs also provide the op-code during a  
LOAD MODE REGISTER command.  
BA0, BA1  
CAS  
Input Pin  
Input Pin  
Input Pin  
Bank Select Aꢀꢀress: BA0 anꢀ BA1 ꢀefines which bank the ACTIVE, READ, WRITE  
or PRECHARGE command is being applied.  
CAS, in conjunction with the RAS and WE, forms the device command. See the  
"Command Truth Table" for details on device commands.  
CKE  
The CKE input determines whether the CLK input is enabled. The next rising edge of  
the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE  
is LOW, the device will be in either power-down mode, clock suspend mode, or self  
refresh mode. CKE is an asynchronous input.  
CLK  
Input Pin  
Input Pin  
CLK is the master clock input for this device. Except for CKE, all inputs to this device  
are acquired in synchronization with the rising edge of this pin.  
CS  
The CS input determines whether command input is enabled within the device.  
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The  
device remains in the previous state when CS is HIGH.  
DQML,  
Input Pin  
DQML anꢀ DQMH control the lower anꢀ upper bytes of the I/O buffers. In reaꢀ  
DQMH  
moꢀe,DQML anꢀ DQMH control the output buffer. WhenDQML orDQMH is LOW, the  
corresponꢀing buffer byte is enableꢀ, anꢀ when HIGH, ꢀisableꢀ. The outputs go to  
the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds  
to OE in conventional DRAMs. In write mode,DQML and DQMH control the input  
buffer. When DQML or DQMH is LOW, the corresponꢀing buffer byte is enableꢀ,  
and data can be written to the device. When DQML or DQMH is HIGH, input data is  
masked and cannot be written to the device. For IS42/45S16800F only.  
DQM  
Input Pin  
For IS42/45S81600F only.  
DQ0-DQ7 or  
DQ0-DQ15  
Input/Output  
Data on the Data Bus is latcheꢀ on DQ pins ꢀuring Write commanꢀs, anꢀ buffereꢀ for  
output after Read commands.  
RAS  
Input Pin  
Input Pin  
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-  
mand Truth Table" item for details on device commands.  
WE  
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-  
mand Truth Table" item for details on device commands.  
Vddq  
Vdd  
Power Supply Pin  
Power Supply Pin  
Power Supply Pin  
Power Supply Pin  
Vddq is the output buffer power supply.  
Vdd is the device internal power supply.  
Vꢂꢂq is the output buffer grounꢀ.  
Vꢂꢂq  
Vꢂꢂ  
Vꢂꢂ is the device internal ground.  
6
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
GENERAL DESCRIPTION  
READ  
TheREADcommandselectsthebankfromBA0,BA1inputs  
and starts a burst read access to an active row. InputsA0-  
A9(x8);A0-A8(x16)providesthestartingcolumnlocation.  
When A10 is HIGH, this command functions as an AUTO  
PRECHARGE command. When the auto precharge is  
selected, the row being accessed will be precharged at  
the end of the READ burst. The row will remain open for  
subsequent accesses when AUTO PRECHARGE is not  
selected. DQ’s read data is subject to the logic level on  
the DQM inputs two clocks earlier. When a given DQM  
signal was registered HIGH, the corresponding DQ’s will  
be High-Z two clocks later. DQ’s will provide valid data  
when the DQM signal was registered LOW.  
PRECHARGEfunctioninconjunctionwithaspecificREAD  
orWRITEcommand. ForeachindividualREADorWRITE  
command, auto precharge is either enabled or disabled.  
AUTO PRECHARGE does not apply except in full-page  
burst mode. Upon completion of the READ or WRITE  
burst, a precharge of the bank/row that is addressed is  
automatically performed.  
AUTO REFRESH COMMAND  
This command executes theAUTO REFRESH operation.  
The row address and bank to be refreshed are automatically  
generated during this operation. The stipulated period (tꢃꢄ)  
is required for a single refresh operation, and no other  
commands can be executed during this period. This com-  
mandisexecutedatleast4096timesforeveryTꢃꢅꢆ.During  
an AUTO REFRESH command, address bits are “Don’t  
Care”. This command corresponds to CBR Auto-refresh.  
WRITE  
A burst write access to an active row is initiated with the  
WRITE command. BA0, BA1 inputs selects the bank, and  
the starting column location is provided by inputs A0-A9  
(x8);A0-A8 (x16). Whether or notAUTO-PRECHARGE is  
used is determined by A10.  
BURST TERMINATE  
The BURST TERMINATE command forcibly terminates  
the burst read and write operations by truncating either  
fixeꢀ-length or full-page bursts anꢀ the most recently  
registered READ or WRITE command prior to the BURST  
TERMINATE.  
The row being accessed will be precharged at the end of  
the WRITE burst, if AUTO PRECHARGE is selected. If  
AUTO PRECHARGE is not selected, the row will remain  
open for subsequent accesses.  
A memory array is written with corresponding input data  
on DQ’s and DQM input logic level appearing at the same  
time. Data will be written to memory when DQM signal is  
LOW. When DQM is HIGH, the corresponding data inputs  
will be ignored, and a WRITE will not be executed to that  
byte/column location.  
COMMAND INHIBIT  
COMMAND INHIBITprevents new commands from being  
executeꢀ. Operations in progress are not affecteꢀ, apart  
from whether the CLK signal is enabled  
NO OPERATION  
When CS is low, the NOP command prevents unwanted  
commandsfrombeingregisteredduringidleorwaitstates.  
PRECHARGE  
The PRECHARGE command is used to deactivate the  
open row in a particular bank or the open row in all banks.  
BA0, BA1 can be used to select which bank is precharged  
or they are treated as “Don’t Care”. A10 determined  
whether one or all banks are precharged. After execut-  
ing this command, the next command for the selected  
bank(s) is executed after passage of the period tRP, which  
is the period required for bank precharging. Once a bank  
has been precharged, it is in the idle state and must be  
activated prior to any READ or WRITE commands being  
issued to that bank.  
LOAD MODE REGISTER  
During the LOAD MODE REGISTER command the mode  
register is loaded from A0-A11. This command can only  
be issued when all banks are idle.  
ACTIVE COMMAND  
When the ACTIVE COMMAND is activated, BA0, BA1  
inputs selects a bank to be accessed, and the address  
inputs on A0-A11 selects the row. Until a PRECHARGE  
command is issued to the bank, the row remains open  
for accesses.  
AUTO PRECHARGE  
The AUTO PRECHARGE function ensures that the pre-  
charge is initiated at the earliest valid stage within a burst.  
This function allows for individual-bank precharge without  
requiring an explicit command. A10 to enable the AUTO  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
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09/11/2019  
IS42/45S81600F, IS42/45S16800F  
COMMAND TRUTH TABLE  
CKE  
A11  
Function  
n – 1  
H
n
×
×
×
×
×
×
×
×
×
×
H
L
×
CS  
H
L
RAS  
×
CAS  
×
WE  
×
BA1  
×
BA0  
×
A10 A9 - A0  
Device deselect (DESL)  
No operation (NOP)  
Burst stop (BST)  
Read  
×
×
×
L
×
×
×
V
V
V
V
V
×
×
×
×
V
H
H
H
H
H
H
H
L
H
H
L
H
L
×
×
H
L
×
×
H
L
H
H
L
V
V
V
V
V
V
×
V
V
V
V
V
V
×
Read with auto precharge  
Write  
H
L
L
H
L
H
L
L
Write with auto precharge  
Bank activate (ACT)  
H
L
L
L
H
V
L
H
L
H
H
H
L
H
L
Precharge select bank (PRE) H  
L
L
Precharge all banks (PALL)  
CBR Auto-Refresh (REF)  
Self-Refresh (SELF)  
H
H
H
H
L
L
L
H
×
×
L
L
L
H
H
L
×
×
L
L
L
×
×
Mode register set (MRS)  
L
L
L
L
L
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data.  
DQM TRUTH TABLE  
CKE  
DQM  
Function  
n-1  
H
n
×
×
×
×
×
×
U
L
L
L
Data write / output enable  
Data mask / output disable  
H
H
L
H
×
L
Upper byte write enable / output enable  
Lower byte write enable / output enable  
Upper byte write inhibit / output disable  
H
H
×
H
×
H
×
H
Lower byte write inhibit / output disable  
H
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data.  
8
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
CKE TRUTH TABLE  
CKE  
Current State /Function  
n – 1 n  
CS  
×
RAS  
CAS WE  
Address  
Activating Clock suspend mode entry  
Any Clock suspend mode  
Clock suspend mode exit  
Auto refresh command Idle (REF)  
Self refresh entry Idle (SELF)  
Power down entry Idle  
H
L
L
L
H
H
L
L
×
×
×
L
L
×
×
×
×
×
H
H
×
×
×
×
×
×
×
×
×
×
L
L
×
L
×
H
H
H
L
L
×
Self refresh exit  
L
L
H
H
L
H
H
×
H
×
H
×
×
×
Power down exit  
L
H
×
×
×
×
×
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data.  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
9
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
FUNCTIONAL TRUTH TABLE  
Current State  
CS  
H
L
RAS CAS WE  
Address  
Command  
DESL  
Action  
Idle  
X
H
H
H
H
L
X
H
H
L
X
H
L
X
Nop or Power Down(2)  
Nop or Power Down(2)  
Nop or Power Down  
ILLEGAL (3)  
X
NOP  
L
X
BST  
L
H
L
BA, CA, A10  
A, CA, A10  
BA, RA  
BA, A10  
X
READ/READA  
WRIT/ WRITA  
ACT  
L
L
ILLEGAL(3)  
L
H
H
L
H
L
Row activating  
Nop  
Auto refresh or Self-refresh(4)  
Mode register set  
Nop  
L
L
PRE/PALL  
REF/SELF  
MRS  
L
L
H
L
L
L
L
OC, BA1=L  
X
Row Active  
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
DESL  
X
NOP  
Nop  
L
X
BST  
Nop  
L
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
READ/READA  
WRIT/ WRITA  
ACT  
Begin read (5)  
Begin write (5)  
ILLEGAL (3)  
L
L
L
H
H
H
L
L
L
PRE/PALL  
Precharge  
Precharge all banks(6)  
L
L
H
L
L
X
L
L
X
H
L
X
REF/SELF  
MRS  
ILLEGAL  
ILLEGAL  
OC, BA  
X
Read  
X
DESL  
Continue burst to end to  
Row active  
L
H
H
H
X
NOP  
Continue burst to end Row  
Row active  
L
L
H
H
H
L
L
X
BST  
Burst stop, Row active  
H
BA, CA, A10  
READ/READA  
Terminate burst,  
begin new read (7)  
L
H
L
L
BA, CA, A10  
WRIT/WRITA  
Terminate burst,  
begin write (7,8)  
L
L
L
L
H
H
H
L
BA, RA  
ACT  
ILLEGAL (3)  
BA, A10  
PRE/PALL  
Terminate burst  
Precharging  
L
L
H
L
L
X
L
L
X
H
L
X
REF/SELF  
MRS  
ILLEGAL  
ILLEGAL  
OC, BA  
X
Write  
X
DESL  
Continue burst to end  
Write recovering  
L
H
H
H
X
NOP  
Continue burst to end  
Write recovering  
L
L
H
H
H
L
L
X
BST  
Burst stop, Row active  
H
BA, CA, A10  
READ/READA  
Terminate burst, start read :  
Determine AP (7,8)  
L
H
L
L
BA, CA, A10  
WRIT/WRITA  
Terminate burst, new write :  
Determine AP (7)  
L
L
L
L
L
L
L
L
H
H
L
H
L
BA, RA  
BA, A10  
X
RA ACT  
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL (3)  
Terminate burst Precharging (9)  
H
L
ILLEGAL  
L
OC, BA  
ILLEGAL  
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code  
10  
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Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
FUNCTIONAL TRUTH TABLE Continued:  
Current State  
CS  
RAS CAS  
WE  
Address  
Command  
Action  
Read with auto  
Precharging  
H
×
×
×
×
DESL  
Continue burst to end, Precharge  
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
H
L
H
L
x
NOP  
Continue burst to end, Precharge  
ILLEGAL  
ILLEGAL (11)  
ILLEGAL (11)  
ILLEGAL (3)  
×
BST  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
×
READ/READA  
WRIT/ WRITA  
ACT  
L
H
H
L
H
L
L
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL (11)  
L
H
L
ILLEGAL  
L
L
OC, BA  
×
ILLEGAL  
Write with Auto  
Precharge  
×
×
×
DESL  
Continue burst to end, Write  
recovering with auto precharge  
L
H
H
H
×
NOP  
Continue burst to end, Write  
recovering with auto precharge  
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
×
BST  
ILLEGAL  
ILLEGAL(11)  
ILLEGAL (11)  
ILLEGAL (3,11)  
H
L
BA, CA, A10  
READ/READA  
WRIT/ WRITA  
ACT  
L
BA, CA, A10  
H
H
L
H
L
BA, RA  
L
BA, A10  
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL (3,11)  
L
H
L
×
ILLEGAL  
L
L
OC, BA  
ILLEGAL  
Precharging  
×
H
H
H
H
L
×
H
H
L
×
H
L
×
DESL  
Nop, Enter idle after tRP  
Nop, Enter idle after tRP  
Nop, Enter idle after tRP  
ILLEGAL (3)  
ILLEGAL (3)  
ILLEGAL(3)  
×
NOP  
×
BST  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
×
READ/READA  
WRIT/WRITA  
ACT  
L
H
H
L
H
L
L
PRE/PALL  
REF/SELF  
MRS  
Nop Enter idle after tRP  
ILLEGAL  
L
H
L
L
L
OC, BA  
×
ILLEGAL  
Row Activating  
×
H
H
H
H
L
×
H
H
L
×
H
L
DESL  
Nop, Enter bank active after tRCD  
Nop, Enter bank active after tRCD  
Nop, Enter bank active after tRCD  
ILLEGAL (3)  
ILLEGAL (3)  
ILLEGAL (3,9)  
×
NOP  
×
BST  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
×
READ/READA  
WRIT/WRITA  
ACT  
L
H
H
L
H
L
L
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL (3)  
L
H
L
ILLEGAL  
L
L
OC, BA  
ILLEGAL  
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code  
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Rev. D1  
11  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
FUNCTIONAL TRUTH TABLE Continued:  
Current State  
CS  
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
RAS CAS  
WE  
Address  
Command  
DESL  
Action  
Write Recovering  
×
H
H
H
H
L
×
H
H
L
×
×
Nop, Enter row active after tDPL  
Nop, Enter row active after tDPL  
Nop, Enter row active after tDPL  
Begin read(8)  
H
L
×
NOP  
×
BST  
H
L
BA, CA, A10  
READ/READA  
WRIT/ WRITA  
ACT  
L
BA, CA, A10  
Begin new write  
ILLEGAL (3)  
ILLEGAL (3)  
H
H
L
H
L
BA, RA  
L
BA, A10  
PRE/PALL  
REF/SELF  
MRS  
L
H
L
×
ILLEGAL  
L
L
OC, BA  
ILLEGAL  
Write Recovering  
with Auto  
×
×
H
H
L
×
H
L
×
DESL  
Nop, Enter precharge after tDPL  
Nop, Enter precharge after tDPL  
Nop, Enter row active after tDPL  
ILLEGAL(3,8,11)  
ILLEGAL (3,11)  
ILLEGAL (3,11)  
H
H
H
H
L
×
NOP  
Precharge  
×
BST  
H
L
BA, CA, A10  
READ/READA  
WRIT/WRITA  
ACT  
L
BA, CA, A10  
H
H
L
H
L
BA, RA  
L
BA, A10  
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL (3,11)  
L
H
L
×
ILLEGAL  
L
L
OC, BA  
ILLEGAL  
Refresh  
×
×
H
L
×
×
H
L
×
DESL  
Nop, Enter idle after tRC  
Nop, Enter idle after tRC  
ILLEGAL  
H
H
H
L
×
NOP/BST  
READ/READA  
WRIT/WRITA  
ACT  
BA, CA, A10  
L
BA, CA, A10  
ILLEGAL  
H
H
L
H
L
BA, RA  
ILLEGAL  
L
BA, A10  
PRE/PALL  
REF/SELF  
MRS  
ILLEGAL  
L
H
L
×
ILLEGAL  
L
L
OC, BA  
ILLEGAL  
Mode Register  
Accessing  
×
×
H
H
L
×
H
L
×
DESL  
Nop, Enter idle after 2 clocks  
Nop, Enter idle after 2 clocks  
ILLEGAL  
H
H
H
L
×
NOP  
×
BST  
×
×
BA, CA, A10  
BA, RA  
READ/WRITE  
ILLEGAL  
×
ACT/PRE/PALL ILLEGAL  
REF/MRS  
Note: H=Vꢇꢈ, L=Vꢇꢉ x= Vꢇꢈ or Vꢇꢉ, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code  
Notes:  
1. All entries assume that CKE is active (CKEn-1=CKEn=H).  
2. If both banks are iꢀle, anꢀ CKE is inactive (Low), the ꢀevice will enter Power Down moꢀe. All input buffers except CKE will be  
disabled.  
3. Illegal to bank in specifieꢀ states; Function may be legal in the bank inꢀicateꢀ by Bank Aꢀꢀress (BA), ꢀepenꢀing on the state of  
that bank.  
4. If both banks are iꢀle, anꢀ CKE is inactive (Low), the ꢀevice will enter Self-Refresh moꢀe. All input buffers except CKE will be  
disabled.  
5. Illegal if tRCD is not satisfieꢀ.  
6. Illegal if tRAS is not satisfieꢀ.  
7. Must satisfy burst interrupt condition.  
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
9. Must mask preceding data which don’t satisfy tDPL.  
10. Illegal if tRRD is not satisfieꢀ.  
11. Illegal for single bank, but legal for other banks.  
12  
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Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
CKE RELATED COMMAND TRUTH TABLE(1)  
CKE  
n-1  
Current State  
Operation  
n
X
H
H
H
H
L
CS  
X
H
L
RAS  
X
X
H
H
L
CAS  
X
X
H
L
WE Address  
Self-Refresh (S.R.)  
INVALID, CLK (n - 1) would exit S.R.  
Self-Refresh Recovery(2)  
Self-Refresh Recovery(2)  
Illegal  
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
L
X
L
L
X
Illegal  
L
L
X
X
X
H
L
X
Maintain S.R.  
L
X
H
L
X
X
H
H
L
X
Self-Refresh Recovery Idle After tꢃꢄ  
H
H
H
H
H
H
H
H
L
H
H
H
H
L
X
Idle After tꢃꢄ  
Illegal  
X
L
X
Illegal  
L
X
X
H
L
X
Begin clock suspend next cycle(5)  
Begin clock suspend next cycle(5)  
H
L
X
H
H
L
X
L
X
Illegal  
L
L
X
Illegal  
L
L
X
X
X
X
X
X
X
X
H
L
X
Exit clock suspend next cycle(2)  
Maintain clock suspend  
INVALID, CLK (n - 1) would exit P.D.  
EXIT P.D. --> Idle(2)  
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
H
L
X
L
X
Power-Down (P.D.)  
Both Banks Idle  
H
L
X
H
L
—
X
Maintain power down mode  
L
X
Refer to operations in Operative Command TableH  
Refer to operations in Operative Command TableH  
Refer to operations in Operative Command TableH  
H
H
H
H
H
L
—
—
L
—
Auto-Refresh  
H
L
L
X
Refer to operations in Operative Command TableH  
Refer to operations in Operative Command TableH  
Refer to operations in Operative Command TableH  
Refer to operations in Operative Command TableH  
L
L
L
Op - Code  
H
L
X
H
L
X
X
H
L
X
X
X
H
L
—
L
—
L
L
—
Self-Refresh(3)  
Refer to operations in Operative Command TableH  
Power-Down(3)  
Refer to operations in Operative Command TableH  
H
L
L
L
X
L
L
L
L
Op - Code  
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any state  
other than  
listed above  
Begin clock suspend next cycle(4)  
Exit clock suspend next cycle  
Maintain clock suspend  
H
L
L
H
L
Notes:  
1. H : High level, L : low level, X : High or low level (Don’t care).  
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup  
time must be satisfieꢀ  
before any command other than EXIT.  
3. Power down and Self refresh can be entered only from the both banks idle state.  
4. Must be legal commanꢀ as ꢀefineꢀ in Operative Commanꢀ Table.  
5. Illegal if tꢂꢃꢊ is not satisfieꢀ.  
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Rev. D1  
13  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
STATE DIAGRAM  
Self  
Refresh  
SELF  
SELF exit  
REF  
Mode  
Register  
Set  
MRS  
CBR (Auto)  
Refresh  
IDLE  
CKE  
CKE  
ACT  
Power  
Down  
CKE  
Active  
Power  
Down  
Row  
Active  
CKE  
BST  
Write  
BST  
Read  
Auto Prech  
Write  
Read  
arge  
Read  
CKE  
CKE  
CKE  
WRITE  
SUSPEND  
READ  
SUSPEND  
READ  
WRITE  
Write  
CKE  
CKE  
CKE  
CKE  
READA  
SUSPEND  
WRITEA  
SUSPEND  
WRITEA  
READA  
CKE  
Precharge  
POWER  
ON  
Precharge  
Automatic sequence  
Manual Input  
14  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Vdd ꢋꢌꢊ  
Vddqꢋꢌꢊ  
Vꢇꢍ  
Parameters  
Rating  
–0.5 to +4.6  
–0.5 to +4.6  
–0.5 to Vdd + 0.5  
–1.0 to Vddq + 0.5  
1
Unit  
V
Maximum Supply Voltage  
Maximum Supply Voltage for Output Buffer  
Input Voltage  
V
V
Vꢎꢏꢐ  
Output Voltage  
V
Pd ꢋꢌꢊ  
Iꢄꢂ  
Allowable Power Dissipation  
Output Shorted Current  
W
mA  
°C  
50  
Tꢎꢑꢃ  
Operating Temperature  
Com.  
Ind.  
A1  
0 to +70  
-40 to +85  
-40 to +85  
-40 to +105  
A2  
Tꢂꢐꢒ  
Storage Temperature  
–55 to +150  
°C  
Notes:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other conditions  
above those inꢀicateꢀ in the operational sections of this specification is not implieꢀ. Exposure to absolute  
maximum rating conꢀitions for extenꢀeꢀ perioꢀs may affect reliability.  
2. All voltages are referenced to Vss.  
DC RECOMMENDED OPERATING CONDITIONS  
Tꢌ = 0oC to +70oC for Commercial grade. Tꢌ = -40oC to +85oC for Industrial and A1 grade. Tꢌ = -40oC to +105oC for A2 grade.  
Symbol  
Vdd  
Parameter  
Min.  
3.0  
Typ.  
3.3  
3.3  
—
Max.  
3.6  
Unit  
V
Supply Voltage  
I/O Supply Voltage  
Input High Voltage  
Input Low Voltage  
Vddq  
Vꢇꢈ(1)  
Vꢇꢉ(2)  
3.0  
3.6  
V
2.0  
Vddq + 0.3  
+0.8  
V
-0.3  
—
V
Note:  
1. Vꢇꢈ (max) = Vddq +1.2V (ꢑꢏꢉꢂꢅ ꢓꢇdꢐꢈ < 3ꢍꢂ).  
2. Vꢇꢉ (min) = -1.2V (ꢑꢏꢉꢂꢅ ꢓꢇdꢐꢈ < 3ꢍꢂ).  
3. All voltages are referenced to Vss.  
CAPACITANCE CHARACTERISTICS (At Tꢌ = 0 to +25°C, Vdd = Vddq = 3.3 ± 0.3V)  
Symbol  
Cꢇꢍ1  
Parameter  
Min.  
2
Max.  
Unit  
pF  
Input Capacitance: CLK  
4
3
5
Cꢇꢍ2  
Input Capacitance:All other input pins  
Data Input/Output Capacitance:I/Os  
1.3  
2
pF  
Cꢇ/ꢎ  
pF  
THERMAL RESISTANCE  
Package  
Substrate  
Theta-ja  
Theta-ja  
Theta-ja  
Theta-jc  
Units  
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)  
Alloy42 TSOP2(54)  
Copper TSOP2(54)  
BGA(54)  
4-layer  
4-layer  
4-layer  
89.5  
53.0  
42.9  
78.5  
47.7  
39.1  
73.3  
45.1  
36.9  
15.4  
11.8  
12.5  
C/W  
C/W  
C/W  
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Rev. D1  
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09/11/2019  
IS42/45S81600F, IS42/45S16800F  
DC ELECTRICAL CHARACTERISTICS 1 (Recommended Operation Conditions unless otherwise noted.)  
Symbol Parameter  
Idd1 (1)  
Operating Current  
Test Condition  
One bank active, CL = 3, BL = 2,  
-5  
-6  
-7  
Unit  
120  
100  
80  
mA  
tꢄꢉꢔ = tꢄꢉꢔ (min), tꢃꢄ = tꢃꢄ (min)  
Idd  
2
ꢑ
Precharge Standby Current CKE ≤ Vꢇꢉ (ꢋꢌꢊ), tꢄꢔ = 15ns  
2
2
2
2
2
2
mA  
mA  
(In Power-Down Mode)  
CS ≥ Vdd - 0.2V  
Idd2  
ꢑꢂ  
Precharge Standby Current CKE ≤ Vꢇꢉ (ꢋꢌꢊ), CLK ≤ Vꢇꢉ (ꢋꢌꢊ)  
with clock stop  
CS ≥ Vdd - 0.2V  
(In Power-Down Mode)  
(2)  
Idd  
2
ꢍ
Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vꢇꢈ (ꢋꢇꢍ)  
(In Non Power-Down Mode) tꢄꢔ = 15ns  
25  
15  
25  
15  
25  
15  
mA  
mA  
Idd2  
ꢍꢂ  
Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vꢇꢈ (ꢋꢇꢍ)  
with clock stop  
(In Non Power-Down Mode) All inputs stable  
(2)  
Idd  
3
ꢑ
Active Standby Current  
(In Power-Down Mode)  
CKE ≤ Vꢇꢉ (ꢋꢌꢊ), CS ≥ Vdd - 0.2V  
tꢄꢔ = 15ns  
6
6
6
6
6
6
mA  
mA  
Idd3  
ꢑꢂ  
Active Standby Current  
with clock stop  
CKE ≤ Vꢇꢉ (ꢋꢌꢊ), CLK ≤ Vꢇꢉ (ꢋꢌꢊ),  
CS ≥ Vdd - 0.2V  
(In Power-Down Mode)  
(2)  
Idd  
3
ꢍ
Active Standby Current  
CS ≥ Vdd - 0.2V, CKE ≥ Vꢇꢈ (ꢋꢇꢍ)  
tꢄꢔ = 15ns  
30  
20  
30  
20  
30  
20  
mA  
mA  
(In Non Power-Down Mode)  
Idd3  
ꢍꢂ  
Active Standby Current  
with clock stop  
CS ≥ Vdd - 0.2V, CKE ≥ Vꢇꢈ (ꢋꢇꢍ)  
All inputs stable  
(In Non Power-Down Mode)  
Operating Current  
Idd4  
All banks active, BL = Full Page, CL = 3, 130  
120  
100  
mA  
tꢄꢔ = tꢄꢔ (min)  
Idd  
5
6
Auto-Refresh Current  
Self-Refresh Current  
tꢃꢄ = tꢃꢄ (min), tꢄꢉꢔ = tꢄꢉꢔ (min)  
CKE ≤ 0.2V  
160  
2
140  
2
120  
2
mA  
mA  
Idd  
Notes:  
1. Idd (ꢋꢌꢊ) is specifieꢀ at the output open conꢀition.  
2. Input signals are changed one time during 30ns.  
DC ELECTRICAL CHARACTERISTICS 2 (Recommended Operation Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
Min  
Max  
Unit  
Iꢇꢉ  
Input Leakage Current  
0V ≤ Vin ≤ Vdd, with pins other than  
the tested pin at 0V  
-5  
5
µA  
Iꢎꢉ  
Output Leakage Current  
Output High Voltage Level  
Output Low Voltage Level  
Output is disabled, 0V ≤ Vout ≤ Vdd,  
Iꢎꢈ = -2mA  
-5  
2.4  
—
5
µA  
V
Vꢎꢈ  
Vꢎꢉ  
—
Iꢎꢉ = 2mA  
0.4  
V
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AC ELECTRICAL CHARACTERISTICS (1,2,3)  
-5  
-6  
-7  
Symbol Parameter  
Min.  
Max.  
Min. Max.  
Min. Max.  
Units  
tꢄꢔ3  
tꢄꢔ2  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
5
10  
—
—
6
10  
—
—
7
7.5  
—
—
ns  
ns  
tꢌꢄ3  
tꢌꢄ2  
Access Time From CLK  
CAS Latency = 3  
CAS Latency = 2  
—
—
5
5.4  
—
—
5.4  
6.5  
—
—
5.4  
5.4  
ns  
ns  
tꢄꢈ  
tꢄꢉ  
CLK HIGH Level Width  
CLK LOW Level Width  
Output Data Hold Time  
2
2
—
—
2.5  
2.5  
—
—
2.5  
2.5  
—
—
ns  
ns  
tꢎꢈ3  
tꢎꢈ2  
CAS Latency = 3  
CAS Latency = 2  
2.5  
2.5  
—
—
2.5  
2.5  
—
—
2.5  
2.5  
—
—
ns  
ns  
tꢉz  
Output LOW Impedance Time  
0
—
0
—
0
—
ns  
ns  
tꢈz3  
tꢈz2  
Output HIGH Impedance Time CAS Latency = 3  
CAS Latency = 2  
2.5  
2.5  
5
5.4  
2.5  
2.5  
5.4  
6.5  
2.5  
2.5  
5.4  
5.4  
tdꢂ  
Input Data Setup Time(2)  
Input Data Hold Time(2)  
Address Setup Time(2)  
Address Hold Time(2)  
CKE Setup Time(2)  
CKE Hold Time(2)  
Command Setup Time (CS, RAS, CAS, WE, DQM)(2)  
Command Hold Time (CS, RAS, CAS, WE, DQM)(2)  
Command Period (REF to REF / ACT to ACT)  
Command Period (ACT to PRE)  
Command Period (PRE to ACT)  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
55  
—
—
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
60  
—
—
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
60  
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tdꢈ  
tꢌꢂ  
—
—
—
tꢌꢈ  
—
—
—
tꢄꢔꢂ  
tꢄꢔꢈ  
tꢄꢋꢂ  
tꢄꢋꢈ  
tꢃꢄ  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tꢃꢌꢂ  
tꢃꢑ  
38  
100K  
—
42  
100K  
—
37  
100K  
—
15  
18  
15  
tꢃꢄd  
tꢃꢃd  
tdꢑꢉ  
Active Command To Read / Write Command Delay Time 15  
—
18  
—
15  
—
Command Period (ACT [0] to ACT[1])  
10  
10  
—
12  
—
14  
—
Input Data To Precharge  
Command Delay time  
—
12  
—
14  
—
tdꢌꢉ  
Input Data To Active / Refresh  
25  
—
30  
—
30  
—
ns  
Command Delay time (During Auto-Precharge)  
tꢋꢃd  
tddꢅ  
tꢊꢂꢃ  
tꢐ  
Mode Register Program Time  
Power Down Exit Setup Time  
Exit Self-Refresh to Active Time(4)  
Transition Time  
10  
5.0  
60  
—
—
—
12  
—
—
—
14  
—
—
—
ns  
ns  
ns  
6.0  
7.0  
67  
67  
0.3  
1.2 0.3  
1.2 0.3  
1.2  
ns  
tꢃꢅꢆ  
Refresh Cycle Time Tꢌ ≤ 70oC Com, Ind, A1, A2  
—
—
—
64  
64  
16  
—
—
—
64  
64  
16  
—
—
—
64  
64  
16  
ms  
ms  
ms  
(4096)  
Tꢌ ≤ 85oC Ind, A1, A2  
Tꢌ > 85oC A2  
Notes:  
1. The power-on sequence must be executed before starting memory operation.  
2. Measured with tꢐ = 1 ns. If clock rising time is longer than 1ns, (tꢐ /2 - 0.5) ns should be added to the parameter.  
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vꢇꢈ(min.) and Vꢇꢉ (max).  
4. Self-Refresh Mode is not supported for A2 grade with Tꢌ > +85oC.  
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OPERATING FREQUENCY / LATENCY RELATIONSHIPS  
SYMBOL PARAMETER  
-5  
-6  
-7  
UNITS  
—
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
5
10  
6
10  
7
7.5  
ns  
ns  
—
Operating Frequency  
CAS Latency = 3  
CAS Latency = 2  
200  
100  
166  
100  
143  
133  
MHz  
MHz  
tꢃꢄd  
tꢃꢌꢄ  
tꢃꢄ  
Active Command To Read/Write Command Delay Time  
RAS Latency (tꢃꢄd + tꢄꢌꢄ)  
CAS Latency = 3  
CAS Latency = 2  
3
2
3
2
3
2
cycle  
cycle  
CAS Latency = 3  
CAS Latency = 2  
6
4
6
4
6
4
cycle  
Command Period (REF to REF / ACT to ACT)  
Command Period (ACT to PRE)  
CAS Latency = 3  
CAS Latency = 2  
11  
6
10  
6
9
8
cycle  
cycle  
tꢃꢌꢂ  
tꢃꢑ  
CAS Latency = 3  
CAS Latency = 2  
8
4
7
5
6
5
cycle  
cycle  
Command Period (PRE to ACT)  
CAS Latency = 3  
CAS Latency = 2  
3
2
3
2
3
2
cycle  
cycle  
tꢃꢃd  
tꢄꢄd  
Command Period (ACT[0] to ACT [1])  
2
1
2
1
2
1
cycle  
cycle  
Column Command Delay Time  
(READ, READA, WRIT, WRITA)  
tdꢑꢉ  
tdꢌꢉ  
Input Data To Precharge Command Delay Time  
2
2
2
cycle  
Input Data To Active/Refresh Command Delay Time  
(During Auto-Precharge)  
CAS Latency = 3  
CAS Latency = 2  
5
4
5
4
5
4
cycle  
cycle  
tꢃꢕd  
tꢓꢕd  
tꢃqꢉ  
tꢓdꢉ  
tꢑqꢉ  
Burst Stop Command To Output in HIGH-Z Delay Time  
(Read)  
CAS Latency = 3  
CAS Latency = 2  
3
2
3
2
3
2
cycle  
cycle  
Burst Stop Command To Input in Invalid Delay Time  
(Write)  
0
0
0
cycle  
cycle  
cycle  
Precharge Command To Output in HIGH-Z Delay Time  
(Read)  
CAS Latency = 3  
CAS Latency = 2  
3
2
3
2
3
2
Precharge Command To Input in Invalid Delay Time  
(Write)  
0
0
0
Last Output To Auto-Precharge Start Time (Read)  
CAS Latency = 3  
CAS Latency = 2  
-2  
-1  
-2  
-1  
-2  
-1  
cycle  
cycle  
tqꢋd  
tdꢋd  
tꢋꢃd  
DQM To Output Delay Time (Read)  
DQM To Input Delay Time (Write)  
2
0
2
2
0
2
2
0
2
cycle  
cycle  
cycle  
Mode Register Set To Command Delay Time  
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AC TEST CONDITIONS  
Input Load  
Output Load  
t
CK  
t
CH  
t
CL  
3.0V  
1.4V  
1.4V  
CLK  
50Ω  
0V  
Z = 50Ω  
tCMS  
t
CMH  
Output  
3.0V  
1.4V  
50 pF  
INPUT  
0V  
t
AC  
tOH  
OUTPUT  
1.4V  
1.4V  
AC TEST CONDITIONS  
Parameter  
Rating  
AC Input Levels  
Input Rise and Fall Times  
0V to 3.0V  
1 ns  
Input Timing Reference Level  
1.4V  
Output Timing Measurement Reference Level  
1.4V  
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Initialization  
FUNCTIONAL DESCRIPTION  
SDRAMs must be powered up and initialized in a  
preꢀefineꢀ manner.  
The128MbSDRAMsarequad-bankDRAMswhichoperate  
at 3.3V and include a synchronous interface (all signals  
are registered on the positive edge of the clock signal,  
CLK). Each of the 33,554,432-bit banks is organized as  
4,096 rows by 512 columns by 16 bits or 4,096 rows by  
1,024 columns by 8 bits.  
The 128M SDRAM is initialized after the power is applied  
to Vdd and Vddq (simultaneously) and the clock is stable  
with DQM High and CKE High.  
A 100µs delay is required prior to issuing any command  
other than a COMMAND INHIBIT or a NOP.The COMMAND  
INHIBIT or NOP may be applied during the 100us period  
and should continue at least through the end of the period.  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for  
a programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an AC-  
TIVEcommandwhichisthenfollowedbyaREADorWRITE  
command. The address bits registered coincident with the  
ACTIVE command are used to select the bank and row  
to be accessed (BA0 and BA1 select the bank, A0-A11 select  
the row). The address bits A0-A9 (x8);A0-A8 (x16) registered  
coincident with the READ or WRITE command are used  
to select the starting column location for the burst access.  
With at least one COMMAND INHIBIT or NOP command  
having been applied, a PRECHARGE command should  
be applieꢀ once the 100µs ꢀelay has been satisfieꢀ. All  
banks must be precharged. This will leave all banks in an  
idle state after which at least two AUTO REFRESH cycles  
must be performed. After the AUTO REFRESH cycles are  
complete, the SDRAM is then ready for mode register  
programming.  
Prior to normal operation, the SDRAM must be initial-  
ized. The following sections provide detailed information  
coveringꢀeviceinitialiꢖation, registerꢀefinition, commanꢀ  
descriptions and device operation.  
The mode register should be loaded prior to applying  
any operational command because it will power up in an  
unknown state.  
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INITIALIZE AND LOAD MODE REGISTER(1)  
T0  
T1  
Tn+1  
To+1  
t
CL  
Tp+1  
Tp+2  
Tp+3  
tCK  
tCH  
CLK  
CKE  
tCKS t  
CKH  
t
CMS  
tCMH  
tCMS  
tCMH  
tCMS tCMH  
AUTO  
REFRESH  
AUTO  
Load MODE  
REGISTER  
COMMAND  
NOP  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
REFRESH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
A0-A9, A11  
A10  
ROW  
ROW  
BANK  
CODE  
AS  
tAH  
ALL BANKS  
CODE  
SINGLE BANK  
ALL BANKS  
AS  
tAH  
BA0, BA1  
DQ  
CODE  
t
RP  
t
RC  
t
RC  
tMRD  
T
Power-up: VCC  
Precharge AUTO REFRESH  
and CLK stable all banks  
AUTO REFRESH  
Program MODE REGISTER(2, 3, 4)  
DON'T CARE  
T = 100µs Min.  
Notes:  
1. If CS is High at clock High time, all commands applied are NOP.  
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.  
3. JEDEC and PC100 specify three clocks.  
4. Outputs are guaranteed High-Z after the command is issued.  
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AUTO-REFRESH CYCLE  
T0  
T1  
T2  
Tn+1  
To+1  
tCK  
tCL  
tCH  
CLK  
CKE  
t
CKS CKH  
t
tCMS  
tCMH  
Auto  
Refresh  
Auto  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
Refresh  
DQM/  
DQML, DQMH  
A0-A9, A11  
A10  
ROW  
ROW  
BANK  
ALL BANKS  
SINGLE BANK  
BANK(s)  
BA0, BA1  
DQ  
tAS  
tAH  
High-Z  
tRP  
tRC  
t
RC  
DON'T CARE  
Notes:  
1. CAS latency = 2, 3  
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SELF-REFRESH CYCLE  
T0  
T1  
T2  
Tn+1  
To+1  
To+2  
t
CK  
tCH  
t
CL  
CLK  
CKE  
t
CKS  
t
CKH  
t
CKS  
tRAS  
t
CKS  
tCMS  
tCMH  
Auto  
Auto  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
Refresh  
Refresh  
DQM/  
DQML, DQMH  
A0-A9, A11  
A10  
ALL BANKS  
SINGLE BANK  
t
AS  
tAH  
BA0, BA1  
DQ  
BANK  
High-Z  
tRP  
tXSR  
Precharge all  
active banks  
Enter self  
refresh mode  
CLK stable prior to exiting  
self refresh mode  
Exit self refresh mode  
(Restart refresh time base)  
DON'T CARE  
Note:  
1. Self-Refresh Mode is not supported for A2 grade with Tꢌ > +85oC.  
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REGISTER DEFINITION  
Mode Register  
The moꢀe register is useꢀ to ꢀefine the specific moꢀe  
of operation of the SDRAM. This ꢀefinition incluꢀes the  
selection of a burst length, a burst type, a CAS latency,  
an operating mode and a write burst mode, as shown in  
MODE REGISTER DEFINITION.  
Mode register bits M0-M2 specify the burst length, M3  
specifiesthetypeofburst(sequentialorinterleaved), M4-M6  
specify the CAS latency, M7 and M8 specify the operating  
moꢀe, M9 specifies the WRITE burst moꢀe, anꢀ M10 anꢀ  
M11 are reserved for future use.  
The mode register is programmed via the LOAD MODE  
REGISTER command and will retain the stored information  
until it is programmed again or the device loses power.  
The mode register must be loaded when all banks are  
iꢀle, anꢀ the controller must wait the specifieꢀ time before  
initiatingthesubsequentoperation.Violatingeitherofthese  
reꢁuirements will result in unspecifieꢀ operation.  
MODE REGISTER DEFINITION  
Address Bus  
BA1 BA0 A11 A10 A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Mode Register (Mx)  
Reserved(1)  
Burst Length  
M2 M1 M0  
M3=0  
M3=1  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
Full Page Reserved  
Burst Type  
M3  
Type  
0
1
Sequential  
Interleaved  
Latency Mode  
M6 M5 M4  
CAS Latency  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
Reserved  
2
3
Reserved  
Reserved  
Reserved  
Reserved  
Operating Mode  
M8 M7 M6-M0 Mode  
0
0
Defined Standard Operation  
All Other States Reserved  
—
—
—
Write Burst Mode  
M9  
0
Mode  
Programmed Burst Length  
Single Location Access  
1. To ensure compatibility with future devices,  
should program BA1, BA0, A11, A10 = "0"  
1
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BURST LENGTH  
ing that the burst will wrap within the block if a boundary  
is reached. The block is uniquely selected by A1-A8 (x16)  
when the burst length is set to two; by A2-A8 (x16) when  
the burst length is set to four; and byA3-A8 (x16) when the  
burstlengthissettoeight.Theremaining(leastsignificant)  
address bit(s) is (are) used to select the starting location  
within the block. Full-page bursts wrap within the page if  
the boundary is reached.  
ReadandwriteaccessestotheSDRAMareburstoriented,  
with the burst length being programmable, as shown in  
MODE REGISTER DEFINITION. The burst length deter-  
mines the maximum number of column locations that can  
be accessed for a given READ or WRITE command. Burst  
lengths of 1, 2, 4 or 8 locations are available for both the  
sequential and the interleaved burst types, and a full-page  
burst is available for the sequential type. The full-page  
burst is used in conjunction with the BURST TERMINATE  
command to generate arbitrary burst lengths.  
Burst Type  
Accesses within a given burst may be programmed to be  
either sequential or interleaved; this is referred to as the  
burst type and is selected via bit M3.  
Reservedstatesshouldnotbeused,asunknownoperation  
or incompatibility with future versions may result.  
When a READ or WRITE command is issued, a block of  
columnseꢁualtotheburstlengthiseffectivelyselecteꢀ.All  
accesses for that burst take place within this block, mean-  
The ordering of accesses within a burst is determined by  
the burst length, the burst type and the starting column  
address, as shown in BURST DEFINITION table.  
BURST DEFINITION  
Burst  
Starting Column  
Order of Accesses Within a Burst  
Length  
Address  
Type = Sequential  
Type = Interleaved  
A 0  
2
4
0
1
0-1  
1-0  
0-1  
1-0  
A 1  
0
A 0  
0
0-1-2-3  
1-2-3-0  
2-3-0-1  
3-0-1-2  
0-1-2-3  
1-0-3-2  
2-3-0-1  
3-2-1-0  
0
1
1
0
1
1
A 2  
A 1  
0
A 0  
0
0
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
Not Supported  
0
0
1
0
1
0
8
0
1
1
1
0
0
1
0
1
1
1
1
0
1
1
Full  
Page  
(y)  
n = A0-A7  
Cn, Cn + 1, Cn + 2  
Cn + 3, Cn + 4...  
…Cn - 1,  
(location 0-y)  
Cn…  
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CAS Latency  
Operating Mode  
The CAS latency is the delay, in clock cycles, between  
the registration of a READ command and the availability of  
the first piece of output ꢀata. The latency can be set to two  
or three clocks.  
ThenormaloperatingmodeisselectedbysettingM7andM8  
to zero; the other combinations of values for M7 and M8 are  
reserved for future use and/or test modes. The programmed  
burst length applies to both READ and WRITE bursts.  
If a READ command is registered at clock edge n, and  
the latency is m clocks, the data will be available by clock  
edge n + m. The DQs will start driving as a result of the  
clock edge one cycle earlier (n + m - 1), and provided that  
the relevant access times are met, the data will be valid by  
clock edge n + m. For example, assuming that the clock  
cycle time is such that all relevant access times are met,  
if a READ command is registered at T0 and the latency  
is programmed to two clocks, the DQs will start driving  
after T1 and the data will be valid by T2, as shown in CAS  
Latency diagrams. The Allowable Operating Frequency  
table indicates the operating frequencies at which each  
CAS latency setting can be used.  
Test modes and reserved states should not be used be-  
cause unknown operation or incompatibility with future  
versions may result.  
Write Burst Mode  
When M9 = 0, the burst length programmed via M0-M2  
applies to both READ and WRITE bursts; when M9 = 1,  
the programmed burst length applies to READ bursts, but  
write accesses are single-location (nonburst) accesses.  
CAS Latency  
Allowable Operating Frequency (MHz)  
Speed  
CAS Latency = 2  
CAS Latency = 3  
Reserved states should not be used as unknown operation  
or incompatibility with future versions may result.  
-5  
100  
100  
133  
200  
166  
143  
-6  
-7  
CAS LATENCY  
T0  
T1  
T2  
T3  
CLK  
READ  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 2  
T0  
T1  
T2  
T3  
T4  
CLK  
READ  
NOP  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 3  
DON'T CARE  
UNDEFINED  
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ACTIVATING SPECIFIC ROW WITHIN SPE-  
CIFIC BANK  
CHIP OPERATION  
BANK/ROW ACTIVATION  
Before any READ or WRITE commands can be issued  
to a bank within the SDRAM, a row in that bank must be  
“opened.” This is accomplished via theACTIVE command,  
which selects both the bank and the row to be activated  
(see Activating Specific Row Within Specific Bank).  
CLK  
HIGH  
CKE  
CS  
After opening a row (issuing anACTIVE command), a READ  
or WRITE command may be issued to that row, subject to  
the tꢃꢄd specification. Minimum tꢃꢄd should be divided  
by the clock period and rounded up to the next whole  
number to determine the earliest clock edge after the AC-  
TIVE command on which a READ or WRITE command  
can be entered. For example, a tꢃꢄd specification of 18ns  
with a 125 MHz clock (8ns period) results in 2.25 clocks,  
rounꢀeꢀ to 3. This is reflecteꢀ in the following example,  
which covers any case where 2 < [tꢃꢄd (MIN)/tꢄꢔ] ≤ 3.  
(Thesameproceꢀureisuseꢀtoconvertotherspecification  
limits from time units to clock cycles).  
RAS  
CAS  
WE  
A0-A11  
BA0, BA1  
ROW ADDRESS  
BANK ADDRESS  
A subseꢁuent ACTIVE commanꢀ to a ꢀifferent row in the  
same bank can only be issued after the previous active  
row has been “closed” (precharged). The minimum time  
interval between successive ACTIVE commands to the  
same bank is ꢀefineꢀ by tꢃꢄ.  
A subsequent ACTIVE command to another bank can be  
issueꢀwhilethefirstbankisbeingaccesseꢀ, whichresults  
in a reduction of total row-access overhead. The minimum  
time interval between successive ACTIVE commands to  
ꢀifferent banks is ꢀefineꢀ by tꢃꢃd.  
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3  
T0  
T1  
T2  
T3  
T4  
CLK  
READ or  
WRITE  
ACTIVE  
NOP  
NOP  
COMMAND  
t
RCD  
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READS  
READ COMMAND  
READ bursts are initiated with a READ command, as  
shown in the READ COMMAND diagram.  
The starting column and bank addresses are provided with  
theREADcommand,andautoprechargeiseitherenabledor  
disabled for that burst access. If auto precharge is enabled,  
the row being accessed is precharged at the completion of  
the burst. For the generic READ commands used in the fol-  
lowing illustrations, auto precharge is disabled.  
CLK  
HIGH  
CKE  
CS  
RAS  
During READ bursts, the valid data-out element from the  
starting column address will be available following the  
CAS latency after the READ command. Each subsequent  
data-out element will be valid by the next positive clock  
edge. The CAS Latency diagram shows general timing  
for each possible CAS latency setting.  
CAS  
WE  
Upon completion of a burst, assuming no other commands  
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst  
will continue until terminated. (At the end of the page, it will  
wrap to column 0 and continue.)  
COLUMN ADDRESS  
AUTO PRECHARGE  
A0-A9  
A11  
Data from any READ burst may be truncated with a sub-  
seꢁuent READ commanꢀ, anꢀ ꢀata from a fixeꢀ-length  
READ burst may be immediately followed by data from a  
READ commanꢀ. In either case, a continuous flow of ꢀata  
can be maintaineꢀ. The first ꢀata element from the new  
burst follows either the last element of a completed burst  
or the last desired data element of a longer burst which  
is being truncated.  
A10  
NO PRECHARGE  
BANK ADDRESS  
BA0, BA1  
Note: A9 is "Don't Care" for x16.  
The DQM input is used to avoid I/O contention, as shown  
in Figures RW1 and RW2. The DQM signal must be as-  
serted (HIGH) at least three clocks prior to the WRITE  
commanꢀ (DQM latency is two clocks for output buffers)  
to suppress data-out from the READ. Once the WRITE  
command is registered, the DQs will go High-Z (or remain  
High-Z), regardless of the state of the DQM signal, pro-  
vided the DQM was active on the clock just prior to the  
WRITE command that truncated the READ command.  
If not, the second WRITE will be an invalid WRITE. For  
example, if DQM was LOW during T4 in Figure RW2, then  
the WRITEs at T5 and T7 would be valid, while the WRITE  
at T6 would be invalid.  
ThenewREADcommandshouldbeissuedxcyclesbefore  
the clock edge at which the last desired data element is  
valid, where x equals the CAS latency minus one. This is  
shown in Consecutive READ Bursts for CAS latencies of  
two and three; data element n + 3 is either the last of a  
burstoffourorthelastdesiredofalongerburst.The128Mb  
SDRAM uses a pipelined architecture and therefore does  
not require the 2n rule associated with a prefetch architec-  
ture.AREAD command can be initiated on any clock cycle  
following a previous READ command. Full-speed random  
read accesses can be performed to the same bank, as  
shown in Random READ Accesses, or each subsequent  
READ may be performeꢀ to a ꢀifferent bank.  
The DQM signal must be de-asserted prior to the WRITE  
commanꢀ (DQM latency is ꢖero clocks for input buffers)  
to ensure that the written data is not masked.  
Data from any READ burst may be truncated with a sub-  
seꢁuent WRITE commanꢀ, anꢀ ꢀata from a fixeꢀ-length  
READ burst may be immediately followed by data from a  
WRITE command (subject to bus turnaround limitations).  
The WRITE burst may be initiated on the clock edge im-  
mediately following the last (or last desired) data element  
from the READ burst, provided that I/O contention can be  
avoided. In a given system design, there may be a pos-  
sibility that the device driving the input data will go Low-Z  
before the SDRAM DQs go High-Z. In this case, at least  
a single-cycle delay should occur between the last read  
data and the WRITE command.  
Afixeꢀ-lengthREADburstmaybefolloweꢀby,ortruncateꢀ  
with, aPRECHARGE commandtothesamebank(provided  
that auto precharge was not activated), and a full-page burst  
may be truncated with a PRECHARGE command to the  
samebank.ThePRECHARGEcommandshouldbeissued  
x cycles before the clock edge at which the last desired  
data element is valid, where x equals the CAS latency  
28  
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minus one. This is shown in the READ to PRECHARGE  
diagram for each possible CAS latency; data element n +  
3 is either the last of a burst of four or the last desired of  
a longer burst. Following the PRECHARGE command, a  
subsequent command to the same bank cannot be issued  
until tꢃꢑ is met. Note that part of the row precharge time  
is hidden during the access of the last data element(s).  
In the case of a fixeꢀ-length burst being executeꢀ to  
completion, a PRECHARGE command issued at the  
optimum time (as described above) provides the same  
operation that woulꢀ result from the same fixeꢀ-length  
burst with auto precharge. The disadvantage of the PRE-  
CHARGE command is that it requires that the command  
and address buses be available at the appropriate time to  
issue the command; the advantage of the PRECHARGE  
commanꢀ is that it can be useꢀ to truncate fixeꢀ-length  
or full-page bursts.  
Full-page READ bursts can be truncated with the BURST  
TERMINATE commanꢀ, anꢀ fixeꢀ-length READ bursts  
may be truncated with a BURST TERMINATE command,  
providedthatautoprechargewasnotactivated.TheBURST  
TERMINATE command should be issued x cycles before  
the clock edge at which the last desired data element is  
valid, where x equals the CAS latency minus one. This is  
shown in the READ Burst Termination diagram for each  
possibleCASlatency;dataelementn+3isthelastdesired  
data element of a longer burst.  
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RW1 - READ to WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
t
HZ  
DOUT n+1  
DOUT n+2  
DOUT  
n
DIN b  
CAS Latency - 2  
t
DS  
DON'T CARE  
RW2 - READ to WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
DQM  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
t
HZ  
DOUT  
n
DIN  
b
CAS Latency - 3  
t
DS  
DON'T CARE  
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CONSECUTIVE READ BURSTS  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
DOUT  
b
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
READ  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
ADDRESS  
DQ  
DOUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
D
OUT  
b
CAS Latency - 3  
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RANDOM READ ACCESSES  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
READ  
READ  
READ  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
DOUT  
n
DOUT  
b
DOUT  
m
DOUT  
x
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
READ  
READ  
READ  
NOP  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
DOUT  
n
DOUT  
b
DOUT  
m
DOUT  
x
CAS Latency - 3  
DON'T CARE  
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READ BURST TERMINATION  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
COMMAND  
ADDRESS  
DQ  
BURST  
TERMINATE  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
x = 1 cycle  
BANK a,  
COL n  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
BURST  
TERMINATE  
READ  
NOP  
NOP  
NOP  
NOP  
x = 2 cycles  
NOP  
NOP  
BANK,  
COL n  
DOUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 3  
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ALTERNATING BANK READ ACCESSES  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
ACTIVE  
COMMAND  
NOP  
READ  
NOP  
ACTIVE  
NOP  
READ  
NOP  
ACTIVE  
tCMS tCMH  
DQM/  
DQML, DQMH  
tAS tAH  
COLUMN m(2)  
ROW  
ROW  
COLUMN b(2)  
ROW  
ROW  
A0-A9, A11  
A10  
ROW  
tAS tAH  
ENABLE AUTO PRECHARGE  
ENABLE AUTO PRECHARGE  
ROW  
tAS tAH  
BANK 0  
BANK 3  
BANK 3  
BANK 0  
BA0, BA1  
BANK 0  
t
LZ  
tOH  
tOH  
tOH  
tOH  
tOH  
DQ  
DOUT  
m
D
OUT m+  
1
D
OUT m+  
2
D
OUT m+  
3
D
OUT  
b
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tRCD - BANK 0  
tRRD  
CAS Latency - BANK 0  
tRP - BANK 0  
tRCD - BANK 0  
tRCD - BANK 3  
CAS Latency - BANK 3  
tRAS - BANK 0  
tRC - BANK 0  
DON'T CARE  
Notes:  
1) CAS latency = 2, Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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READ - FULL-PAGE BURST  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
Tn+1  
Tn+2  
Tn+3  
Tn+4  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
ACTIVE  
COMMAND  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
BURST TERM  
NOP  
NOP  
tCMS tCMH  
DQM/  
DQML, DQMH  
tAS tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
tAS tAH  
ROW  
tAS tAH  
BA0, BA1  
BANK  
BANK  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tHZ  
D
OUT  
m
D
OUT m+  
1
D
OUT m+  
2
D
OUT m-  
1
D
OUT  
m
D
OUT m+  
1
DQ  
tLZ  
t
OH  
tOH  
tOH  
tOH  
t
OH  
tOH  
tRCD  
CAS Latency  
each row (x4) has  
1,024 locations  
DON'T CARE  
UNDEFINED  
Full page Full-page burst not self-terminating.  
completion Use BURST TERMINATE command.  
Notes:  
1) CAS latency = 2, Burst Length = Full Page  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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READ - DQM OPERATION  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
DISABLE AUTO PRECHARGE  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
OH  
tOH  
tOH  
t
AC  
tAC  
D
OUT  
m
D
OUT m+  
2
D
OUT m+  
3
DQ  
tLZ  
tLZ  
t
HZ  
tAC  
tHZ  
DON'T CARE  
UNDEFINED  
t
RCD  
CAS Latency  
Notes:  
1) CAS latency = 2, Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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READ to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
t
RP  
PRECHARGE  
READ  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
NOP  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
t
RQL  
High-Z  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
t
RP  
PRECHARGE  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
BANK,  
COL n  
BANK,  
COL b  
BANK a,  
ROW  
t
RQL  
High-Z  
DOUT  
n
DOUT n+1  
D
OUT n+2  
DOUT n+3  
CAS Latency - 3  
DON'T CARE  
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WRITES  
An example is shown in WRITE to WRITE diagram. Data  
n + 1 is either the last of a burst of two or the last desired  
of a longer burst. The 128Mb SDRAM uses a pipelined  
architecture and therefore does not require the 2n rule as-  
sociated with a prefetch architecture. A WRITE command  
can be initiated on any clock cycle following a previous  
WRITEcommand.Full-speedrandomwriteaccesseswithin  
a page can be performed to the same bank, as shown in  
Random WRITE Cycles, or each subsequent WRITE may  
be performeꢀ to a ꢀifferent bank.  
WRITE bursts are initiated with a WRITE command, as  
shown in WRITE Command diagram.  
WRITE COMMAND  
CLK  
HIGH  
CKE  
Data for any WRITE burst may be truncated with a subse-  
ꢁuentREADcommanꢀ, anꢀꢀataforafixeꢀ-lengthWRITE  
burstmaybeimmediatelyfollowedbyasubsequentREAD  
command. Once the READ com mand is registered, the  
data inputs will be ignored, and WRITEs will not be ex-  
ecuted. An example is shown in WRITE to READ. Data  
n + 1 is either the last of a burst of two or the last desired  
of a longer burst.  
CS  
RAS  
CAS  
WE  
Data for a fixeꢀ-length WRITE burst may be followeꢀ  
by, or truncated with, a PRECHARGE command to the  
same bank (provided that auto precharge was not acti-  
vated), and a full-page WRITE burst may be truncated  
with a PRECHARGE command to the same bank. The  
PRECHARGE command should be issued tdꢑꢉ after the  
clock edge at which the last desired input data element is  
registered. The auto precharge mode requires a tdꢑꢉ of  
at least one clock plus time, regardless of frequency. In  
addition, when truncating a WRITE burst, the DQM signal  
must be used to mask input data for the clock edge prior  
to, and the clock edge coincident with, the PRECHARGE  
command. An example is shown in the WRITE to PRE-  
CHARGE diagram. Data n+1 is either the last of a burst  
of two or the last desired of a longer burst. Following the  
PRECHARGE command, a subsequent command to the  
same bank cannot be issued until tꢃꢑ is met.  
COLUMN ADDRESS  
AUTO PRECHARGE  
A0-A9  
A11  
A10  
NO PRECHARGE  
BANK ADDRESS  
BA0, BA1  
Note: A9 is "Don't Care" for x16.  
The starting column and bank addresses are provided with  
theWRITEcommand,andautoprechargeiseitherenabled  
or disabled for that access. If auto precharge is enabled,  
the row being accessed is precharged at the completion of  
the burst. For the generic WRITE commands used in the  
following illustrations, auto precharge is disabled.  
Inthecaseofafixeꢀ-lengthburstbeingexecuteꢀtocomple-  
tion, a PRECHARGE command issued at the optimum  
time (as described above) provides the same operation that  
woulꢀ result from the same fixeꢀ-length burst with auto  
precharge.ThedisadvantageofthePRECHARGEcommand  
is that it requires that the command and address buses be  
available at the appropriate time to issue the command;  
the advantage of the PRECHARGE command is that it  
can be useꢀ to truncate fixeꢀ-length or full-page bursts.  
During WRITE bursts, the first valiꢀ data-in element will be  
registered coincident with the WRITE command. Subse-  
quentdataelementswillberegisteredoneachsuccessive  
positive clock eꢀge. Upon completion of a fixeꢀ-length  
burst, assuming no other commands have been initiated,  
the DQs will remain High-Z and any additional input data  
will be ignored (see WRITE Burst). A full-page burst will  
continue until terminated. (At the end of the page, it will  
wrap to column 0 and continue.)  
Fixed-length or full-page WRITE bursts can be truncated  
with the BURST TERMINATE command. When truncat-  
ing a WRITE burst, the input data applied coincident with  
the BURST TERMINATE command will be ignored. The  
last data written (provided that DQM is LOW at that time)  
will be the input data applied one clock previous to the  
BURST TERMINATE command. This is shown in WRITE  
Burst Termination, where data n is the last desired data  
element of a longer burst.  
Data for any WRITE burst may be truncated with a subse-  
ꢁuent WRITE commanꢀ, anꢀ ꢀata for a fixeꢀ-length WRITE  
burst may be immediately followed by data for a WRITE  
command. The new WRITE command can be issued on  
any clock following the previous WRITE command, and the  
data provided coincident with the new command applies to  
the new command.  
38  
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WRITE BURST  
T0  
T1  
T2  
T3  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
NOP  
NOP  
BANK,  
COL n  
DIN  
n
DIN n+1  
DON'T CARE  
WRITE TO WRITE  
T0  
T1  
T2  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
DIN  
n
DIN n+1  
DIN b  
DON'T CARE  
RANDOM WRITE CYCLES  
T0  
T1  
T2  
T3  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
WRITE  
WRITE  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
DIN  
n
DIN  
b
DIN  
m
DIN x  
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WRITE to READ  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
READ  
NOP  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
DIN  
n
DIN n+1  
D
OUT  
b
DOUT b+1  
CAS Latency - 2  
DON'T CARE  
WP1 - WRITE to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
tRP  
PRECHARGE  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
NOP  
NOP  
ACTIVE  
NOP  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
t
DPL  
DIN  
n
D
IN n+1  
DIN n+2  
DON'T CARE  
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WP2 - WRITE to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
tRP  
COMMAND  
ADDRESS  
DQ  
PRECHARGE  
WRITE  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
tDPL  
DIN  
n
DIN n+1  
DON'T CARE  
WRITE Burst Termination  
T0  
T1  
T2  
CLK  
BURST  
TERMINATE  
NEXT  
COMMAND  
ADDRESS  
DQ  
WRITE  
COMMAND  
BANK,  
COL n  
(ADDRESS)  
DIN  
n
(DATA)  
DON'T CARE  
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WRITE - FULL PAGE BURST  
T0  
T1  
T2  
T3  
T4  
T5  
Tn+1  
NOP  
Tn+2  
t
CK  
t
CL  
t
CH  
CLK  
CKE  
t
CKS CKH  
t
t
CMS  
t
CMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
BURST TERM  
NOP  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ROW  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+  
3
DIN m-1  
DQ  
tRCD  
Full page completed  
DON'T CARE  
Notes:  
1) Burst Length = Full Page  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
42  
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WRITE - DQM OPERATION  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
t
CK  
tCL  
t
CH  
CLK  
CKE  
t
CKS CKH  
t
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
DISABLE AUTO PRECHARGE  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
DS  
t
DH  
tDS  
t
DH  
t
DS  
t
DH  
D
IN  
m
D
IN m+  
2
DIN m+3  
DQ  
t
RCD  
DON'T CARE  
Notes:  
1) Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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ALTERNATING BANK WRITE ACCESSES  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
t
CK  
t
CL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
ACTIVE  
t
CMS tCMH  
DQM/DQML  
DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
COLUMN b(2)  
ROW  
ROW  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ENABLE AUTO PRECHARGE  
ROW  
AS  
tAH  
BANK 0  
BANK 1  
BANK 1  
BANK 0  
BA0, BA1  
BANK 0  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
t
DS  
tDH  
t
DS  
tDH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+  
3
DIN  
b
D
IN b+  
1
D
IN b+  
2
DIN b+3  
t
t
t
t
RCD - BANK 0  
RRD  
t
DPL - BANK 0  
tRP - BANK 0  
t
RCD - BANK 0  
t
RCD - BANK 1  
tDPL - BANK 1  
RAS - BANK 0  
RC - BANK 0  
DON'T CARE  
Notes:  
1) Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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CLOCK SUSPEND  
of a suspended internal clock edge is ignored; any data  
presentontheDQpinsremainsdriven;andburstcounters  
are not incremented, as long as the clock is suspended.  
(See following examples.)  
Clock suspend mode occurs when a column access/burst  
is in progress and CKE is registered LOW. In the clock  
suspend mode, the internal clock is deactivated, “freezing”  
the synchronous logic.  
Clock suspend mode is exited by registering CKE HIGH;  
the internal clock and related operation will resume on the  
subsequent positive clock edge.  
For each positive clock edge on which CKE is sampled  
LOW, the next internal positive clock edge is suspended.  
Any command or data present on the input pins at the time  
Clock Suspend During WRITE Burst  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
CKE  
INTERNAL  
CLOCK  
COMMAND  
ADDRESS  
DQ  
NOP  
WRITE  
NOP  
NOP  
BANK a,  
COL n  
D
IN  
n
DIN n+1  
DIN n+2  
DON'T CARE  
Clock Suspend During READ Burst  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
CKE  
INTERNAL  
CLOCK  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
BANK a,  
COL n  
DOUT  
n
D
OUT n+1  
DOUT n+2  
DOUT n+3  
DON'T CARE  
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CLOCK SUSPEND MODE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCKS tCKH  
tCMS tCMH  
COMMAND  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE  
NOP  
tCMS tCMH  
DQM/DQML  
DQMH  
tAS tAH  
COLUMN n(2)  
A0-A9, A11  
A10  
COLUMN m(2)  
tAS tAH  
tAS tAH  
BA0, BA1  
BANK  
BANK  
tDS tDH  
tAC  
tAC  
tHZ  
DQ  
DOUT  
m
D
OUT m+1  
DIN e  
D
IN e+1  
tLZ  
tOH  
DON'T CARE  
UNDEFINED  
Notes:  
1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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PRECHARGE  
PRECHARGE Command  
ThePRECHARGEcommanꢀ(seefigure)isuseꢀtoꢀeacti-  
vate the open row in a particular bank or the open row in all  
banks. The bank(s) will be available for a subsequent row  
access some specifieꢀ time (tꢃꢑ) after the PRECHARGE  
command is issued. InputA10 determines whether one or  
all banks are to be precharged, and in the case where only  
one bank is to be precharged, inputs BA0, BA1 select the  
bank. When all banks are to be precharged, inputs BA0,  
BA1 are treated as “Don’t Care.” Once a bank has been  
precharged, it is in the idle state and must be activated  
prior to any READ or WRITE commands being issued to  
that bank.  
CLK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
POWER-DOWN  
Power-down occurs if CKE is registered LOW coincident  
with a NOP or COMMAND INHIBIT when no accesses  
are in progress. If power-down occurs when all banks are  
idle, this mode is referred to as precharge power-down;  
if power-down occurs when there is a row active in either  
bank, this mode is referred to as active power-down.  
Entering power-down deactivates the input and output  
buffers, excluꢀingCKE, formaximumpowersavingswhile  
in standby. The device may not remain in the power-down  
statelongerthantherefreshperiod(64ms)sincenorefresh  
operations are performed in this mode.  
A0-A9, A11  
ALL BANKS  
A10  
BANK SELECT  
BANK ADDRESS  
BA0, BA1  
The power-down state is exited by registering a NOP or  
COMMAND INHIBIT and CKE HIGH at the desired clock  
edge (meeting tꢄꢔꢂ). See figure below.  
POWER-DOWN  
CLK  
t
CKS  
≥ tCKS  
CKE  
COMMAND  
NOP  
NOP  
ACTIVE  
tRCD  
tRAS  
t
RC  
All banks idle  
Input buffers gated off  
Enter power-down mode  
Exit power-down mode  
less than 64ms  
DON'T CARE  
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POWER-DOWN MODE CYCLE  
T0  
T1  
T2  
Tn+1  
Tn+2  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS  
t
CKH  
t
CKS  
tCKS  
tCMS  
tCMH  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
DQM/DQML  
DQMH  
A0-A9, A11  
A10  
ROW  
ROW  
ALL BANKS  
SINGLE BANK  
t
AS  
tAH  
BA0, BA1  
DQ  
BANK  
BANK  
High-Z  
Two clock cycles  
Input buffers gated  
All banks idle  
off while in  
power-down mode  
Precharge all  
active banks  
All banks idle, enter  
power-down mode  
DON'T CARE  
Exit power-down mode  
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BURST READ/SINGLE WRITE  
Four cases where CONCURRENT AUTO PRECHARGE  
occurs are ꢀefineꢀ below.  
The burst read/single write mode is entered by programming  
the write burst mode bit (M9) in the mode register to a logic  
1. In this mode, all WRITE commands result in the access  
of a single column location (burst of one), regardless of  
the programmed burst length. READ commands access  
columns according to the programmed burst length and  
sequence,justasinthenormalmodeofoperation(M9=0).  
READ with Auto Precharge  
1. Interrupted by a READ (with or without auto precharge):  
AREADtobankmwillinterruptaREADonbankn, CAS  
latency later. The PRECHARGE to bank n will begin  
when the READ to bank m is registered.  
CONCURRENT AUTO PRECHARGE  
2.InterruptedbyaWRITE(withorwithoutautoprecharge):  
A WRITE to bank m will interrupt a READ on bank n  
whenregistered.DQMshouldbeusedthreeclocksprior  
to the WRITE command to prevent bus contention. The  
PRECHARGE to bank n will begin when the WRITE to  
bank m is registered.  
An access command (READ or WRITE) to another bank  
while an access command with auto precharge enabled is  
executing is not allowed by SDRAMs, unless the SDRAM  
supports CONCURRENT AUTO PRECHARGE. ISSI  
SDRAMs support CONCURRENT AUTO PRECHARGE.  
READ With Auto Precharge interrupted by a READ  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
READ - AP  
BANK n  
READ - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Idle  
COMMAND  
BANK n  
Page Active  
READ with Burst of 4  
Page Active  
Interrupt Burst, Precharge  
t
RP - BANK n  
tRP - BANK m  
Internal States  
BANK m  
READ with Burst of 4  
Precharge  
BANK n,  
COL a  
BANK n,  
COL b  
ADDRESS  
DQ  
D
OUT  
a
DOUT a+1  
DOUT  
b
DOUT b+1  
CAS Latency - 3 (BANK n)  
DON'T CARE  
CAS Latency - 3 (BANK m)  
READ With Auto Precharge interrupted by a WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
READ - AP  
BANK n  
WRITE - AP  
BANK m  
COMMAND  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Idle  
BANK n  
READ with Burst of 4  
Page Active  
Interrupt Burst, Precharge  
Page Active  
tRP - BANK n  
tDPL - BANK m  
Internal States  
BANK m  
WRITE with Burst of 4  
Write-Back  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQM  
DQ  
D
OUT  
a
DIN  
b
DIN b+1  
DIN b+2  
DIN b+3  
CAS Latency - 3 (BANK n)  
DON'T CARE  
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WRITE with Auto Precharge  
4.InterruptedbyaWRITE(withorwithoutautoprecharge):  
WRITE to bank m will interrupt a WRITE on bank n  
3. Interrupted by a READ (with or without auto precharge):  
AREADtobankmwillinterruptaWRITEonbanknwhen  
registered, with the data-out appearing (CAS latency)  
later. The PRECHARGE to bank n will begin after tdꢑꢉ  
is met, where tdꢑꢉ begins when the READ to bank m is  
registered. The last valid WRITE to bank n will be data-  
in registered one clock prior to the READ to bank m.  
A
whenregistered.ThePRECHARGEtobanknwillbegin  
after tdꢑꢉ is met, where tdꢑꢉ begins when the WRITE  
to bank m is registered. The last valid data WRITE  
to bank n will be data registered one clock prior to a  
WRITE to bank m.  
WRITE With Auto Precharge interrupted by a READ  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
BANK n  
WRITE - AP  
BANK n  
READ - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Page Active  
WRITE with Burst of 4 Interrupt Burst, Write-Back  
DPL - BANK n  
Precharge  
t
tRP - BANK n  
Internal States  
tRP - BANK m  
BANK m  
Page Active  
READ with Burst of 4  
Precharge  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQ  
DIN  
a
DIN a+1  
DOUT  
b
DOUT b+1  
CAS Latency - 3 (BANK m)  
DON'T CARE  
WRITE With Auto Precharge interrupted by a WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
BANK n  
WRITE - AP  
BANK n  
WRITE - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Page Active  
WRITE with Burst of 4  
Interrupt Burst, Write-Back  
DPL - BANK n  
Precharge  
t
t
RP - BANK n  
Internal States  
tDPL - BANK m  
BANK m  
Page Active  
WRITE with Burst of 4  
Write-Back  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQ  
DIN  
a
DIN a+1  
DIN a+2  
D
IN  
b
DIN b+1  
DIN b+2  
DIN b+3  
DON'T CARE  
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READ WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
tAH  
BA0, BA1  
DQ  
BANK  
BANK  
t
AC  
t
AC  
t
AC  
t
AC  
tHZ  
DOUT  
m
D
OUT m+1  
D
OUT m+2  
D
OUT m+3  
t
LZ  
tOH  
tOH  
t
OH  
tOH  
t
t
t
RCD  
RAS  
RC  
CAS Latency  
DON'T CARE  
UNDEFINED  
t
RP  
Notes:  
1) CAS latency = 2, Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
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READ WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
t
CL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
PRECHARGE  
ALL BANKS  
NOP  
ACTIVE  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
tAH  
ROW  
AS  
tAH  
DISABLE AUTO PRECHARGE  
SINGLE BANK  
BANK  
BA0, BA1  
DQ  
BANK  
BANK  
t
AC  
t
AC  
t
AC  
t
AC  
tHZ  
DOUT  
m
DOUT m+1  
D
OUT m+2  
DOUT m+3  
t
LZ  
tOH  
t
OH  
tOH  
tOH  
tRCD  
tRAS  
t
RC  
CAS Latency  
DON'T CARE  
UNDEFINED  
tRP  
Notes:  
1) CAS latency = 2, Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
52  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
SINGLE READ WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
ACTIVE  
NOP  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
tOH  
t
AC  
DOUT m  
DQ  
tHZ  
DON'T CARE  
UNDEFINED  
tRCD  
tRAS  
t
RC  
CAS Latency  
tRP  
Notes:  
1) CAS latency = 2, Burst Length = 1  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
53  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
SINGLE READ WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
t
CL  
tCH  
CLK  
CKE  
t
CKS CKH  
t
t
CMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
PRECHARGE  
NOP  
ACTIVE  
NOP  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
tAH  
ALL BANKS  
ROW  
SINGLE BANK  
BANK  
AS  
tAH  
DISABLE AUTO PRECHARGE  
BA0, BA1  
DQ  
BANK  
BANK  
t
OH  
t
AC  
D
OUT  
m
t
LZ  
tHZ  
DON'T CARE  
UNDEFINED  
t
t
t
RCD  
RAS  
RC  
CAS Latency  
tRP  
Notes:  
1) CAS latency = 2, Burst Length = 1  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
54  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
WRITE - WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
t
CK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
t
CMS tCMH  
DQM/DQML  
DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
BANK  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
tDS  
t
DH  
t
DS  
t
DH  
t
DS  
tDH  
t
DS  
tDH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+3  
tRCD  
tRAS  
t
RC  
tDPL  
tRP  
DON'T CARE  
Notes:  
1) Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
55  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
WRITE - WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
tCL  
tCH  
CLK  
CKE  
t
CKS CKH  
t
tCMS  
t
CMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
PRECHARGE  
NOP  
ACTIVE  
t
CMS  
t
CMH  
DQM/DQML  
DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
ROW  
ROW  
BANK  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ALL BANKS  
ROW  
AS  
tAH  
SINGLE BANK  
BANK  
DISABLE AUTO PRECHARGE  
BANK  
BA0, BA1  
BANK  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+3  
t
t
t
RCD  
RAS  
RC  
t
DPL(3)  
tRP  
DON'T CARE  
Notes:  
1) Burst Length = 4  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
3) tꢃꢌꢂ must not be violated.  
56  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
SINGLE WRITE - WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
tCK  
t
CL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
ACTIVE  
NOP  
NOP  
NOP  
WRITE  
NOP  
NOP  
NOP  
ACTIVE  
NOP  
COMMAND  
tCMS tCMH  
DQM/DQML, DQMH  
t
t
t
AS  
tAH  
A0-A9, A11  
A10  
COLUMN m(2)  
ROW  
ROW  
BANK  
ROW  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
t
AH  
BA0, BA1  
BANK  
BANK  
tDS  
t
DH  
DQ  
D
IN  
m
t
t
t
RCD  
RAS  
RC  
t
DPL  
tRP  
DON'T CARE  
Notes:  
1) Burst Length = 1  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
57  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
SINGLE WRITE - WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
PRECHARGE  
NOP  
ACTIVE  
NOP  
tCMS tCMH  
DQM/DQML  
DQMH  
tAS tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
tAS tAH  
DISABLE AUTO PRECHARGE  
ALL BANKS  
ROW  
SINGLE BANK  
tAS tAH  
BA0, BA1  
BANK  
BANK  
BANK  
tDS tDH  
DQ  
DIN m  
tRCD  
tDPL(3)  
tRP  
tRAS  
tRC  
DON'T CARE  
Notes:  
1) Burst Length = 1  
2) x16: A9 and A11 = "Don't Care"  
x8: A11 = "Don't Care"  
3) tꢃꢌꢂ must not be violated.  
58  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
ORDERING INFORMATION - Vꢀꢀ = 3.3V  
Commercial Range: 0°C to +70°C  
Frequency  
200 MHz  
166 MHz  
143 MHz  
Speed (ns) Order Part No.  
Package  
5
6
7
IS42S81600F-5TL  
IS42S81600F-6TL  
IS42S81600F-7TL  
54-Pin TSOPII, Lead-free  
54-Pin TSOPII, Lead-free  
54-Pin TSOPII, Lead-free  
Frequency  
Speed (ns) Order Part No.  
Package  
200 MHz  
5
6
7
IS42S16800F-5TL  
IS42S16800F-5BL  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
166 MHz  
143 MHz  
IS42S16800F-6TL  
IS42S16800F-6BL  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
IS42S16800F-7TL  
IS42S16800F-7BL  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
Industrial Range: -40°C to +85°C  
Frequency  
200 MHz  
166 MHz  
143 MHz  
Speed (ns) Order Part No.  
Package  
5
6
7
IS42S81600F-5TLI  
IS42S81600F-6TLI  
IS42S81600F-7TLI  
54-Pin TSOPII, Lead-free  
54-Pin TSOPII, Lead-free  
54-Pin TSOPII, Lead-free  
Frequency  
Speed (ns) Order Part No.  
Package  
200 MHz  
5
6
7
IS42S16800F-5TLI  
IS42S16800F-5BLI  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
166 MHz  
143 MHz  
IS42S16800F-6TLI  
IS42S16800F-6BLI  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
IS42S16800F-7TLI  
IS42S16800F-7BLI  
54-Pin TSOPII, Lead-free  
54-ball BGA, Lead-free  
*Contact ISSI for Leaded parts support.  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
59  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
ORDERING INFORMATION - Vꢀꢀ = 3.3V  
Automotive Range A1: -40°C to +85°C  
Frequency Speed (ns) Order Part No.  
Package  
166 MHz  
143 MHz  
6
7
IS45S81600F-6TLA1  
IS45S81600F-7TLA1  
IS45S81600F-7CTLA1  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Cu leadframe plated with matte Sn  
Frequency Speed (ns) Order Part No.  
Package  
166 MHz  
6
IS45S16800F-6TLA1  
IS45S16800F-6CTLA1  
IS45S16800F-6BLA1  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Cu leadframe plated with matte Sn  
54-ball BGA, SnAgCu balls  
143 MHz  
7
IS45S16800F-7TLA1  
IS45S16800F-7CTLA1  
IS45S16800F-7BLA1  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Cu leadframe plated with matte Sn  
54-ball BGA, SnAgCu balls  
Automotive Range A2: -40°C to +105°C  
Frequency Speed (ns) Order Part No.  
Package  
143 MHz  
7
IS45S81600F-7TLA2  
IS45S81600F-7CTLA2  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Cu leadframe plated with matte Sn  
Frequency Speed (ns) Order Part No.  
Package  
166 MHz  
143 MHz  
6
7
IS45S16800F-6TLA2  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
IS45S16800F-7TLA2  
IS45S16800F-7CTLA2  
IS45S16800F-7BLA2  
54-pin TSOPII, Alloy42 leadframe plated with matte Sn  
54-pin TSOPII, Cu leadframe plated with matte Sn  
54-ball BGA, SnAgCu balls  
Notes:  
1. Contact ISSI for Leaded and Copper lead frame parts support.  
2. Part numbers with "L" are leadfree, and RoHS compliant.  
60  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
61  
09/11/2019  
IS42/45S81600F, IS42/45S16800F  
62  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D1  
09/11/2019  

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