IS45S32400F-7BLA2-TR [ISSI]
IC DRAM 128M PARALLEL 90TFBGA;
| 型号： | IS45S32400F-7BLA2-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC DRAM 128M PARALLEL 90TFBGA 动态存储器 |
| 文件： | 总60页 (文件大小：852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S32400F
IS45S32400F
4M x 32
128Mb SYNCHRONOUS DRAM
NOVEMBER 2015
OVERVIEW
FEATURES
ISSI'sꢀ128MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Theꢀ128MbꢀSDRAMꢀisꢀorganizedꢀinꢀ1Megꢀxꢀ32ꢀbitꢀxꢀ4ꢀ
Banks.ꢀ
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143,ꢀ133ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ SingleꢀPowerꢀsupply:ꢀ3.3Vꢀ+ꢀ0.3V
•ꢀ LVTTLꢀinterface
KEY TIMING PARAMETERS
•ꢀ Programmableꢀburstꢀlengthꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
Parameter
-6
-7
-75E Unit
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
6ꢀ
10ꢀ
ꢀ
7ꢀ
10ꢀ
ꢀ
ꢀ
–ꢀ
7.5ꢀ
nsꢀ
ns
•ꢀ Programmableꢀburstꢀsequence:ꢀ
Sequential/Interleave
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
166ꢀ
100ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
143ꢀ
100ꢀ
–ꢀ
133ꢀ
Mhzꢀ
Mhz
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
–ꢀ
5.5ꢀ
ꢀ
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ16msꢀ(A2ꢀgrade)ꢀorꢀ
64ꢀmsꢀ(Commercial,ꢀIndustrial,ꢀA1ꢀgrade)
5.4ꢀ
6.5ꢀ
5.4ꢀ
6.5ꢀ
nsꢀ
ns
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
ADDRESS TABLE
Parameter
operations capability
4M x 32
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
Configuration
1Mꢀxꢀ32ꢀxꢀ4ꢀbanks
Com./Ind. 4Kꢀ/ꢀ64ms
RefreshꢀCount
OPTIONS
A1
A2
4Kꢀ/ꢀ64ms
4Kꢀ/ꢀ16ms
A0 – A11
A0 – A7
•ꢀ Package:ꢀ
86-pinꢀTSOP-IIꢀ
90-ballꢀTF-BGA
RowꢀAddresses
•ꢀ OperatingꢀTemperatureꢀRange:
Commercial (0oC to +70oC)
Column
Addresses
Industrialꢀ(-40oC to +85oC)
BankꢀAddressꢀ
Pins
BA0,ꢀBA1
AutomotiveꢀGrade,ꢀA1ꢀ(-40oC to +85oC)
AutomotiveꢀGrade,ꢀA2ꢀ(-40oC to +105oC)
Autoprecharge
Pins
A10/AP
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
1
10/28/2015
IS42S32400F, IS45S32400F
DEVICE OVERVIEW
A self-timed row precharge initiated at the end of the burst
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
enabled. Precharge one bank while accessing one of the
otherthreebankswillhidetheprechargecyclesandprovide
seamless, high-speed, random-access operation.
Theꢀ 128Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀmemoryꢀdesignedꢀtoꢀoperateꢀinꢀ3.3VꢀVdd
andꢀ3.3VꢀVddq memoryꢀsystemsꢀcontainingꢀ134,217,728ꢀ
bits.ꢀꢀInternallyꢀconfiguredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀ
synchronousꢀinterface.ꢀꢀEachꢀ33,554,432-bitꢀbankꢀisꢀorga-
nizedꢀasꢀ4,096ꢀrowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ32ꢀbits.
SDRAM readandwriteaccessesareburstorientedstarting
at a selected location and continuing for a programmed
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
command in conjunction with address bits registered are
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registered are used to select the starting column location
for the burst access.
Theꢀ128MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ
and a power-saving, power-down mode. All signals are
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.
Theꢀ128MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
data at a high data rate with automatic column-address
generation, theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1,ꢀ2,ꢀ4ꢀandꢀ8ꢀlocationsꢀorꢀfullꢀpage,ꢀwithꢀaꢀburstꢀterminateꢀ
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 1MX32X4 BANKS)
CLK
CKE
CS
RAS
CAS
WE
DQM0 - DQM3
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
4
32
32
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-31
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
32
32
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
256
(x 32)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
8
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD
DQ0
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
2
DQ15
VDDQ
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SSQ
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
VDDQ
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ10
DQ9
V
SSQ
VDDQ
DQ7
NC
DQ8
NC
VDD
VSS
DQM0
WE
DQM1
NC
NC
CAS
RAS
CS
CLK
CKE
A9
A11
BA0
BA1
A10
A0
A8
A7
A6
A5
A1
A2
A4
A3
DQM2
DQM3
VDD
VSS
NC
DQ16
NC
DQ31
V
SSQ
VDDQ
DQ17
DQ18
DQ30
DQ29
VDDQ
VSSQ
DQ19
DQ20
DQ28
DQ27
V
SSQ
VDDQ
DQ21
DQ22
DQ26
DQ25
VDDQ
VSSQ
DQ23
DQ24
VDD
VSS
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
ꢀ
WriteꢀEnable
A0-A7
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
DQM0-DQM3ꢀ
x32ꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ31ꢀ
Vdd
Vssꢀ
Vddqꢀ
Vssqꢀ
NC
ꢀ
ꢀ
ꢀ
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
No Connection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
Integrated Silicon Solution, Inc. - www.issi.comꢀ
3
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
PIN CONFIGURATION
PACKAGEꢀCODE:ꢀBꢀꢀ90ꢀBALLꢀTF-BGAꢀ(TopꢀView)ꢀ(8.00ꢀmmꢀxꢀ13.00ꢀmmꢀBody,ꢀ0.8ꢀmmꢀBallꢀPitch)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
B
C
D
E
F
G
H
J
A4
A7
A5
A8
A6
NC
A9
NC
A10
NC
A0
A1
BA1 A11
CLK CKE
DQM1 NC
BA0
CS RAS
K
L
CAS WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
M
N
P
R
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
ꢀ
WriteꢀEnable
A0-A7
Column Address Input
BankꢀSelectꢀAddress
DataꢀI/O
DQM0-DQM3ꢀ
x32ꢀInput/OutputꢀMask
Power
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ31ꢀ
Vdd
Vssꢀ
Vddqꢀ
Vssqꢀ
NC
ꢀ
ꢀ
ꢀ
Ground
CLKꢀ
CKEꢀ
CS
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
PowerꢀSupplyꢀforꢀI/OꢀPin
GroundꢀforꢀI/OꢀPin
No Connection
Chip Select
RASꢀ
CAS
ꢀ
RowꢀAddressꢀStrobeꢀCommand
Column Address Strobe Command
4ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
PIN FUNCTIONS
Symbol
A0-A11
ꢀ
Type
Input Pin
ꢀ
Function (In Detail)
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE
ꢀ
ꢀ
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(columnꢀaddressꢀ
A0-A7), with A10 defining auto precharge) to select one location out of the memory
arrayꢀinꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀcommandꢀtoꢀ
determineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀby
BA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀLOADꢀ
MODEꢀREGISTERꢀcommand.
BA0,ꢀBA1
CAS
Input Pin
Input Pin
Input Pin
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
CKEꢀ
ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refresh mode. CKEꢀisꢀan asynchronous input.
CLKꢀ
Input Pin
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
TheꢀCS input determines whether command input is enabled within the device.
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
device remains in the previous state when CSꢀisꢀHIGH.
DQM0-DQM3ꢀ
Input Pin
ꢀ
DQM0ꢀ-ꢀDQM3ꢀcontrolꢀtheꢀfourꢀbytesꢀofꢀtheꢀI/Oꢀbuffersꢀ(DQ0-DQ31).ꢀInꢀread
ꢀ
ꢀ
ꢀ
ꢀ
mode,ꢀDQMnꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀDQMnꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbuf-
ferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀimped-
anceꢀstateꢀwhenDQMnꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀtoꢀOE in conventional
DRAMs.ꢀInꢀwriteꢀmode,ꢀDQMnꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀDQMnꢀisꢀLOW,ꢀtheꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀ
DQMnꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀmaskedꢀandꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀdevice.
DQ0-DQ31ꢀ
RAS
Input/OutputꢀPin
Input Pin
DataꢀonꢀtheꢀDataꢀBusꢀisꢀlatchedꢀonꢀtheseꢀpinsꢀduringꢀWriteꢀcommands,ꢀandꢀbufferedꢀafterꢀ
Readꢀcommands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddq
Vdd
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
ꢀ
ꢀ
ꢀ
ꢀ
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vssq
Vss
Vss is the device internal ground.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
5
10/28/2015
IS42S32400F, IS45S32400F
GENERAL DESCRIPTION
READ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
and starts a burst read access to an active row. Inputs
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀꢀWhenꢀA10ꢀisꢀ
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ
command.ꢀꢀWhenꢀtheꢀautoꢀprechargeꢀisꢀselected,ꢀtheꢀrowꢀ
beingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀtheꢀREADꢀ
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ
dataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀtheꢀDQMꢀinputsꢀtwoꢀ
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ
wasꢀregisteredꢀLOW.
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ
command, auto precharge is either enabled or disabled.
AUTOꢀPRECHARGEꢀdoesꢀnotꢀapplyꢀexceptꢀinꢀfull-pageꢀ
burstꢀ mode.ꢀ Uponꢀ completionꢀ ofꢀ theꢀ READꢀ orꢀWRITEꢀ
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(trc)is
required for a single refresh operation, and no other com-
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀ
isꢀexecutedꢀatꢀleastꢀ4096ꢀtimesꢀforꢀeveryꢀTref.ꢀDuringꢀanꢀ
AUTOꢀREFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀ
ThisꢀcommandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.
WRITE
A burst write access to an active row is initiated with the
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ
and the starting column location is provided by inputs
A0-A7.ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀusedꢀisꢀ
determined by A10.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
open for subsequent accesses.
A memory array is written with corresponding input data
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/column location.
COMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
NO OPERATION
WhenꢀCSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commands from being registered during idle or wait
states.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
open row in a particular bank or the open row in all banks.
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bank(s) is executed after passage of the period tRP, which
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
has been precharged, it is in the idle state and must be
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issued to that bank.
LOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
be issued when all banks are idle.
ACTIVE COMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputs selects a bank to be accessed, and the address
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
command is issued to the bank, the row remains open
for accesses.
AUTO PRECHARGE
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-
charge is initiated at the earliest valid stage within a burst.
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ
requiringꢀanꢀexplicitꢀcommand.ꢀA10ꢀtoꢀenableꢀtheꢀAUTOꢀ
6ꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
COMMAND TRUTH TABLE
CKE
A11
Function
n – 1
Hꢀꢀ
n
CS
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
RAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
CAS
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
WE
×ꢀꢀ
Hꢀ
BA1
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
BA0
×ꢀꢀ
×ꢀ
A10 A9 - A0
Deviceꢀdeselectꢀ(DESL)ꢀꢀ
Noꢀoperationꢀ(NOP)ꢀ ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀ
×
Hꢀꢀ
×
Burstꢀstopꢀ(BST)ꢀꢀ
Readꢀꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
Vꢀꢀ
Vꢀꢀ
Vꢀ
×ꢀꢀ
Lꢀꢀ
Hꢀ
Lꢀ
×
ꢀ
Hꢀꢀ
Vꢀ
Vꢀ
V
V
V
×
Readꢀwithꢀautoꢀprechargeꢀꢀ Hꢀꢀ
Writeꢀꢀ ꢀꢀ Hꢀꢀ
Writeꢀwithꢀautoꢀprechargeꢀꢀ Hꢀ
Bankꢀactivateꢀ(ACT)ꢀꢀꢀ Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀꢀ
Lꢀ
Hꢀ
Vꢀ
Hꢀꢀ
Vꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀ
×ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀ
ꢀVꢀꢀ
Vꢀ
Prechargeꢀselectꢀbankꢀ(PRE)ꢀ Hꢀꢀ
Prechargeꢀallꢀbanksꢀ(PALL)ꢀ Hꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Vꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀ
×
CBRꢀAuto-Refreshꢀ(REF)ꢀ
Self-Refreshꢀ(SELF)ꢀ ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×
Lꢀ
Lꢀ
Lꢀ
Hꢀ
×ꢀ
×ꢀ
×
Modeꢀregisterꢀsetꢀ(MRS)ꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Vꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
DQM TRUTH TABLE
CKE
DQM
Function
n-1
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
n
U
L
L
Dataꢀwriteꢀ/ꢀoutputꢀenableꢀꢀꢀ
Dataꢀmaskꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
ꢀ×ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
H
×
L
Upperꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Lowerꢀbyteꢀwriteꢀenableꢀ/ꢀoutputꢀenableꢀꢀꢀꢀ ꢀ
Upperꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
×
H
Lowerꢀbyteꢀwriteꢀinhibitꢀ/ꢀoutputꢀdisableꢀꢀꢀꢀ ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
7
10/28/2015
IS42S32400F, IS45S32400F
CKE TRUTH TABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CKE
CurrentꢀStateꢀ/Functionꢀꢀ
ActivatingꢀClockꢀsuspendꢀmodeꢀentryꢀꢀ
AnyꢀClockꢀsuspendꢀmodeꢀꢀ
Clockꢀsuspendꢀmodeꢀexitꢀꢀ
AutoꢀrefreshꢀcommandꢀIdleꢀ(REF)ꢀꢀ
SelfꢀrefreshꢀentryꢀIdleꢀ(SELF)ꢀꢀ
PowerꢀdownꢀentryꢀIdleꢀꢀ
nꢀ–ꢀ1ꢀꢀ nꢀꢀ
CS
×ꢀ
RAS
×ꢀꢀ
×ꢀꢀ
×ꢀ
CAS WE
Address
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀꢀ
Hꢀ
×
×
×
×
×
×ꢀꢀ
×ꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀ
×ꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Lꢀꢀ
×ꢀ
ꢀ
Selfꢀrefreshꢀexitꢀꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×
ꢀ
ꢀ
Powerꢀdownꢀexitꢀ
ꢀ
Lꢀꢀ
Hꢀꢀ
×ꢀꢀ
×ꢀ
×ꢀꢀ
×ꢀꢀ
×ꢀ
ꢀ
Note:ꢀꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData.
8
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
FUNCTIONAL TRUTH TABLE
Current State
CS
RAS CAS WE
Address
Xꢀ
Command
DESLꢀꢀ
Action
Idleꢀ
Hꢀꢀ Xꢀ
Xꢀ
Xꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown(2)
NopꢀorꢀPowerꢀDown
ILLEGALꢀ(3)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
Xꢀ
NOPꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Xꢀ
BSTꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
A,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGAL(3)
Rowꢀactivating
Nop
AutoꢀrefreshꢀorꢀSelf-refresh(4)
Modeꢀregisterꢀset
Nop
Lꢀꢀ
Lꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
OC,ꢀBA1=Lꢀꢀ
Xꢀ
RowꢀActiveꢀ
Hꢀꢀ Xꢀ
Xꢀ
DESLꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Xꢀ
NOPꢀꢀ
Nop
Hꢀꢀ
Hꢀ
Xꢀ
BSTꢀ
Nop
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀreadꢀ(5)
Beginꢀwriteꢀ(5)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Lꢀ
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
Precharge
Precharge all banks(6)ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
OC,ꢀBAꢀꢀ
Readꢀ
ꢀ
Hꢀꢀ Xꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀtoꢀꢀ
Rowꢀactive
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
ContinueꢀburstꢀtoꢀendꢀꢀRowꢀꢀ
Rowꢀꢀactive
ꢀ
ꢀ
Lꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
Hꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/READAꢀꢀ
Terminateꢀburst,ꢀꢀ ꢀ
ꢀ
ꢀ
begin new read (7)
ꢀ
Lꢀ
Hꢀꢀ
Lꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
WRIT/WRITAꢀꢀ
ꢀ
Terminateꢀꢀburst,ꢀꢀꢀ
begin write (7,8)
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀ
BA,ꢀRAꢀꢀ
ACTꢀꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
Lꢀꢀ
BA,ꢀA10ꢀꢀ
PRE/PALLꢀꢀ
Terminateꢀburstꢀꢀꢀ ꢀ
ꢀ
Precharging
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Lꢀꢀ
Xꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ILLEGAL
ILLEGAL
OC,ꢀBAꢀꢀ
Writeꢀ
ꢀ
Hꢀ
ꢀꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
Xꢀ
ꢀ
DESLꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
ꢀ
Hꢀꢀ
ꢀ
Hꢀ
ꢀ
Hꢀꢀ
ꢀ
Xꢀ
ꢀ
NOPꢀꢀ
ꢀ
ꢀ
ꢀ
Continueꢀburstꢀtoꢀendꢀꢀꢀ
Writeꢀrecovering
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Xꢀ
BSTꢀꢀ
ꢀ
Burstꢀstop,ꢀꢀRowꢀactive
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
READ/READAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀstartꢀreadꢀ:ꢀꢀ
DetermineꢀAPꢀ(7,8)
ꢀ
ꢀ
Lꢀ
ꢀ
Hꢀꢀ
ꢀ
Lꢀ
ꢀ
Lꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
ꢀ
WRIT/WRITAꢀꢀ
ꢀ
ꢀ
ꢀ
Terminateꢀburst,ꢀnewꢀwriteꢀ:ꢀꢀ
DetermineꢀAPꢀ(7)
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
BA,ꢀRAꢀ
BA,ꢀA10ꢀꢀ
Xꢀ
RAꢀACTꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ILLEGALꢀ(3)
TerminateꢀburstꢀPrechargingꢀ(9)
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
ILLEGAL
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Integrated Silicon Solution, Inc. - www.issi.comꢀ
9
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
RAS CAS
WE
Address
Command
Action
Readꢀwithꢀautoꢀ
Hꢀ
ꢀ×ꢀꢀ
×ꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
DESLꢀ
Continueꢀburstꢀtoꢀend,ꢀPrechargeꢀꢀ
Precharging
ꢀ
ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Hꢀ
xꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀPrecharge
ILLEGAL
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(11)
ꢀ
ꢀ
ꢀ
ꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3)
ILLEGALꢀ(11)
ILLEGAL
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀwithꢀAutoꢀ
ꢀ×ꢀꢀ
DESLꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
Precharge
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
×ꢀꢀ
NOPꢀꢀ
BSTꢀꢀ
Continueꢀburstꢀtoꢀend,ꢀWriteꢀꢀ ꢀ
recovering with auto precharge
ꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(11)
ꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀ
ILLEGALꢀ(11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Prechargingꢀ
Hꢀꢀ ×ꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
Nop,ꢀEnterꢀidleꢀafterꢀtRP
ꢀ
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
ꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGAL(3)
ꢀ
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
NopꢀꢀEnterꢀidleꢀafterꢀtRP
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
ꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
RowꢀActivatingꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
Nop,ꢀEnterꢀbankꢀactiveꢀafterꢀtRCD
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
×ꢀꢀ
NOPꢀꢀ
×ꢀꢀ
BSTꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGALꢀ(3)
Lꢀ
Hꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3)
ILLEGALꢀ(3,9)
ILLEGALꢀ(3)
ILLEGAL
Lꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
Lꢀ
Lꢀ
OC,ꢀBAꢀꢀ
ILLEGAL
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
10
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
Hꢀ
Lꢀꢀ
Lꢀ
RAS CAS
WE
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
Address
×ꢀꢀ
Command
DESLꢀꢀ
NOPꢀꢀ
Action
WriteꢀRecoveringꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀ
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
ꢀ
×ꢀꢀ
ꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀCA,ꢀA10ꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ Beginꢀread (8)
ꢀ
Lꢀꢀ
Lꢀ
Lꢀ
WRIT/ꢀWRITAꢀꢀ
ACTꢀꢀ
Beginꢀnewꢀwrite
ILLEGALꢀ(3)
ILLEGALꢀ(3)
ꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀꢀ
Lꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
WriteꢀRecoveringꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀꢀ
×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
Lꢀꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀprechargeꢀafterꢀtDPL
Nop,ꢀEnterꢀrowꢀactiveꢀafterꢀtDPL
withꢀAutoꢀ
×ꢀꢀ
NOPꢀꢀ
Prechargeꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
ꢀ×ꢀꢀ
READ/READAꢀꢀ ILLEGAL(3,8,11)
ꢀ
Lꢀꢀ
Hꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ILLEGALꢀ(3,11)
ꢀ
ꢀ
Lꢀ
Lꢀꢀ
Hꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Lꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
×ꢀꢀ
ILLEGAL
Refreshꢀ
Hꢀꢀ ×ꢀꢀ
×ꢀ
DESLꢀꢀꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀtRC
Nop,ꢀEnterꢀidleꢀafterꢀtRC
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
NOP/BSTꢀ
ꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
BA,ꢀRAꢀꢀ
BA,ꢀA10ꢀꢀ
×ꢀꢀ
READ/READAꢀꢀ ILLEGAL
ꢀ
Lꢀ
WRIT/WRITAꢀꢀ
ACTꢀꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Lꢀꢀ
Lꢀ
Lꢀꢀ
Lꢀ
Hꢀꢀ
Hꢀ
Lꢀꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀꢀ
Hꢀꢀ
Lꢀꢀ
×ꢀ
PRE/PALLꢀꢀ
REF/SELFꢀꢀ
MRSꢀꢀ
ILLEGAL
ꢀ
Lꢀ
ILLEGAL
ꢀ
Lꢀ
Lꢀꢀ
ꢀ×ꢀ
Hꢀꢀ
Hꢀꢀ
Hꢀ
OC,ꢀBAꢀꢀ
ꢀ×ꢀꢀ
ILLEGAL
ModeꢀRegisterꢀ
Accessingꢀ
Hꢀ
Lꢀ
ꢀ×ꢀꢀ
Hꢀ
Hꢀ
Lꢀꢀ
DESLꢀꢀ
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
Nop,ꢀEnterꢀidleꢀafterꢀ2ꢀclocks
ILLEGAL
Hꢀꢀ
Lꢀꢀ
×ꢀꢀꢀ
×ꢀꢀ
NOPꢀ
Lꢀ
×ꢀꢀ
BSTꢀꢀ
ꢀ
Lꢀꢀ
BA,ꢀCA,ꢀA10ꢀꢀ
READ/WRITEꢀꢀ ILLEGAL
ꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
×ꢀꢀꢀ
ꢀ
×ꢀꢀ
ꢀ
BA,ꢀRAꢀꢀ
ꢀ
ACT/PRE/PALLꢀꢀ ILLEGALꢀ
REF/MRSꢀ
ꢀ
ꢀ
ꢀ
Note:ꢀH=Vih,ꢀL=Vilꢀx=ꢀVihꢀorꢀVil,ꢀVꢀ=ꢀValidꢀData,ꢀBA=ꢀBankꢀAddress,ꢀCA+ColumnꢀAddress,ꢀRA=RowꢀAddress,ꢀOC=ꢀOp-Code
Notes:
1.ꢀAllꢀentriesꢀassumeꢀthatꢀCKEꢀisꢀactiveꢀ(CKEn-1=CKEn=H).
2.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀPowerꢀDownꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
3.ꢀIllegalꢀtoꢀbankꢀinꢀspecifiedꢀstates;ꢀFunctionꢀmayꢀbeꢀlegalꢀinꢀtheꢀbankꢀindicatedꢀbyꢀBankꢀAddressꢀ(BA),ꢀdependingꢀonꢀtheꢀstateꢀofꢀ
that bank.
4.ꢀIfꢀbothꢀbanksꢀareꢀidle,ꢀandꢀCKEꢀisꢀinactiveꢀ(Low),ꢀtheꢀdeviceꢀwillꢀenterꢀSelf-Refreshꢀmode.ꢀAllꢀinputꢀbuffersꢀexceptꢀCKEꢀwillꢀbeꢀ
disabled.
5.ꢀIllegalꢀifꢀtRCDꢀisꢀnotꢀsatisfied.
6.ꢀIllegalꢀifꢀtRASꢀisꢀnotꢀsatisfied.
7.ꢀMustꢀsatisfyꢀburstꢀinterruptꢀcondition.
8.ꢀMustꢀsatisfyꢀbusꢀcontention,ꢀbusꢀturnꢀaround,ꢀand/orꢀwriteꢀrecoveryꢀrequirements.
9.ꢀMustꢀmaskꢀprecedingꢀdataꢀwhichꢀdon’tꢀsatisfyꢀtDPL.
10.ꢀIllegalꢀifꢀtRRDꢀisꢀnotꢀsatisfied.
11. Illegal for single bank, but legal for other banks.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
11
10/28/2015
IS42S32400F, IS45S32400F
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
Current State
Operation
n-1
n
CS
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
RAS
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
CAS
Xꢀ
Xꢀ
Hꢀ
Lꢀ
WE Address
Self-Refreshꢀ(S.R.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀS.R.ꢀ
Self-RefreshꢀRecovery(2)
Self-RefreshꢀRecovery(2)
Illegalꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
—
—
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
Lꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
MaintainꢀS.R.ꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Self-RefreshꢀRecoveryꢀIdleꢀAfterꢀꢀtrc
ꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Idle After trc
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Illegalꢀ
Illegalꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)
Beginꢀclockꢀsuspendꢀnextꢀcycle(5)
Illegalꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Illegalꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Exit clock suspend next cycle(2)
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
Maintainꢀclockꢀsuspendꢀ
Lꢀ
Power-Downꢀ(P.D.)ꢀ
INVALID,ꢀCLKꢀ(nꢀ-ꢀ1)ꢀwouldꢀexitꢀP.D.ꢀ
EXITꢀP.D.ꢀ-->ꢀIdle(2)
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
Maintainꢀpowerꢀdownꢀmodeꢀ
Lꢀ
BothꢀBanksꢀIdleꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Auto-Refreshꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
ꢀ
ꢀ
ꢀ
Lꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Self-Refresh(3)ꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
—
—
—
X
ꢀ
Lꢀ
ꢀ
Lꢀ
ꢀ
Lꢀ
Lꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Power-Down(3)ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ Opꢀ-ꢀCode
ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
X
X
X
X
Anyꢀstateꢀ
otherꢀthanꢀ
listedꢀaboveꢀ
ꢀ
ReferꢀtoꢀoperationsꢀinꢀOperativeꢀCommandꢀTableꢀ
Beginꢀclockꢀsuspendꢀnextꢀcycle(4)ꢀ
Exitꢀclockꢀsuspendꢀnextꢀcycleꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Maintainꢀclockꢀsuspendꢀ
Lꢀ
Notes:
1.ꢀHꢀ:ꢀHighꢀlevel,ꢀLꢀ:ꢀlowꢀlevel,ꢀXꢀ:ꢀHighꢀorꢀlowꢀlevelꢀ(Don’tꢀcare).
2.ꢀCKEꢀLowꢀtoꢀHighꢀtransitionꢀwillꢀre-enableꢀCLKꢀandꢀotherꢀinputsꢀasynchronously.ꢀAꢀminimumꢀsetupꢀ
time must be satisfied
beforeꢀanyꢀcommandꢀotherꢀthanꢀEXIT.
ꢀ
3.ꢀPowerꢀdownꢀandꢀSelfꢀrefreshꢀcanꢀbeꢀenteredꢀonlyꢀfromꢀtheꢀbothꢀbanksꢀidleꢀstate.
4.ꢀMustꢀbeꢀlegalꢀcommandꢀasꢀdefinedꢀinꢀOperativeꢀCommandꢀTable.
5. Illegal if txsr is not satisfied.
12
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
STATE DIAGRAM
Self
Refresh
SELF
SELF exit
REF
Mode
Register
Set
MRS
CBR (Auto)
Refresh
IDLE
CKE
CKE
ACT
Power
Down
CKE
Active
Power
Down
Row
Active
CKE
BST
Write
BST
Read
Auto Prech
Write
Read
arge
Read
CKE
CKE
CKE
WRITE
SUSPEND
READ
SUSPEND
READ
WRITE
Write
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual Input
Integrated Silicon Solution, Inc. - www.issi.comꢀ
13
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vdd maxꢀ
Vddq max
Vinꢀ
Parameters
Rating
-0.5ꢀtoꢀ+4.6ꢀ
-0.5ꢀtoꢀ+4.6ꢀ
-0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
-1.0ꢀtoꢀVddqꢀ+ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
W
mA
°C
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
output Shorted Current
operatingꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Voutꢀ
Pd max
Ics
50
ꢀ
Topr
Com.
Ind.ꢀ
A1ꢀ
A2ꢀ
ꢀ
0 to +70
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+105
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
-65ꢀtoꢀ+150ꢀ
°C
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
DC RECOMMENDED OPERATING CONDITIONS
(Taꢀ=ꢀ0oC to +70oCꢀforꢀCom.ꢀgrade.ꢀTaꢀ=ꢀ-40oC to +85oCꢀforꢀInd.ꢀandꢀA1ꢀgrade.ꢀꢀTaꢀ=ꢀ-40oC to +105oC for A2 grade.)
Symbol
Vdd ꢀ
Parameter
Min.
3.0ꢀ
3.0ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
3.3ꢀ
3.3ꢀ
—ꢀ
Max.
3.6ꢀ
3.6ꢀ
Unit
V
V
V
V
ꢀ
SupplyꢀVoltageꢀ
I/OꢀSupplyꢀVoltageꢀ
InputꢀHighꢀVoltageꢀ
InputꢀLowꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀ
(1)
ꢀ
ꢀ
Vih ꢀ
Vddq +ꢀ0.3ꢀ
+0.8ꢀ
(2)
Vil ꢀ
—ꢀ
Note:
1.ꢀꢀVih (max)ꢀ=ꢀVddq +1.2V (pulse width < 3ns).
2.ꢀꢀVilꢀ(min)ꢀꢀ=ꢀ-1.2V (pulse width < 3ns).
3.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀVss.
CAPACITANCE CHARACTERISTICS (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVddꢀ=ꢀVddq =ꢀ3.3ꢀ±ꢀ0.3V)
Symbol
Cin1ꢀ
Parameter
Min. Max.
2ꢀ 4ꢀ
1.3ꢀ ꢀ 3ꢀ
Unit
pF
pF
InputꢀCapacitance:ꢀCLKꢀ
InputꢀCapacitance:Allꢀotherꢀinputꢀpinsꢀ
DataꢀInput/OutputꢀCapacitance:I/Osꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cin2ꢀ
Ci/oꢀ
2ꢀ
ꢀ
5ꢀ
pF
THERMAL RESISTANCE
Package
Substrate
Theta-ja
Theta-ja
Theta-ja
Theta-jc
Units
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)
TSOP2(86)
BGA(90)
4-layer
4-layer
88.1
38.1
77.3
33.1
72.3
31.3
15.3
5.7
C/W
C/W
14
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
DC ELECTRICAL CHARACTERISTICS 1 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
-6
-7
-75E
Unit
i
dd1 (1)
ꢀ
OperatingꢀCurrentꢀ
Oneꢀbankꢀactive,ꢀCLꢀ=ꢀ3,ꢀBLꢀ=ꢀ1,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
120ꢀ
100ꢀ
120ꢀ
ꢀ
ꢀ
mA
tclkꢀ=ꢀtclk (min), trcꢀ=ꢀtrc (min)
i
i
i
dd2p
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(InꢀPower-DownꢀMode)
(max), tckꢀ=ꢀ15nsꢀ
ꢀ
2ꢀ
2
2ꢀ
2
2ꢀ
2
mA
mA
mA
dd2ps
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil
(InꢀPower-DownꢀMode)
(max),ꢀCLKꢀ≤ Vil
(
max
)
(2)
dd2n
Precharge Standby Current
(InꢀNonꢀPower-DownꢀMode)
Precharge Standby Current
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
min
)
25
25
25
t
I
i
I
I
dd2ns
(min) or
15
40ꢀ
25
15
40ꢀ
25
15
40ꢀ
25
mA
mA
mA
mA
mA
mA
(InꢀNonꢀPower-DownꢀMode) CKEꢀ≤ Vil (max), All inputs stable
(2)
dd3n
Active Standby Current
(InꢀNonꢀPower-DownꢀMode)
Active Standby Current
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
ckꢀ=ꢀ15ns
CS ≥ Vddꢀ-ꢀ0.2V,ꢀCKEꢀ≥ Vih
(
min)ꢀ
ꢀ
t
dd3ns
(min) or
(InꢀNonꢀPower-DownꢀMode) CKEꢀ≤ Vil
(max), All inputs stable
dd3p
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(Power-DownꢀMode)
ActiveꢀStandbyꢀCurrentꢀ
(Power-DownꢀMode)
OperatingꢀCurrentꢀ
CKEꢀ≤ Vil
(max), tckꢀ=ꢀ15nsꢀ
ꢀ
6ꢀ
6ꢀ
6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Idd3ps
ꢀ
CKEꢀ≤ Vil
(max),ꢀCLKꢀ≤ Vil
(max)ꢀ
6ꢀ
6ꢀ
6ꢀ
i
dd4
ꢀ
Allꢀꢀbanksꢀactive,ꢀBLꢀ=ꢀ4,ꢀCLꢀ=ꢀ3,ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
150ꢀ
100ꢀ
150ꢀ
tckꢀ=ꢀtck (min)
i
i
dd5
dd6
ꢀ
ꢀ
Auto-RefreshꢀCurrentꢀ
Self-RefreshꢀCurrentꢀ
trcꢀ=ꢀtrc (min), tclkꢀ=ꢀtclkꢀ(min)ꢀꢀꢀꢀꢀꢀꢀꢀ
150ꢀ
130ꢀ
150ꢀ
mA
CKEꢀ≤ 0.2V
2
2
2
mA
Notes:
1. Idd (max) is specified at the output open condition.
2.ꢀ Inputꢀsignalsꢀareꢀchangedꢀoneꢀtimeꢀduringꢀ30ns.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbol Parameter
Test Condition
Min
Max
Unit
i
ꢀꢀ
i
il
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀꢀ≤ꢀVinꢀ≤ꢀVdd, with pins other than
-10
10
µA
theꢀtestedꢀpinꢀatꢀ0Vꢀ
ꢀ
ol
oh
ol
ꢀ
OutputꢀLeakageꢀCurrentꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀꢀ≤ꢀVoutꢀ≤ꢀVdd
,
-10
2.4ꢀ
—
10
—
µA
V
V
ꢀ
I
ohꢀꢀ=ꢀꢀ-2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
olꢀꢀ=ꢀꢀ2mAꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
ꢀ
I
0.4
V
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
15
10/28/2015
IS42S32400F, IS45S32400F
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-6
-7
-75E
Min.
Symbol Parameter
Min.
Max.
Min.
Max.
Max.
Units
tck3ꢀ
tck2ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
6ꢀ
10ꢀ
—ꢀ
—ꢀ
7ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
7.5ꢀ
—ꢀ
—ꢀ
ns
ns
tac3ꢀ
tac2ꢀ
AccessꢀTimeꢀFromꢀCLKꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6.5ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6.5ꢀ
—ꢀ
—ꢀ
—ꢀ
5.5ꢀ
ns
ns
tchꢀ
tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTimeꢀ
ꢀ
ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
ns
ns
toh3ꢀ
toh2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
ns
ns
tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
ns
thz3ꢀ
thz2ꢀ
OutputꢀHIGHꢀImpedanceꢀTimeꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
2.5ꢀ
2.5ꢀ
5.4ꢀ
6.5ꢀ
2.5ꢀ
2.5ꢀ
5.4ꢀ
6.5ꢀ
—ꢀ
2.5ꢀ
—ꢀ
5.5ꢀ
nsꢀ
ns
ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
tdsꢀ
InputꢀDataꢀSetupꢀTime(2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
60ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
65ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
67.5ꢀ
45ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdhꢀ
InputꢀDataꢀHoldꢀTime(2)
AddressꢀSetupꢀTime(2)
AddressꢀHoldꢀTime(2)
CKEꢀSetupꢀTime(2)
CKEꢀHoldꢀTime(2)
ꢀ
tasꢀ
ꢀ
—ꢀ
tahꢀ
ꢀ
—ꢀ
tcksꢀ
tckhꢀ
tcmsꢀ
tcmhꢀ
trcꢀ
ꢀ
—ꢀ
ꢀ
—ꢀ
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)(2)
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)(2)
ꢀ
—ꢀ
ꢀ
—ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
trasꢀ
trpꢀ
42ꢀ
100K
—ꢀ
ꢀ
42ꢀ
100K
ꢀ
100Kꢀ
—ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
18ꢀ
20ꢀ
—ꢀ
15ꢀ
trcdꢀ
trrdꢀ
tdplꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
18ꢀ
—ꢀ
20ꢀ
—ꢀ
15ꢀ
—ꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
ꢀ
ꢀ
12ꢀ
—ꢀ
14ꢀ
—ꢀ
15ꢀ
—ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
12ꢀ
—ꢀ
14ꢀ
—ꢀ
15ꢀ
—ꢀ
ꢀ ꢀ ꢀ
tdalꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
ꢀ
30
—ꢀ
35
—ꢀ
30ꢀ
—ꢀ
ns
ꢀ ꢀ ꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)
tmrd
tdde
txsr
ttꢀ
ModeꢀRegisterꢀProgramꢀTimeꢀ
PowerꢀDownꢀExitꢀSetupꢀTimeꢀ
ExitꢀSelf-RefreshꢀtoꢀActiveꢀTimeꢀ(4)
ꢀ
12ꢀ
6ꢀ
—ꢀ
—ꢀ
14ꢀ
7ꢀ
—ꢀ
—ꢀ
15ꢀ
7.5ꢀ
70ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
70ꢀ
0.3ꢀ
—ꢀ
70ꢀ
0.3ꢀ
—ꢀ
—ꢀ
TransitionꢀTimeꢀ
ꢀ
1.2ꢀ
1.2ꢀ
0.3ꢀ
1.2ꢀ
trefꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ta ≤ 70oCꢀꢀCom.,ꢀInd.,ꢀA1,ꢀA2ꢀ
Ta ≤ 85oCꢀꢀInd.,ꢀA1,ꢀA2ꢀ
Ta > 85oCꢀꢀA2ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
16ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
16ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
—ꢀ
msꢀ
msꢀ
ms
Notes:
1.ꢀ Theꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2. measured with tt =ꢀ1ꢀns.ꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀ(tr /2 - 0.5) ns should be added to the parameter.
3.ꢀꢀTheꢀreferenceꢀlevelꢀisꢀ1.4Vꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih(min.)ꢀandꢀVil
(max).
4.ꢀꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ85oC.
16
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-6
-7
-75E UNITS
—ꢀ
ClockꢀCycleꢀTimeꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
6ꢀ
10ꢀ
7ꢀ
10ꢀ
—ꢀ
7.5ꢀ
nsꢀ ꢀ
ns
ꢀ—ꢀ
OperatingꢀFrequencyꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
166ꢀ
100ꢀ
143ꢀ
100ꢀ
—ꢀ
MHzꢀ
MHz
133ꢀ
trcdꢀ
trac
trc
ActiveꢀCommandꢀToꢀRead/WriteꢀCommandꢀDelayꢀTimeꢀ
RASꢀLatencyꢀ(trcd + tcac)
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
—ꢀ
2ꢀ
cycleꢀ
cycle
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
6ꢀ
4ꢀ
6ꢀ
4ꢀ
—ꢀ
4
cycleꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
10ꢀ
6ꢀ
10ꢀ
7ꢀ
—ꢀ
9ꢀ
cycleꢀ
cycle
trasꢀ
trpꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
7ꢀ
5ꢀ
6ꢀ
5ꢀ
—ꢀ
6ꢀ
cycleꢀ
cycle
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
—ꢀ
2ꢀ
cycleꢀ
cycle
trrdꢀ
CommandꢀPeriodꢀ(ACT[0]ꢀtoꢀACTꢀ[1])ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
2ꢀ
1ꢀ
cycle
cycle
tccdꢀ
ꢀꢀ
ColumnꢀCommandꢀDelayꢀTimeꢀ
(READ,ꢀREADA,ꢀWRIT,ꢀWRITA)
tdplꢀ
InputꢀDataꢀToꢀPrechargeꢀCommandꢀDelayꢀTimeꢀ
ꢀ
2ꢀ
2ꢀ
2ꢀ
cycle
tdalꢀ
ꢀꢀ
InputꢀDataꢀToꢀActive/RefreshꢀCommandꢀDelayꢀTimeꢀ
(DuringꢀAuto-Precharge)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
5ꢀ
4ꢀ
5ꢀ
4ꢀ
—ꢀ
4ꢀ
cycle
cycle
trbd
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime
(Read)ꢀ
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
cycle
cycle
twbdꢀ
ꢀꢀ
BurstꢀStopꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
cycle
cycle
cycle
trql
ꢀꢀ
PrechargeꢀCommandꢀToꢀOutputꢀinꢀHIGH-ZꢀDelayꢀTime
(Read)
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
3ꢀ
2
twdlꢀ
ꢀꢀ
PrechargeꢀCommandꢀToꢀInputꢀinꢀInvalidꢀDelayꢀTimeꢀ
(Write)
ꢀ
0ꢀ
0ꢀ
0ꢀ
tpql
LastꢀOutputꢀToꢀAuto-PrechargeꢀStartꢀTimeꢀ(Read)
CASꢀꢀLatencyꢀ=ꢀ3ꢀ
CASꢀꢀLatencyꢀ=ꢀ2ꢀ
-2ꢀ
-1ꢀ
-2ꢀ
-1ꢀ
-2ꢀ
-1ꢀ
cycleꢀ
cycle
tqmdꢀ
tdmdꢀ
tmrdꢀ
DQMꢀToꢀOutputꢀDelayꢀTimeꢀ(Read)ꢀ
DQMꢀToꢀInputꢀDelayꢀTimeꢀ(Write)ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
2ꢀ
0ꢀ
2ꢀ
cycle
cycle
cycle
ModeꢀRegisterꢀSetꢀToꢀCommandꢀDelayꢀTimeꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
17
10/28/2015
IS42S32400F, IS45S32400F
AC TEST CONDITIONS
Input Load
Output Load
t
CK
t
CH
tCL
3.0V
1.4V
1.4V
CLK
50Ω
0V
Z = 50Ω
tCMS
tCMH
Output
3.0V
1.4V
50 pF
INPUT
0V
tAC
t
OH
OUTPUT
1.4V
1.4V
AC TEST CONDITIONS
Parameter
Rating
ACꢀInputꢀLevelsꢀ
0Vꢀtoꢀ3.0V
1ꢀns
ꢀ
ꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
InputꢀTimingꢀReferenceꢀLevelꢀ
OutputꢀTimingꢀMeasurementꢀReferenceꢀLevelꢀ
1.4V
1.4V
18
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
TIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorWRITEꢀ
IS42S32400F, IS45S32400F
Initialization
FUNCTIONAL DESCRIPTION
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ
predefined manner.
Theꢀ128MbꢀSDRAMsꢀareꢀquad-bankꢀDRAMsꢀwhichꢀoperateꢀ
atꢀ3.3Vꢀandꢀincludeꢀaꢀsynchronousꢀinterfaceꢀ(allꢀsignalsꢀareꢀ
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK).ꢀ
Eachꢀofꢀtheꢀ33,554,432-bitꢀbanksꢀisꢀorganizedꢀasꢀ4,096ꢀ
rowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ32ꢀbits.
Theꢀ128MꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVddꢀandꢀVddq (simultaneously) and the clock is stable
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
A 100µs delay is required prior to issuing any command
other than a COMMANDꢀINHIBIT or a NOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100µsꢀperiodꢀandꢀ
should continue at least through the end of the period.
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
be applied once the 100µs delay has been satisfied. All
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀanꢀ
idle state after which at least two AUTOꢀREFRESH cycles
must be performed. After the AUTOꢀREFRESH cycles are
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ
programming.
command.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀ
ACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀ
be accessed (BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-A11ꢀselectꢀtheꢀ
row).ꢀTheꢀaddressꢀbitsꢀA0-A7 registered coincident with the
READꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀ
column location for the burst access.
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
covering device initialization, register definition, command
descriptions and device operation.
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
any operational command because it will power up in an
unknown state.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
19
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
INITIALIꢀE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
To+1
t
CL
Tp+1
Tp+2
Tp+3
t
CK
tCH
CLK
CKE
tCKS t
CKH
t
CMS
tCMH
tCMS
tCMH
tCMS tCMH
AUTO
REFRESH
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
DQM0-DQM3
t
t
t
AS
tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
AS
tAH
ALL BANKS
CODE
SINGLE BANK
ALL BANKS
AS
tAH
BA0, BA1
DQ
CODE
t
RP
t
RC
t
RC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
DON'T CARE
T = 100µs Min.
Notes:
1. If CSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3.ꢀꢀJEDECꢀandꢀPC100ꢀspecifyꢀthreeꢀclocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
20
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM0 - DQM3
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
t
RP
tRC
tRC
DON'T CARE
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
21
10/28/2015
IS42S32400F, IS45S32400F
SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
tCK
tCH
tCL
CLK
CKE
tCKS tCKH
tCKS
≥ tRAS
tCKS
tCMS tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM0 - DQM3
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
tAS tAH
BA0, BA1
DQ
BANK
High-Z
t
RP
tXSR
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1.ꢀꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ85oC.
22
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
initiatingꢀtheꢀsubsequentꢀoperation.
Violatingꢀeitherꢀofꢀtheseꢀ
IS42S32400F, IS45S32400F
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀ
ModeꢀregisterꢀbitsꢀM0-M2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀ
specifiesthetypeofburst(sequentialorinterleaved),ꢀM4-ꢀM6ꢀ
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11ꢀareꢀreservedꢀforꢀfutureꢀuse.
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
until it is programmed again or the device loses power.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle, and the controller must wait the specified time before
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
0
Defined Standard Operation
All Other States Reserved
—
—
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
1
Integrated Silicon Solution, Inc. - www.issi.comꢀ
23
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
BURST LENGTH
ing that the burst will wrap within the block if a boundary
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A7ꢀ(x32)ꢀ
whenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀbyꢀA2-A7ꢀ(x32)ꢀwhenꢀ
theꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A7ꢀ(x32)ꢀwhenꢀtheꢀ
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ
address bit(s) is (are) used to select the starting location
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ
the boundary is reached.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ
with the burst length being programmable, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
mines the maximum number of column locations that can
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengthsꢀofꢀ1,ꢀ2,ꢀ4ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ
sequential and the interleaved burst types, and a full-page
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
command to generate arbitrary burst lengths.
BurstꢀType
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within this block, mean-
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
the burst length, the burst type and the starting column
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A 0
2
0
1
0-1
1-0
0-1
1-0
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
ꢀ
1ꢀ
1ꢀ
A 2
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
A 1
0ꢀ
A 0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
ꢀ2-3-4-5-6-7-0-1ꢀ
ꢀ3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
ꢀ0ꢀ
1ꢀ
8ꢀ
ꢀ
ꢀ1ꢀ
0ꢀ
0ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
1ꢀ
0ꢀ
ꢀ
1ꢀ
1ꢀ
ꢀ
ꢀ
Fullꢀ
Pageꢀ
(y)
nꢀ=ꢀA0-A7ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cn - 1,
ꢀ
(location 0-y)
Cn…
24
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
CAS Latency
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
the registrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
three clocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ
the latency is m clocks, the data will be available by clock
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycle time is such that all relevant access times are met,
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀ
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowableꢀOperatingꢀFrequencyꢀ
table indicates the operating frequencies at which each
CAS latency setting can be used.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ
or incompatibility with future versions may result.
-6
100
100
133
166
143
–
-7
-75E
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
25
10/28/2015
IS42S32400F, IS45S32400F
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
which selects both the bank and the row to be activated
(see ActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).
CLK
HIGH
CKE
CS
After opening a row (issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
the trcdꢀspecification.ꢀMinimumꢀtrcd should be divided by
the clock period and rounded up to the next whole number
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtrcd specification of 18ns with a
125ꢀMHzꢀclockꢀ(8nsꢀperiod)ꢀresultsꢀinꢀ2.25ꢀclocks,ꢀroundedꢀ
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[trcdꢀ(MIN)/tck] ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedure is used to convert other specification limits from
time units to clock cycles).
RAS
CAS
WE
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
same bank can only be issued after the previous active
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
same bank is defined by trc.
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedwhilethefirstbankisbeingaccessed, whichresults
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
different banks is defined by trrd.
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
DON'T CARE
26
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
sameꢀbank.TheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.Theꢀ128Mbꢀ
IS42S32400F, IS45S32400F
READS
READ COMMAND
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowing illustrations, auto precharge is disabled.
HIGH
CKE
CS
RAS
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ
starting column address will be available following the
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ
data-out element will be valid by the next positive clock
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtiming
for each possible CAS latency setting.
CAS
WE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8, A9, A11
A10
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
NO PRECHARGE
BANK ADDRESS
BA0, BA1
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀtwoꢀclocksꢀforꢀoutputꢀbuffers)ꢀ
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
be invalid.
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesbefore
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ
two and three; data element n +ꢀ3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀ
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ
not require the 2n rule associated with a prefetch architec-
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
read accesses can be performed to the same bank, as
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀzeroꢀclocksꢀforꢀinputꢀbuffers)ꢀ
to ensure that the written data is not masked.
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀWRITEꢀ command,ꢀ andꢀ dataꢀ fromꢀ aꢀ fixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediately following the last (or last desired) data element
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided. In a given system design, there may be a pos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
a single-cycle delay should occur between the last read
dataꢀandꢀtheꢀWRITEꢀcommand.
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ
with, aPRECHARGE commandtothesamebank(provided
that auto precharge was not activated), and a full-page burst
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
27
10/28/2015
IS42S32400F, IS45S32400F
diagram for each possible CAS latency; data element n +
3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀ
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequent command to the same bank cannot be issued
until trp is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
and address buses be available at the appropriate time to
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleCASlatency;dataelementn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ
data element of a longer burst.
28
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
DOUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
Integrated Silicon Solution, Inc. - www.issi.comꢀ
29
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
DON'T CARE
30
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
RANDOM READ ACCESSES
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
D
OUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
DON'T CARE
Integrated Silicon Solution, Inc. - www.issi.comꢀ
31
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ BURST TERMINATION
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
x = 1 cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
32
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS tCMH
DQM0 - DQM3
tAS tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
tOH
tOH
tOH
tOH
t
OH
DQ
DOUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
D
OUT
b
tAC
tAC
tAC
tAC
tAC
tAC
tRCD - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
33
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
tAS tAH
ROW
tAS tAH
BA0, BA1
BANK
BANK
tAC
tAC
tAC
tAC
tAC
tAC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+
1
DQ
tLZ
t
OH
tOH
tOH
tOH
tOH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) x32: A8, A9, A11 = "Don't Care"
34
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
OH
t
OH
tOH
tAC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
t
AC
tHZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1) CAS latency = 2, Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
35
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
RQL
High-Z
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
t
RQL
High-Z
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
36
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
precharge.TheꢀdisadvantageꢀofꢀtheꢀPRECHARGEcommand
IS42S32400F, IS45S32400F
WRITES
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
n + 1 is either the last of a burst of two or the last desired
ofꢀaꢀlongerꢀburst.ꢀTheꢀ128MbꢀSDRAMꢀusesꢀaꢀpipelinedꢀ
architecture and therefore does not require the 2n rule as-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
can be initiated on any clock cycle following a previous
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
a page can be performed to the same bank, as shown in
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
be performed to a different bank.
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
WRITE COMMAND
CLK
HIGH
CKE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ
command.ꢀOnceꢀtheꢀREADꢀcomꢀmandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
CS
RAS
CAS
WE
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
same bank (provided that auto precharge was not acti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtdpl after the
clock edge at which the last desired input data element
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtdpl of
at least one clock plus time, regardless of frequency. In
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
must be used to mask input data for the clock edge prior
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1 is either the last of a burst
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
same bank cannot be issued until trp is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8, A9, A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
following illustrations, auto precharge is disabled.
Inthecaseofafixed-lengthburstbeingexecutedtocomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-in element will be
registeredcoincidentwiththeWRITEꢀcommand.Subsequent
data elements will be registered on each successive posi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assuming no other commands have been initiated, the
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
is that it requires that the command and address buses be
availableattheappropriatetimetoissuethecommand;the
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
used to truncate fixed-length or full-page bursts.
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
will be the input data applied one clock previous to the
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn is the last desired data
element of a longer burst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
data provided coincident with the new command applies to
the new command.
Integrated Silicon Solution, Inc. - www.issi.comꢀ
37
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE BURST
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE TO WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
RANDOM WRITE CYCLES
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
38
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
tDPL
DIN
n
D
IN n+1
DIN n+2
DON'T CARE
Integrated Silicon Solution, Inc. - www.issi.comꢀ
39
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
ADDRESS
DQ
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
DPL
DIN
n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
40
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
41
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
tCK
t
CL
t
CH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
tDS
t
DH
DIN
m
D
IN m+
2
DIN m+3
DQ
tRCD
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
42
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
ALTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
t
DS
tDH
tDS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
DPL - BANK 0
tRP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tDPL - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
43
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
CLOCK SUSPEND
of a suspended internal clock edge is ignored; any data
presentꢀonꢀtheꢀDQꢀpinsꢀremainsꢀdriven;ꢀandꢀburstꢀcountersꢀ
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode occurs when a column access/burst
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
the synchronous logic.
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
the internal clock and related operation will resume on the
subsequent positive clock edge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Any command or data present on the input pins at the time
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
D
IN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
D
OUT n+2
DOUT n+3
DON'T CARE
44
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS tAH
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
tAC
tAC
tHZ
DQ
D
OUT
m
D
OUT m+1
DIN e
D
IN e+1
t
LZ
tOH
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
45
Rev. D
10/28/2015
allꢀbanks.Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ
IS42S32400F, IS45S32400F
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-
PRECHARGE Command
tivate the open row in a particular bank or the open row in
CLK
access some specified time (trp)ꢀafterꢀtheꢀPRECHARGEꢀ
command is issued.Input A10 determines whether one or
all banks are to be precharged, and in the case where only
oneꢀbankꢀisꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀ
bank.ꢀWhenꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀ
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ
precharged, it is in the idle state and must be activated
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ
that bank.
HIGH
CKE
CS
RAS
CAS
WE
POWER-DOWN
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ
stateꢀlongerꢀthanꢀtheꢀrefreshꢀperiodꢀ(64ms)ꢀsinceꢀnoꢀrefreshꢀ
operations are performed in this mode.
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ
edge (meeting tcks).ꢀSeeꢀfigureꢀbelowꢀ(Power-Down).
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than 64ms
DON'T CARE
46
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
t
CKS
t
CKH
t
CKS
tCKS
t
CMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM0 - DQM3
A0-A9, A11
ROW
ROW
ALL BANKS
A10
SINGLE BANK
tAS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
Note:
x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
47
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
BURST READ/SINGLE WRITE
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occurs are defined below.
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccess
columns according to the programmed burst length and
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀthreeꢀclocksꢀpriorꢀ
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bank m is registered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
while an access command with auto precharge enabled is
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK n,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tDPL - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
48
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE with Auto Precharge
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITE tobankmwillinterruptaWRITE onbanknwhen
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
registered, with the data-out appearing (CAS latency)
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtdpl
is met, where tdplꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ
registered.ꢀTheꢀlastꢀvalidꢀWRITE to bank n will be data-in
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
tdpl is met, where tdplꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP - BANK m
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
DPL - BANK n
Precharge
t
t
RP - BANK n
Internal States
tDPL - BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
Integrated Silicon Solution, Inc. - www.issi.comꢀ
49
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
t
AC
t
AC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
OH
tOH
t
OH
tOH
t
t
t
RCD
RAS
RC
CAS Latency
DON'T CARE
tRP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
50
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ROW
AS
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
tAC
t
AC
tHZ
D
OUT
m
DOUT m+1
DOUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
51
10/28/2015
IS42S32400F, IS45S32400F
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tOH
tAC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
t
t
t
RCD
RAS
RC
CAS Latency
t
RP
Notes:
1) CAS latency = 2, Burst Length = 1
2) x32: A8, A9, A11 = "Don't Care"
52
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
tAH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
tAH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
tAC
D
OUT
m
t
LZ
t
HZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1) CAS latency = 2, Burst Length = 1
2) x32: A8, A9, A11 = "Don't Care"
Integrated Silicon Solution, Inc. - www.issi.comꢀ
53
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
DPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
54
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
t
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS
t
CMH
DQM0 - DQM3
t
t
t
AS
t
AH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
ALL BANKS
ROW
AS
tAH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
t
DH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A8, A9, A11 = "Don't Care"
3) tras must not be violated.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
55
10/28/2015
IS42S32400F, IS45S32400F
SINGLE WRITE WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
ACTIVE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
tCMS tCMH
DQM0-DQM3
tAS tAH
A0-A9, A11
A10
COLUMN m(2)
ROW
ROW
BANK
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BA0, BA1
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tDPL
tRP
tRAS
DON'T CARE
tRC
Notes:
1) Burst Length = 1
2) x32: A8, A9, A11 = "Don't Care"
3) tras must not be violated.
56
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS tCMH
DQM0 - DQM3
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
tAH
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
SINGLE BANK
AS
tAH
BA0, BA1
BANK
BANK
BANK
tDS
t
DH
DQ
DIN
m
tRCD
tRAS
t
RC
t
DPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) x32: A8, A9, A11 = "Don't Care"
3) tras must not be violated.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
57
10/28/2015
IS42S32400F, IS45S32400F
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to +70°C
Frequency
ꢀ166ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
6ꢀ
6ꢀ
IS42S32400F-6TLꢀ
IS42S32400F-6BLꢀ
IS42S32400F-7TLꢀ
IS42S32400F-7BLꢀ
IS42S32400F-75ETLꢀ
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-freeꢀꢀ
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-free
86-PinꢀTSOPII,ꢀLead-free
7ꢀ
7ꢀ
7.5ꢀ
Industrial Range: -40°C to +85°C
Frequency
ꢀ166ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ133ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
6ꢀ
6ꢀ
IS42S32400F-6TLIꢀ
IS42S32400F-6BLIꢀ
IS42S32400F-6BIꢀ
IS42S32400F-7TLIꢀ
IS42S32400F-7TIꢀ
IS42S32400F-7BIꢀ
IS42S32400F-7BLIꢀ
IS42S32400F-75ETLIꢀ
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-free
90-BallꢀTF-BGA,ꢀLeadedꢀꢀ
86-PinꢀTSOPII,ꢀLead-free
86-PinꢀTSOPII,ꢀLeadedꢀ
90-BallꢀTF-BGA.ꢀLeaded
90-BallꢀTF-BGA,ꢀLead-free
86-PinꢀTSOPII,ꢀLead-free
6ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7.5ꢀ
ORDERING INFORMATION - VDD = 3.3V
Automotive Range: -40°C to +85°C
Frequency
ꢀ166ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
6ꢀ
6ꢀ
7ꢀ
7ꢀ
7ꢀ
IS45S32400F-6TLA1ꢀ
IS45S32400F-6BLA1ꢀ
IS45S32400F-7TLA1ꢀ
IS45S32400F-7BLA1ꢀ
IS45S32400F-7BA1ꢀ
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-freeꢀꢀ
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-free
90-BallꢀTF-BGA,ꢀLeaded
Automotive Range: -40°C to +105°C
Frequency
ꢀ166ꢀMHzꢀ
ꢀ166ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
ꢀ143ꢀMHzꢀ
Speed (ns)
Order Part No.
Package
6ꢀ
6ꢀ
7ꢀ
7ꢀ
IS45S32400F-6TLA2ꢀ
IS45S32400F-6BLA2ꢀ
IS45S32400F-7TLA2ꢀ
IS45S32400F-7BLA2ꢀ
86-PinꢀTSOPII,ꢀLead-free
90-BallꢀTF-BGA,ꢀLead-free
86-PinꢀTSOPII,ꢀLead-freeꢀ
90-BallꢀTF-BGA,ꢀLead-free
*ContactꢀProductꢀManagerꢀforꢀleadedꢀpartꢀsupport.
58
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
Integrated Silicon Solution, Inc. - www.issi.comꢀ
59
Rev. D
10/28/2015
IS42S32400F, IS45S32400F
1 D
60
Integrated Silicon Solution, Inc. - www.issi.com
Rev. D
10/28/2015
相关型号：
©2020 ICPDF网 联系我们和版权申明