IS46LR32640B-5BLA1 [ISSI]
DRAM,;型号: | IS46LR32640B-5BLA1 |
厂家: | INTEGRATED SILICON SOLUTION, INC |
描述: | DRAM, 动态存储器 |
文件: | 总47页 (文件大小:1906K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IS43/46LR32640B
IS43/46LR16128B
2Gb (x16, x32) Mobile DDR SDRAM
Advanced Information
DECEMBER 2019
Description
The IS43/46LR16128B/32640B is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 128Meg
words of 16bits or 64Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data
Input/ Output signals are transmitted on a 16-bit or 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture
with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations
referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• 64ms refresh period (8K cycle)
• Auto & self refresh
• Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
• Concurrent Auto Precharge
• Maximum clock frequency up to 208MHZ
• Maximum data rate up to 416Mbps/pin
• Power Saving support
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
or 1/2, 1/4, 1/8 or 3/4 of Full Strength
• Status Register Read (SRR)
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• LVCMOS compatible inputs/outputs
• Operation Temperature:
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
- Commercial (TA= 0 ~ 70 C )
- Industrial (TA= -40 ~ 85 C )
- Automotive, A1 (TA= -40 ~ 85 C )
- Automotive, A2 (TA= -40 ~ 105 C )
OPTIONS
• Configuration:
- 128Mx16 (32M x16 x 4 banks)
- 64Mx32 (16M x32 x 4 banks)
• Packages:
- 60-Ball TFBGA (8x10 mm) for x16
- 90-Ball TFBGA (8x13 mm) for x32
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Figure 1.1: 60Ball FBGA Ball Assignment (x16)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CK
DQ14
DQ12
DQ10
DQ8
NC
DQ1
DQ3
DQ5
DQ7
A13
/WE
/CS
DQ2
DQ4
DQ6
LDQS
LDM
/CAS
BA0
A0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
/RAS
BA1
G
H
J
CKE
/CK
A9
A11
A12
A8
A6
A7
A10
A2
A1
K
VSS
A4
A5
A3
VDD
[Top View]
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Figure 1.2: 90Ball FBGA Ball Assignment (x32)
1
2
3
4
5
6
7
8
9
A
B
C
D
VDDQ
DQ17
DQ19
DQ21
DQ23
A13
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CLK
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
/CAS
BA0
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSS
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
E
F
G
H
J
/WE
/CS
/RAS
BA1
/CLK
A12
A9
A11
A10
A6
A7
A0
A1
A8
K
L
A2
A4
DM1
DQS1
DQ9
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
A3
A5
DQ7
DQ5
DQ3
DQ1
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ8
DQ10
DQ12
DQ14
VSSQ
M
N
DQ11
DQ13
DQ15
P
R
[Top View]
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Table2 : Pin Descriptions
Symbol
Type
Function
Descriptions
The system clock input. CK and /CK are differential clock
inputs. All address and control input signals are registered on
the crossing of the rising edge of CK and falling edge of /CK.
Input and output data is referenced to the crossing of CK and
/CK.
CK, /CK
Input
System Clock
CKE is clock enable controls input. CKE HIGH activates, and
CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. CKE is synchronous for all functions
except for SELF REFRESH EXIT, which is achieved
asynchronously.
CKE
Input
Input
Input
Clock Enable
Chip Select
/CS enables (registered Low) and disables (registered High)
the command decoder. All commands are masked when /CS
IS REGISTERED high. /CS provides for external bank selection
on systems with multiple banks. /CS is considered part of the
command code.
/CS
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standard mode register or
extended mode register) is loaded during a LOAD MODE
REGISTER command.
BA0, BA1
Bank Address
Address
Row Address
Column Address
: RA0~RA13
: CA0~CA9, CA11 (x16)
A0~A13
Input
Input
CA0~CA9
: A10
(x32)
Auto Precharge
Row Address Strobe,
Column Address Strobe,
Write Enable
/RAS, /CAS and /WE define the operation.
Refer function truth table for details.
/RAS, /CAS, /WE
LDM, UDM
(x16)
DM0~DM3
(x32)
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM balls are input-only.
Input
Data Input Mask
DQ0~DQ15 (x16)
DQ0~DQ31 (x32)
In/Output
In/Output
Data Input/Output
Data input/output pin.
LDQS, UDQS
(x16)
DQS0~DQS3
(x32)
Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. Data strobe is
used to capture data.
Data Input/Output
Strobe
VDD
VSS
Supply
Supply
Supply
Supply
NC
Power Supply
Ground
Power supply
Ground
VDDQ
VSSQ
NC
DQ Power Supply
DQ Ground
Power supply for DQ
Ground for DQ
No connection.
No Connection
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Figure 2.1 : Functional Block Diagram (128Mb X 16)
PASR
Extended
Self refresh
Mode
Write Data Register
2-bit Prefetch Unit
Logic & timer
Register
X16
DS
Internal Row
Counter
X32
32Mx16 BANK 3
Row Active
Row
Pre
Decoder
32Mx16 BANK 2
32Mx16 BANK 1
/CK
CK
CKE
32Mx16 BANK 0
/CS
Refresh
/RAS
DQ0
.
Memory
Cell
Array
|
|
|
|
/CAS
/WE
.
.
Column Active
.
32
|
16
|
Column
Pre
Decoder
LDM/UDM
.
.
.
|
|
DQ15
Column Decoders
Column Add
Counter
Bank Select
UDQS,LDQS
A0
A1
Address
Register
Burst
Counter
Data Strobe
Transmitter
DS
Data Strobe
Receiver
A13
BA0
BA1
CAS
Latency
Mode Register
Data Out Control
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Figure 2.2 : Functional Block Diagram (64Mb X 32)
PASR
Extended
Self refresh
Mode
Write Data Register
2-bit Prefetch Unit
Logic & timer
Register
X32
DS
Internal Row
Counter
X64
16Mx32 BANK 3
Row Active
Row
Pre
Decoder
16Mx32 BANK 2
16Mx32 BANK 1
/CK
CK
CKE
16Mx32 BANK 0
/CS
Refresh
/RAS
DQ0
.
Memory
Cell
Array
|
|
|
|
/CAS
/WE
.
.
Column Active
.
64
|
32
|
Column
Pre
Decoder
DM0~DM3
.
.
.
|
|
DQ31
Column Decoders
Column Add
Counter
Bank Select
DQS0 ~ DQS3
A0
A1
Address
Register
Burst
Counter
Data Strobe
Transmitter
DS
Data Strobe
Receiver
A13
BA0
BA1
CAS
Latency
Mode Register
Data Out Control
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Figure3 : Simplified State Diagram
Power
DPDSX
Power
On
Deep Power
Down
Applied
DPDS
Self
Refresh
SRR
Precharge
All Banks
Read
REFS
MRS
REFSX
MRS
Idle
All Banks
Precharged
Auto
Refresh
MRS
EMRS
REFA
CKEL
CKEH
Precharge
Power
Down
ACT
Active
Power
Down
CKEH
Row
Active
Burst
Stop
CKEL
WRITE
READ
WRITE
READ
BST
READ A
READ
WRITE A
WRITE
READ
WRITE A
READ A
PRE
WRITE A
READ A
PRE
PRE
Precharge
PREALL
PRE
Automatic
sequence
ACT = Active
BST = Burst
PREALL= Precharge All Banks
REFA = Auto Refresh
CKEL = Enter Power- Down
CKEH = Exit Power-Down
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power- Down
EMRS = Ext. Mode Reg. Set
MRS = Mode Register Set
PRE = Precharge
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
READ = Read w/o Auto Precharge
READ A = Read with Auto Precharge
SRR = Status Register Read
WRITE = Write w/o Auto Precharge
WRITE A = Write with Auto Precharge
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Figure4 : Mode Register Set (MRS) Definition
BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
5
A4
4
A3
A2
2
A1
1
A0
0
A13
Address Bus
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
3
Mode Register (Mx)
0
CAS Latency
BT
Burst Length
M6 M5 M4 CAS Latency
M3 Burst Type
Burst Length
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
1
Sequential
Interleave
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
2
3
4
4
Reserved
Reserved
Reserved
Reserved
8
8
16
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note:
M15(BA1) = 0 and M14(BA0) = 0 to select Mode Register
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
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Table3 : Burst Definition
Starting Column Address
Order of Access within a Burst
Burst Length
A3
x
A2
x
A1
x
A0
0
Sequential Mode
Interleave Mode
0-1
1-0
0-1
1-0
2
x
x
x
1
x
x
0
0
0-1-2-3
1-2-3-0
0-1-2-3
1-0-3-2
x
x
0
1
4
x
x
x
x
1
1
0
1
2-3-0-1
3-0-1-2
2-3-0-1
3-2-1-0
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
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Note :
1. For a burst length of two, A1-A9 select the block of two burst; A0 selects the starting column within the block.
2. For a burst length of four, A2-A9 select the block of four burst; A0-A1 select the starting column within the block.
3. For a burst length of eight, A3-A9 select the block of eight burst; A0-A2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Figure5 : Extended Mode Set (EMRS) Register
A13 A12
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
5
A4
A3
A2
2
A1
A0
0
Address Bus
15
1
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
4
0
3
0
1
Extended Mode Register (Ex)
DS
PASR
E2
0
E1
0
E0
Self Refresh Coverage
E7
0
E6
E5
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength(2)
3/4 Strength
Reserved
0
1
0
1
0
Four Banks
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
Two Bank (BA1=0)
One Bank (BA1=BA0=0)
Reserved
0
0
1
0
0
1
0
1
0
Reserved
1
One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
1
1
0
1
1
Reserved
One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
1
1
1
1
0
1
1
Reserved
Reserved
Note:
1. E15(BA1) = 1 and E14(BA0) = 0 to select Extended Mode Register
2. Contact ISSI MKT for 3/4 Strength instead of 1/8 Strength at E7(A7) ~ E5(A5) = 011.
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Functional Description
The 2Gb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648-bits. It is internally
configured as a quad-bank DRAM. The 2Gb Mobile DDR SDRAM uses a double data rate architecture to achieve high speed operation. The
double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle
at the I/O balls, single read or write access for the 2Gb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
Read and Write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0–A13 select the row). The address bits registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has
been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be powered up and initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
Power up and Initialization
Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ (simultaneously).
After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile DDR. Then, 2 or more
Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a Mode Register Set(MRS) command will be issued to
program the specific mode of operation (Cas Latency, Burst length, etc.) And a Extended Mode Register Set(EMRS) command will be issued
to Partial Array Self Refresh(PASR). The following these cycles, the Mobile DDR SDRAM is ready for normal operation. To ensure device
functionality, there is a predefined sequence that must occur at device power up or if there is any interruption of device power.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the same power source and brought
up simultaneously. If separate power sources are used, VDD must lead VDDQ.
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.
3. Once the clock is stable, a 200μs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an executable command.
During this time, NOP or DESELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH
command followed by NOP or DESELECT commands for at least tRFC time. As part of the individualization sequence, two AUTO REFRESH
commands must be issued. Typically, both of these commands are issued at this stage as described above.
7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the order in
which the standard and extended mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.
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Figure6 : Power up sequence
VDD
VDDQ
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
CLK
/CLK
tCL
LVCMOS
HIGH LEVEL
CKE
tIS
tIH
2
3
1
NOP
NOP
PCG
AREF
AREF
MRS
MRS
ACT
RA
NOP
Command
tIS
tIH
CODE
CODE
A0~A9, A11-A13
tIS
tIH
All
CODE
CODE
RA
BA
A10
BA0, BA1
DQS, DQ
Banks
tIS
tIH
tIS
tIH
BA0=L,
BA1=L
BA0=L,
BA1=H
High-Z
DM
T = 200 µs
tCK
4
4
4
4
4
tRP
tRFC
tRFC
tMRD
tMRD
Load Standard Mode Load Extended Mode
Register Register
Power-up: VDD and CLK stable
Don t care
’
Notes:
1.
PCG = PRECHARGE command, MRS = LOAD MODE REGISTER command, AREF = AUTOREFRESH command,
ACT = ACTIVE command, RA = Row address, BA = Bank address.
2.
3.
4.
NOP or DESELECT commands are required for at least 200μs.
Other valid commands are possible.
NOPs or DESELECTs are required during this time.
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Mode Register
The mode register is used to define the specific mode of operation of the Mobile DDR SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency. The mode register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until programmed again, the device goes into deep power-down mode, or the device loses power.
Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency,
and A7-A13 should be set to zero. BA0 and BA1 must be zero to access the mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure
(Mode Register Set Definition). The burst length determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4, or 8 are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9 when the burst
length is set to two; by A2-A9 when the burst length is set to four; by A3-A9 when the burst length is set to eight; and by A4-A9 when the
burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 2, 3 clocks, as shown in Figure (Standard Mode Register Definition).
For CL = 3, if the READ command is registered at clock edge n, then the data will be available at (n + 2 clocks + tAC). For CL = 2, if the
READ command is registered at clock edge n, then the data will be available at (n + 1 clock + tAC).
Figure7 : CAS Latency (BL=4)
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
L
/C K
CLK
READ
NOP
NOP
NOP
NOP
Command
1tCK
tAC
CL=2
tRPRE
tRPST
DQS
DQ
D
D
n+1
D
n+2
D
n+3
OUT
n
OUT
OUT
OUT
2tCK
tAC
CL=3
tRPRE
tRPST
DQS
DQ
D
D
n+1
D
n+2
D
n+3
OUT
n
OUT
OUT
OUT
Don’t care
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Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special
features of the Mobile DDR SDRAM. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command (BA0=0, BA1=1) and retains the stored information until
programmed again, the device goes into deep power-down mode, or the device loses power.
The Extended Mode Register must be programmed with A7 through A13 set to “0”. The Extended Mode Register must be loaded when all
banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation.
Violating either of these requirements results in unspecified operation.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are as follows:
• Full array: banks 0, 1, 2, and 3
• Half array: banks 0 and 1
• Quarter array: bank 0
• One eighth array: half of bank 0
• One sixteenth array: quarter of bank 0
WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH.
Data in banks that are disabled will be lost.
Output Driver Strength
Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive
strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and
A6 of the extended mode register can be used to select the driver strength of the DQ outputs. There are four allowable settings for the
output drivers.
Temperature Compensated Self Refresh
In the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device.
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the
case temperature of the Mobile SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature
ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature.
At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often.
Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
It is not supported for any temperature grade with TA above 85C
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Figure8 : Status Register Read (SRR)
DQ6
DQ10 DQ9 DQ8 DQ7
DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQ14 DQ13
DQ11
DQ15
DQ12
Data Bus (DQ)
15
14
Density
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Sx)
DT
DW
Refresh
Revision ID
Manufacturer
Multiplier
Refresh
S3
S2
S1
S0
Manufacturer ID
S15 S14 S13
Density
S10 S9 S8
Multipliers
Reserved
Reserved
Reserved
2x
1
0
1
1
ISSI
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
128Mb
256Mb
512Mb
1Gb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
All
others
Other
manufacturers
2Gb
1x
Reserved
Reserved
Reserved
Reserved
0.25x
Reserved
Device
Width
Device
Type
S11
S12
0
1
x16
x32
0
1
mDDR
LPDDR2
Status Register Read
The Status Register Read (SRR) command allows the user to access the manfacturer device information. It is optional for the user. The 16-
bit encoded data is stored in the Status Register, and can be output onto DQ0~DQ15, with a fixed burst length (BL) of 2. The Manufacturer's
ID is on S0~S3, the Device Revision ID is on S4~S7, the Refresh Rate is on S8~S10, the Data Width is on S11, the Device Type is on S12,
and the Density is on S13~S15. The SRR command sequence is as follows:
• All banks must be idle, and Reads and Writes completed
• A Mode Register Set (MRS) command is issued with BA0=1, BA1=0, and A0~A12=0 to initiate SRR
• After a time period tSRR, a Read command is issued to any bank or address
• The next valid command may be issued a time period tSRC after the Read command
The Read command causes the Status Register data to be output after two or three clock cycles, whichever corresponds to the CAS Latency
setting. In the second half of the Read burst, the DQ0~DQ15 values are "Don't Care”.
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Commands
The following COMMANDS Truth Table and DM Operation Truth Table provide quick reference of available commands. This is followed by a
written description of each command.
Deselect
The DESELECT function (/CS HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is
effectively deselected. Operations already in progress are not affected.
NO Operation (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (/CS = LOW, /RAS = /CAS = /WE =
HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
Active
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0–A13 selects the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
Read
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not
selected, the row will remain open for subsequent accesses.
Write
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A9 selects the starting column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the
DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to
memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
Precharge
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of
precharging.
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Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit
command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A
precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This
device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto
precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an
explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN). The user must not issue another
command to the same bank until the precharge time (tRP) is completed.
Burst Terminate
The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ
command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains
open.
Auto Refresh
AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in
FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the
internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 2Gb Mobile DDR SDRAM
requires AUTO REFRESH cycles at an average interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval is provided.
Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the auto refresh period.
The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.
Self Refresh
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When
in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during SELF
REFRESH.
During SELF REFRESH, the device is refreshed as identified in the external mode register (see PASR setting). For a the full array refresh, all
four banks are refreshed simultaneously with the refresh frequency set by an internal self refresh oscillator. This oscillator changes due to
the temperature sensors input. As the case temperature of the Mobile DDR SDRAM increases, the oscillation frequency will change to
accommodate the change of temperature. This happens because the DRAM capacitors lose charge faster at higher temperatures. To ensure
efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, Clock must be stable prior to CKE going back HIGH. Once
CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tXSR is required for the completion of any internal refresh in
progress. The SELF REFRESH command is not applicable for operation with TA > 85C.
Deep Power-down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the
devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while
CKE is low. This mode is exited by asserting CKE high.
This mode is not applicable for operation with TA > 85C.
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Table4: Command Truth Table
Function
/CS
/RAS
/CAS
/WE
BA
A10/AP
ADDR
Note
DESELECT (NOP)
H
X
X
X
X
X
X
2
NO OPERATION (NOP)
L
H
H
H
X
X
X
2
ACTIVE (Select Bank and activate Row)
L
L
L
H
L
H
H
V
V
Row
L
Row
Col
READ (Select bank and column and start read burst)
H
READ with AP (Read Burst with Auto recharge)
WRITE (Select bank and column and start write burst)
WRITE with AP (Write Burst with Auto recharge)
BURST TERMINATE or enter DEEP POWER DOWN
PRECHARGE (Deactivate Row in selected bank)
PRECHARGE ALL (Deactivate rows in all banks)
AUTO REFRESH or enter SELF REFRESH
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
L
L
L
L
H
L
V
V
V
X
V
X
X
V
H
L
Col
Col
Col
X
3
L
H
X
L
3
4,5
6
H
H
H
L
X
L
H
X
X
6
L
X
7,8,9
10
MODE REGISTER SET
L
L
Op_Code
Table5 : DM Truth Table
Function
Write Enable
Write Inhibit
DM
L
DQ
Valid
X
Note
11
H
11
Note:
1. All states and sequences not shown are illegal or reserved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge
4. Burst Terminate applies to only Read bursts with autoprecharge disabled.
This command is undefined and should not be used for Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are don‘t
care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select among Mode Register (MRS) or Extended Mode Register (EMRS).
11. Used to mask write data, provided coincident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
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Table6 : CKE Truth Table
CKEn-1
CKEn
Current State
Power Down
COMMANDn
ACTIONn
Note
L
L
L
L
L
L
H
L
L
X
Maintain Power Down
Maintain Self Refresh
Maintain Deep Power Down
Exit Power Down
Self Refresh
X
L
Deep Power Down
Power Down
X
H
H
H
L
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
NOP or DESELECT
5,6,9
5,7,10
5,8
Self Refresh
Exit Self Refresh
Deep Power Down
All Banks Idle
Exit Deep Power Down
Precharge Power
Down entry
5
H
L
Bank(s) Active
NOP or DESELECT
Active Power Down
Entry
5
H
H
L
L
All Banks Idle
All Banks Idle
AUTO REFRESH
Self Refresh Entry
BURST TERMINATE
Enter Deep Power
Down
H
H
See the other Truth Tables
Note:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of Mobile DDR immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description.
9. The clock must toggle at least one time during the tXP period.
10. The clock must toggle at least once during the tXSR time.
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Table7 : Current State BANKn Truth Table(COMMAND TO BANK n)
Command
Current State
Action
Note
/CS
/RAS
/CAS
/WE
Description
DESELECT(NOP)
NOP
H
L
L
L
X
H
L
X
H
H
L
X
H
H
H
Continue previous Operation
Continue previous Operation
Select and activate row
Auto refresh
Any
Idle
ACTIVE
L
AUTO REFRESH
10
10
MODE REGISTER
SET
L
L
L
L
Mode register set
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
PRECHARGE
READ
No action if bank is idle
Select Column & start read burst
Select Column & start write burst
Deactivate Row in bank (or banks)
Truncate Read & start new Read burst
Truncate Read & start new Write burst
Truncate Read, start Precharge
Burst terminate
Row Active
L
WRITE
H
L
L
PRECHARGE
READ
4
H
H
L
H
L
5,6
Read
(without Auto
recharge)
L
WRITE
5,6,13
H
H
L
L
PRECHARGE
BURST TERMINATE
READ
H
H
H
L
L
11
5,6,12
5,6
H
L
Truncate Write & start new Read burst
Truncate Write & start new Write burst
Truncate Write, start Precharge
Write
(without Auto
precharge)
L
WRITE
H
L
PRECHARGE
12
Note:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or
Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with autoprecharge is enabled.
6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank.
DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table3, and according to Truth Table 4.
• Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
• Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the ''row active'' state.
• Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends when tRP has
been met. Once tRP has been met, the bank will be in the idle state.
• Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been
met. Once tRP is met, the bank will be in the idle state.
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9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be appliedto each
positive clock edge during these states.
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met.
Once tRFC is met, the Mobile DDR will be in an ''all banks idle'' state.
• Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the Mobile DDR will be in an ''all banks idle'' state.
• Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end the
READ prior to asserting a WRITE command.
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Table8 : Current State BANKn Truth Table (COMMAND TO BANK m)
Command
Current State
Action
Note
/CS
H
L
/RAS
X
/CAS
X
/WE
X
Description
DESELECT(NOP)
NOP
Continue previous Operation
Continue previous Operation
Any command allowed to bank m
Activate Row
Any
Idle
H
X
H
X
H
X
X
L
ANY
L
H
L
H
H
L
ACTIVE
L
H
H
L
READ
Start READ burst
Start WRITE burst
Precharge
8
8
Row Activating, Active,
or Precharging
L
L
WRITE
L
H
H
L
L
PRECHARGE
ACTIVE
L
L
H
H
L
Activate Row
L
H
H
L
READ
State READ burst
Start WRITE burst
Precharge
8
Read with Auto Precha
rge disabled
L
L
WRITE
8,10
L
H
H
L
L
PRECHARGE
ACTIVE
L
L
H
H
L
Activate Row
L
H
H
L
READ
Start READ burst
Start WRITE burst
Precharge
8,9
8
Write with Auto
precharge disabled
L
L
WRITE
L
H
H
L
L
PRECHARGE
ACTIVE
L
L
H
H
L
Activate Row
L
H
H
L
READ
Start READ burst
Start WRITE burst
Precharge
5,8
Read with Auto
Precharge
L
L
WRITE
5,8,10
L
H
H
L
L
PRECHARGE
ACTIVE
L
L
H
H
L
Activate Row
L
H
H
L
READ
Start READ burst
Start WRITE burst
Precharge
5,8
5,8
Write with Auto
precharge
L
L
WRITE
L
H
L
PRECHARGE
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Note:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or
Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge enabled states
can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is defined as if the
same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still
accesses all the data in the burst.
For Write with Auto precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled.
The access period starts with registration of the command and ends where the precharge period (or tRP) begins.
During the precharge period, of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE,
PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE
commands to the other banks may be applied. In either case, all other related limitations apply
(e.g. contention between READ data and WRITE data must be avoided).
6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank;
It applies to the bank represented by the current state only.
8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and READs and WRITEs
with AUTO PRECHARGE disabled.
9. Requires appropriate DM masking.
10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to
end the READ prior to asserting a WRITE command.
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Table9 : Absolute Maximum Rating
Parameter
Storage Temperature
Symbol
TSTG
Rating
-55 ~ 150
-0.3 ~ 2.7
-0.3 ~ 2.7
50
Unit
C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
V
V
mA
W
PD
1.5
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table10 : Operating Temperature
Parameter
Symbol
Rating
-40 ~ 105
-40 ~ 85
-40 ~ 85
0 ~ 70
Unit
Ambient Temperature (Automotive, A2)
Ambient Temperature (Automotive, A1)
Ambient Temperature (Industrial)
Ambient Temperature (Commercial)
TA
C
Table11 : AC/DC Operating Conditions (1)
Parameter
Symbol
Min
Typ
1.8
Max
Unit
Note
Power Supply Voltage
VDD
1.7
1.95
V
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDDQ
VIH (DC)
VIL (DC)
1.7
0.7 x VDDQ
-0.3
1.8
1.95
V
V
V
2
VDDQ + 0.3
0.3 x VDDQ
Input Differential Voltage, for
CK, /CK inputs
VID (DC)
0.4 x VDDQ
VDDQ + 0.6
V
3
Output High Voltage
VOH (DC)
VOL (DC)
ILI
0.9 x VDDQ
-
V
V
IOH=-0.1mA
IOL=0.1mA
Output Low Voltage
-
0.1 x VDDQ
2
Input Leakage Current
Output Leakage Current
Input High Voltage, all inputs
Input Low Voltage, all inputs
-2
-5
uA
uA
V
ILO
5
VIH (AC)
VIL (AC)
0.8 x VDDQ
-0.3
VDDQ + 0.3
0.2 x VDDQ
V
Input Differential Voltage, for C
K, /CK inputs
VID(AC)
VIX(AC)
0.6 x VDDQ
0.4 x VDDQ
VDDQ + 0.6
0.6 x VDDQ
V
V
3
4
Input Differential Crosspoint
Voltage for CK and /CK inputs
Notes :
1. All Voltages are referenced to VSS = 0V
2. VDD and VDDQ must track each other, and VDDQ must not exceed the level of VDD.
3. The magnitude of difference between input level on CK and input level on /CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
24
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Table12 : Capacitance (TA=25 C, f=1MHz, VDD=1.8V)
Parameter
Pin
Symbol
Min
Max
Unit
CK, /CK
CI1
1.5
5
pF
A0~A13, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE
Input Capacitance
CI2
1.5
5
pF
DM0~DM3
CI3
CIO
3.0
3.0
5.0
5.0
pF
pF
Data & DQS Input/Output Capacitance
DQ0~DQ31, DQS0~DQS3
Table13 : AC Operating Test Condition
(TA= 0 ~ 70 C for Commercial, or TA= -40 ~ 85 C for Industrial or Automotive, VDD = 1.7V to 1.95V, VSS=0V)
Parameter
AC Input High/Low Level Voltage
Symbol
VIH / VIL
VTRIP
Value
0.8 x VDDQ / 0.2 x VDDQ
0.5 x VDDQ
1 / 1
Unit
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
V
tR / tF
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
VOUTREF
CL
0.5 x VDDQ
30
pF
Figure8 : Output load circuit
VDDQ
VTT=0.5 x VDDQ
13.9K
50
Output
Output
Z0=50
30pF
30pF
10.6K
DC Output Load Circuit
AC Output Load Circuit
Table14 : AC Overshoot/Undershoot Specification
Parameter
Specification
Maximum Peak Amplitude allowed for Overshoot Area
Maximum Peak Amplitude allowed for Undershoot Area
Maximum Overshoot Area above VDD/VDDQ
Maximum Undershoot Area below VSS/VSSQ
0.9V
0.9V
3V-ns
3V-ns
Figure9 : AC Overshoot/Undershoot Definition
Overshoot Area
Undershoot Area
Maximum Amplitude
Maximum Amplitude
VDD/VDDQ
VSS/VSSQ
Voltage [V]
Time [ns]
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Table15B : DC Characteristic (DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
Unit Note
-5
-6
-75
140
tRC = tRC(min), tCK = tCK(min), CKE is HIGH, /CS is
HIGH between valid commands, address inputs are
SWITCHING, data bus inputs are STABLE
Operating one bank active-
precharge current
IDD0
190
150
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
All banks idle, CKE is LOW, /CS is HIGH, tCK =
tCK(min), address and control inputs are SWITCHING,
data bus inputs are STABLE
Precharge power-down
standby current
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
10
10
70
60
10
10
70
54
Precharge power-down
standby current with clock
stop
All banks idle, CKE is LOW, /CS is HIGH, CK = LOW,
/CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE
All banks idle, CKE is HIGH, /CS is HIGH, tCK =
tCK(min) , address and control inputs are SWITCHING,
data bus inputs are STABLE
Precharge non power-down
standby current
Precharge non power-down
standby current with clock
stop
All banks idle, CKE is HIGH, /CS is HIGH, CK = LOW,
/CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE
One bank active, CKE is LOW, /CS is HIGH, tCK =
tCK(min), address and control inputs are SWITCHING,
data bus inputs are STABLE
Active power-down standby
current
One bank active, CKE is LOW, /CS is HIGH, CK = LOW,
/CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE
Active power-down standby
current with clock stop
IDD3PS
IDD3N
IDD3NS
One bank active, CKE is HIGH, /CS is HIGH, tCK =
tCK(min), address and control inputs are SWITCHING,
data bus inputs are STABLE
Active non power-down
standby current
Active non power-down
standby current with clock
stop
One bank active, CKE is HIGH, /CS is HIGH, CK =
LOW, /CK = HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE
One bank active, BL=4, CL=3, tCK = tCK(min),
continuous read bursts, IOUT=0mA,
address inputs are SWITCHING, 50% data change
each burst transfer
Operating burst read current
Operating burst write current
IDD4R
180
180
170
160
160
mA
1
One bank active, BL=4, tCK=tCK(min), continuous
write bursts, address inputs are SWITCHING, 50%
data change each burst transfer
IDD4W
IDD5
170
160
mA
mA
1
2
tRC=138ns, tCK=tCK(min), burst refresh,
CKE is HIGH, address and control inputs are
SWITCHING, data bus inputs are STABLE
Auto Refresh Current
PASR
TCSR
85C
45C
85C
45C
85C
45C
85C
45C
85C
45C
10
3.5
9
4 banks
CKE is LOW
2 Banks
1 Bank
3.2
8
CK=LOW, /CK=HIGH
tCK=tCK(min)
Extended Mode Register set to all 0's, address and
control inputs are STABLE, data bus inputs are
STABLE
Self
Refresh
Current
IDD6
mA
4
2.8
7
Half
Bank
2.4
7
Quarter
Bank
2.4
Standby Current in
Deep Power Down Mode
Address and control inputs are STABLE, data bus
inputs are STABLE
IDD8
20
uA
5
Note : 1. Measured with outputs open. 4. Values apply for tA 85oC
2. Refresh period is 64ms.
3. -75 is for reference only.
5. Typical value at room temperature.
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Table16: AC Characteristic (AC operation conditions unless otherwise noted)
-5
Parameter
Symbol
Unit Note
Min
4.8
12
Max
CL=3
CL=2
CL=3
CL=2
ns
ns
ns
1
1
System Clock Cycle time
tCK
2.0
2.0
0.45
0.45
1
5.0
6.5
DQ Output access time from CK, /CK
tAC
Clock High pulse width
Clock Low pulse width
tCH
0.55
0.55
tCK
tCK
tCK
ns
tCL
CKE min. pulse width (High/Low pulse width)
DQ and DM Input Setup time
tCKE
tDS
0.4
0.4
1.4
0.9
0.9
2.3
1.0
0.4
2, 3, 4
DQ and DM Input Hold time
tDH
ns
2, 3, 4
DQ and DM Input Pulse width
tDIPW
tIS
ns
5
Address and Control Input Setup time
Address and Control Input Hold time
Address and Control Input Pulse Width
DQ & DQS Low-impedance time from CK, /CK
DQ & DQS High-impedance time from CK, /CK
DQS - DQ Skew
ns
4, 6, 7
tIH
ns
4, 6, 7
tIPW
tLZ
ns
5
8
8
9
ns
tHZ
0.6
0.4
tCK
ns
tDQSQ
tHP
Half Clock Period
tCH, tCL
ns
Data Hold Skew Factor
tQHS
tQH
0.5
ns
DQ / DQS Output Hold time from DQS
Write Command to first DQS Latching Transition
DQS Input High pulse Width
tHP-tQHS
0.7
ns
tDQSS
tDQSH
tDQSL
tDSS
tDSH
1.2
0.6
0.6
tCK
tCK
tCK
tCK
tCK
ns
0.4
DQS Input Low pulse Width
0.4
DQS Falling Edge to CK Setup Time
DQS Falling Edge Hold Time From CK
0.2
0.2
CL=3
CL=2
2.0
5.0
8.0
Access Window of DQS from CK, /CK
tDQSCK
2.0
ns
tRAS
tRC
ACTIVE to PRECHARGE Command Period
ACTIVE to ACTIVE Command Period
Mode Register Set command cycle time
Average periodic refresh interval
Auto Refresh Period
38.4
52.8
2
70K
ns
ns
tMRD
tREFI
tRFC
tRCD
tRP
tCK
us
7.8
10, 15
72
14.4
14.4
9.6
ns
Active to Read or Write delay
Precharge command period
Active Bank A to Active Bank B Delay
Read of SRR to next valid command
SRR to read
ns
ns
tRRD
tSRC
tSRR
tWR
ns
CL + 1
2
tCK
tCK
ns
Write Recovery time
14.4
Auto Precharge Write Recovery + Precharge time
Internal Write to Read Command Delay
tDAL
tWTR
(tWR/tCK) + (tRP/tCK)
2
tCK
tCK
tCK
tCK
tCK
ns
CL=3
0.9
0.5
0.4
0.25
0
1.1
1.1
0.6
11
11
DQS Read preamble
CL=2
tRPRE
DQS Read postamble
tRPST
tWPRE
tWPRES
tWPST
tXP
DQS Write preamble
DQS Write preamble setup time
DQS Write postamble
12
13
14
0.4
1
0.6
tCK
tCK
ns
Exit Power Down to next valid command Delay
Self Refresh Exit to next valid Command Delay
tXSR
110
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Table16: AC Characteristic (AC operation conditions unless otherwise noted)
-6 -75
Parameter
Symbol
Unit Note
Min
6
Max
Min
7.5
12
Max
CL=3
CL=2
CL=3
CL=2
ns
ns
ns
1
1
System Clock Cycle time
tCK
12
2.0
2.0
0.45
0.45
1
5.0
8.0
2.5
2.5
0.45
0.45
1
6.0
8.0
DQ Output access time from CK, /CK
tAC
Clock High pulse width
Clock Low pulse width
tCH
tCL
0.55
0.55
0.55
0.55
tCK
tCK
tCK
ns
CKE min. pulse width (High/Low pulse width)
DQ and DM Input Setup time
tCKE
tDS
0.6
0.8
2, 3, 4
DQ and DM Input Hold time
tDH
tDIPW
tIS
0.6
1.6
1.1
1.1
2.7
1.0
0.4
0.8
1.8
1.3
1.3
3.0
1.0
0.4
ns
ns
ns
ns
ns
ns
2, 3, 4
DQ and DM Input Pulse width
5
Address and Control Input Setup time
Address and Control Input Hold time
Address and Control Input Pulse Width
DQ & DQS Low-impedance time from CK, /CK
4, 6, 7
tIH
4, 6, 7
tIPW
tLZ
5
8
8
9
DQ & DQS High-impedance time from CK, /CK
DQS - DQ Skew
tHZ
0.6
0.5
0.6
0.6
tCK
ns
tDQSQ
tHP
Half Clock Period
tCH, tCL
tCH, tCL
ns
Data Hold Skew Factor
tQHS
tQH
0.65
0.75
ns
DQ / DQS Output Hold time from DQS
Write Command to first DQS Latching Transition
DQS Input High pulse Width
tHP-tQHS
0.7
0.4
0.4
0.2
0.2
2.0
2.0
42
tHP-tQHS
0.75
0.4
ns
tDQSS
tDQSH
tDQSL
tDSS
tDSH
1.25
0.6
1.2
0.6
0.6
tCK
tCK
tCK
tCK
tCK
ns
DQS Input Low pulse Width
0.6
0.4
DQS Falling Edge to CK Setup Time
DQS Falling Edge Hold Time From CK
0.2
0.2
CL=3
CL=2
5.0
8.0
2.5
6.0
8.0
Access Window of DQS from CK, /CK
tDQSCK
2.5
ns
tRAS
tRC
ACTIVE to PRECHARGE Command Period
ACTIVE to ACTIVE Command Period
Mode Register Set command cycle time
70K
45
70K
ns
60
70
ns
tMRD
2
2
tCK
Average periodic refresh interval
Auto Refresh Period
tREFI
tRFC
7.8
7.8
us
ns
10, 15
72
72
Active to Read or Write delay
Precharge command period
Active Bank A to Active Bank B Delay
Read of SRR to next valid command
SRR to read
tRCD
tRP
18
18
22
22
ns
ns
tRRD
tSRC
tSRR
tWR
12
15
ns
CL + 1
2
CL + 1
2
tCK
tCK
ns
Write Recovery time
15
15
Auto Precharge Write Recovery + Precharge time
Internal Write to Read Command Delay
tDAL
tWTR
(tWR/tCK) + (tRP/tCK)
2
2
0.9
0.5
0.4
0.25
0
tCK
tCK
tCK
tCK
tCK
ns
CL=3
1.1
1.1
0.6
0.9
0.5
0.4
0.25
0
1.1
1.1
0.6
11
11
DQS Read preamble
CL=2
tRPRE
DQS Read postamble
tRPST
tWPRE
tWPRES
tWPST
tXP
DQS Write preamble
DQS Write preamble setup time
DQS Write postamble
12
13
14
0.4
1
0.6
0.4
1
0.6
tCK
tCK
ns
Exit Power Down to next valid command Delay
Self Refresh Exit to next valid Command Delay
tXSR
120
120
28
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Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to
VIL(AC) for falling input signals.
3. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
4. Input slew rate ≥ 0.5V/ns and < 1.0V/ns.
Input setup/hold slew rate [V/ns]
∆tDS/∆tIS [ps]
∆tDH/∆tIH [ps]
1.0
0.5
0
0
+150
+150
5. These parameters guarantee device timing but they are not necessarily tested on each device.
6. The transition time for address and command inputs is measured between VIH and VIL.
7. A CK,/CK slew rate must be ≥ 1.0V/ns (2.0V/ns if measured differentially) is assumed for this parameter.
CK,/CK setup/hold slew rate [V/ns]
1.0
∆tDS/∆tIS [ps]
∆tDH/∆tIH [ps]
0
0
8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
9. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
10. A maximum of eight Refresh commands can be posted to any given Low-Power DDR SDRAM, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8*tREFI.
11. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system.
It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or
transitioning from HIGH to LOW at this time, depending on tDQSS.
13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
14. At least one clock pulse is required during tXP.
15. The specifications in the table for TREF and TREFI are applicable for all temperature grades with TA ≤ +85°C. Only A2 temperature grade
supports operation with TA > +85°C, and these values must be further constrained with TREF max of 32ms, and TREFI max of 3.9μs.
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Timing Diagram
Bank/row Activation
The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs
selects the bank, and the address provided on A0-A13 (or the highest address bit) selects the row.
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be opened. This
is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. The row remains active until a
PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command is issued to the bank.
A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before opening a different
row in the same bank.
Figure10 : Active command
CLK
/CLK
CKE
/CS
/RAS
/CAS
Notes :
1. RA : Row address
2. BA : Bank address
/WE
RA
BA
A0~A13
BA0, BA1
Don’t care
Once a row is Open(with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification.
tRCD(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command can be entered.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been
closed(precharge). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent
ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
Figure11 : tRCD, tRRD, tRC
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
/CLK
CLK
tCK
tCH
tCL
tIS
tIH
RD/WT
with AP
ACT
NOP
NOP
NOP
ACT
NOP
ACT
Command
A0-A13
ROW
COL
ROW
ROW
Bank
a
Bank
a
Bank b
Bank a
BA0, BA1
tRCD
tRRD
tRC
Don t care
’
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Read
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select
the starting column location.
The value of A10 determines whether or not auto-precharge is used. If auto-precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-
out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble and the last data-
out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon completion of a burst, assuming no new READ
commands have been initiated, the I/O's will go high-Z.
CLK
Figure12 : Read command
/CLK
CKE
/CS
/RAS
/CAS
Notes :
1. CA : Column address
/WE
2. BA : Bank address
CA
A0~A9
3. A10=High : Enable Auto precharge
A10=Low : Disable Auto precharge
A10
Dont care
’
BA0, BA1
BA
Figure13 : Read Data out timing (BL=4)
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
/CLK
CLK
READ
NOP
NOP
NOP
NOP
Command
Address
Bank a
COL n
CL=2
tRPST
tAC
tRPRE
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL=3
tAC
tDQSCK
tRPST
tRPRE
DQS
DQ
tDQSQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
n
tLZ
tQH
tHZ
Don’t care
Notes:
1. BL=4
2. Shown with nominal tAC, tDQSCK and tDQSQ
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Figure14 : Consecutive Read bursts (BL=4)
T0
T1
T2
T3
T4
T5
/CLK
CLK
READ
NOP
READ
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
CL=3
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
m
DOUT
m+1
Dont care
’
Notes:
1. Dout n or m = Data-Out from Column n or m
2. BL=4,8 (if 4, the bursts are concatenated; If 8, the second burst interrupts the first)
3. Shown with nominal tAC, tDQSCK and tDQSQ
Figure15 : Non-Consecutive Read bursts (BL=4)
T0
T1
T2
T3
T4
T5
/CLK
CLK
READ
NOP
NOP
READ
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
CL=3
CL=3
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
m
DOUT
m+1
Don t care
’
Notes:
1. Dout n or m = Data-Out from Column n or m
2. BL=4,8 (if 4, the bursts are concatenated; If 8, the second burst interrupts the first)
3. Shown with nominal tAC, tDQSCK and tDQSQ
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Figure16 : Random Read access
T0
T1
T2
T3
T4
T5
/CLK
CLK
READ
READ
READ
READ
NOP
NOP
NOP
Command
Bank a
COL n
Bank a
COL m
Bank a
COL p
Bank a
COL q
Address
CL=3
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
m
DOUT
m+1
DOUT
p
DOUT
p+1
DOUT
q
DOUT
q+1
Don t care
’
Notes:
1. Dout n or m,p,q = Data-Out from Column n or m,p,q
2. BL=2,4,8 (if 4 or 8, the following burst interrupts the previous)
3. Reads are to an Active row in any bank.
4. Shown with nominal tAC, tDQSCK and tDQSQ
Truncated Reads
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure16. The BURST TERMINATE
latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command,
where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is
necessary, the BURST TERMINATE command must be used.
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not
activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data
element pairs (pairs are required by the n-prefetch architecture). This is shown in Figure (READ to PRECHARGE). Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Figure17 : Read Burst terminate (BL=4 or 8)
T0
T1
T2
T3
T4
/CLK
CLK
READ
BST
NOP
NOP
NOP
Command
Address
Bank a
COL n
CL=3
DQS
DQ
D
OUT
n
D
OUT
n+1
Don t care
’
Notes:
1. Dout n = Data-Out from Column n
2. CKE=high
3. Shown with nominal tAC, tDQSCK and tDQSQ
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Figure18 : Read to write terminate (BL=4 or 8)
T0
T1
T2
T3
T4
T5
/CLK
CLK
READ
BST
NOP
NOP
WRITE
Bank a
NOP
Command
Address
Bank a
COL n
COL
m
CL=3
tDQSS
(NOM )
DQS
DQ
OUT
OUT
IN
D
IN
D
D
D
n
n+1
m
m +1
Don t care
’
Notes:
1. Dout n = Data-Out from Column n , Din m = Data-In from Column m.
2. CKE=high
3. Shown with nominal tAC, tDQSCK and tDQSQ
Figure19 : Read to Precharge (BL=4)
T0
T1
T2
T3
T4
T5
/CLK
CLK
READ
NOP
PCG
NOP
NOP
ACT
Command
ADDRESS
Bank a
COL n
Bank a
(a, or all)
Bank a
Row
tRP
CL =3
DQS
DQ
D
D
n+1
D
n+2
D
n+3
OUT
n
OUT
OUT
OUT
Don t care
’
Notes:
1. Dout n = Data-Out from Column n.
2. Read to Precharge equals 2 tCK, which allows 2 data pairs of Data-Out.
3. Shown with nominal tAC, tDQSCK and tDQSQ
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Write
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs
select the starting column location.
The value of A10 determines whether or not auto precharge is used.If autoprecharge is selected, the row being accessed will be precharged
at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. Input data appearing on the
data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is
registered low, the corresponding data will be written to the memory; if the DM signal is registered high, the corresponding data-inputs will
be ignored, and a write will not be executed to that byte/column location. The memory controller drives the DQS during write operations.
The initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write postamble. Upon
completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z and any additional input data will be
ignored.
Figure20 : Write command
CLK
/CLK
CKE
/CS
/RAS
Notes :
1. CA : Column address
/CAS
2. BA : Bank address
3. A10=High : Enable Auto precharge
A10=Low : Disable Auto precharge
/WE
CA
A0~A9
A10
BA
BA0, BA1
Dont care
’
Figure21 : Write Burst (BL=4)
T0
T1
T1n
T2
T2n
T3
/CLK
CLK
WRITE
NOP
WRITE
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
tDQSH
tWPST
DQS
tWPRES
tWPRE
tDS
tDH
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DQ
DM
Don t care
’
Notes:
1. Din n = Data-In from Column n.
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Figure22 : Consecutive Write to write (BL=4)
T0
T1
T2
T3
T4
T5
/CLK
CLK
WRITE
NOP
WRITE
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
(NOM )
DQS
DQ
D
D
IN
n+1
D
IN
n+2
D
IN
n+3
D
D
IN
m+1
D
IN
m +2
D
IN
m+3
IN
IN
n
m
DM
Don’t care
Notes:
1. Din n = Data-In from Column n.
2. Each Write command may be to any banks.
Figure23 : Non-Consecutive Write to write (BL=4)
T0
T1
T2
T3
T4
T5
/CLK
CLK
WRITE
NOP
NOP
WRITE
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
tDQSS
(NOM )
(NOM )
DQS
DQ
IN
D
n
IN
IN
D
n+2
IN
IN
D
m
IN
IN
D
m +2
IN
D
m+3
D
D
D
n+1
n+3
m+1
DM
Don’t care
Notes:
1. Din n = Data-In from Column n.
2. Each Write command may be to any banks.
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Figure24 : Random Write to write
T0
T1
T2
T3
T4
/CLK
CLK
WRITE
WRITE
WRITE
WRITE
NOP
Command
Bank a
COL n
Bank a
COL p
Bank a
COL m
Bank a
COL q
Address
tDQSS
(NOM)
DQS
DQ
DIN
n
DIN
n+1
DIN
p
DIN
p+1
DIN
m
DIN
m+1
DIN
q
DIN
q+1
DM
Don’t care
Notes:
1. Din n,p,m,q = Data-In from Column n,p,m,q.
2. Each Write command may be to any banks.
Figure25 : Write to Read (Uninterrupting)
T0
T1
T2
T3
T4
T5
T6
T7
/CLK
CLK
WRITE
NOP
NOP
NOP
READ
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
(NOM)
tWTR
CL=3
DQS
DQ
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DOUT
m
DOUT
m+1
DOUT
m+2
DM
Don’t care
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWTR is not required and the Read command
could be applied ealier.
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Figure26 : Write to Read (Interrupting)
T0
T1
T2
T3
T4
T5
T6
T7
/CLK
CLK
WRITE
NOP
NOP
READ
NOP
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
(NOM)
tWTR
CL=3
DQS
DQ
DIN
n
DIN
n+1
DOUT
m
DOUT
m+1
DOUT
m+2
DOUT
m+3
DM
Don’t care
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
Figure27 : Write to Read (Odd number of data Interrupting)
T0
T1
T2
T3
T4
T5
T6
T7
/CLK
CLK
WRITE
NOP
NOP
READ
NOP
NOP
NOP
NOP
Command
Address
Bank a
COL n
Bank a
COL m
tDQSS
(NOM)
tWTR
CL=3
DQS
DQ
DIN
n
DOUT
m
DOUT
m+1
DOUT
m+2
DOUT
m+3
DM
Don’t care
Notes:
1. Din n = Data-In from Column n, Dout m = Data-Out from Column m.
2. tWTR is referenced from the first positive CK edge after the last data-in pair.
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Figure28 : Write to Precharge (Uninterrupting)
T0
T1
T2
T3
T4
T5
/CLK
CLK
WRITE
NOP
NOP
NOP
NOP
PCG
Command
Address
Bank a
COL n
tDQSS
(NOM)
tWR
DQS
DQ
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DM
Don’t care
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ealier.
Figure29 : Write to Precharge (Interrupting)
T0
T1
T2
T3
T4
T5
/CLK
CLK
WRITE
NOP
NOP
NOP
PCG
NOP
Command
Address
Bank a
COL n
tDQSS
(NOM)
tWR
DQS
DQ
DIN
n
DIN
n+1
DM
Don’ t care
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ealier.
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Figure30 : Write to Precharge (Odd number of data Interrupting)
T0
T1
T2
T3
T4
T5
/CLK
CLK
WRITE
NOP
NOP
NOP
PCG
NOP
Command
Address
Bank a
COL n
tDQSS
(NOM)
tWR
DQS
DQ
DIN
n
DM
Don’ t care
Notes:
1. Din n = Data-In from Column n.
2. tWR is referenced from the first positive CK edge after the last data-in pair.
3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command
could be applied ealier.
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Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The banks will be available
for subsequent row access some specified time (tRP) after the Precharge command issued.
Input A10 determines whether one or all banks are to be precharged. In the case where only one bank is to be precharged (A10=Low),
inputs BA0,BA1 select the banks.
When all banks are to be precharged (A10=High), inputs BA0,BA1 are treated as a “Don’t Care”. Once a bank has been precharged, it is in
the idle state and must be actived prior to any Read or Write commands being issued to that bank.
Figure31 : Precharge command
CLK
/CLK
CKE
/CS
/RAS
/CAS
Notes :
1. BA : Bank address
/WE
A10
BA
BA0, BA1
Don’t care
Mode Register
The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selection of a burst length
( 2, 4, 8), a cas latency(2, 3), a burst type. The mode register set must be done before any activate command after the power up
sequence.
Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command.
Figure32 : Mode Resister Set
0
1
2
3
4
5
7
8
9
10
6
/CLK
CLK
Mode
Resister
Set
Precharge
All Bank
Command
(any)
CMD
tCK
tRP
2 CK min
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Auto refresh
The Auto refresh command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a refresh
is required. The refresh addressing is generated by the internal refresh controller. The Mobile DDR requires AUTO REFRESH commands at an
average periodic interval of tREFI. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREFI.
Figure33 : Auto refresh
T0
T1
T2
T3
T4
Ta0
Tb0
Ta2
Tb0
/CLK
CLK
tCK
tCH
tCL
tIS
tIH
CKE
VALID
NOP
VALID
NOP
tIS
tIH
NOP
PCG
NOP
AREF
NOP
AREF
NOP
ACT
Command
A0~A9, A11-A13
RA
RA
All Banks
A10
BA0, BA1
One Bank
BA
BA
DQS, DQ, DM
tRP
tRFC
tRFC
Don’t care
Self refresh
This state retains data in the Mobile DDR, even if the rest of the system is powered down (even without external clocking). Note refresh
interval timing while in Self Refresh mode is scheduled internally in the Mobile DDR and may vary and may not meet tREFI time. "Don't
Care" except CKE, which must remain low. An internal refresh cycle is scheduled on Self Refresh entry. The procedure for exiting Self
Refresh mode requires a series of commands. First clock must be stable before CKE going high. NOP commands should be issued for the
duration of the refresh exit time (tXSR), because time is required for the completion of any internal refresh in progress. The use of SELF
REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode.
Figure34 : Self refresh
T0
T1
Ta0
Ta1
Tb0
/CLK
CLK
tIS
tIH
tIS
tIS
CKE
tIS
tIH
NOP
AREF
NOP
VALID
VALID
Command
Address
DQS, DQ, DM
tRP
Self-refresh mode entry
tXSR
Don’t care
Self-refresh mode exit
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Power down
Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power
down occurs when all banks are idle, it is Precharge Power Down. If Power down occurs when one or more banks are Active, it is referred to
as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. The
power down state is exited by setting CKE high while issuing a Device Deselect or NOP command. A valid command can be issued after tXP.
Figure35 : Power down (Active or Precharge)
T0
T1
T2
Ta0
Ta1
Tb0
/CLK
CLK
tCK
tCH
tCL
tXP
tIS
tIS
tIH
tIS
CKE
tIH
Command
VALID
NOP
NOP
VALID
VALID
tIS
tIH
Address
VALID
DQS, DQ, DM
Must not exceed refresh device limits
Power-down mode entry Power-down mode exit
Don t care
’
Deep Power down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile DDR are stopped
and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP
POWER-DOWN COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus prior to
entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the
clock is stable and NOP command must be maintained for at least 200 us.
Figure36 : Deep Power down
T0
T1
T2
Ta0
Ta1
Ta2
Tb0
/CLK
CLK
T=200us
tIS
tCKE
CKE
Command
NOP
DPD
NOP
NOP
VALID
VALID
Address
DQS, DQ, DM
Deep Power -down mode
entry
Deep Power-down mode
exit
Don’t care
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Clock Stop Mode
Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption during idle periods of
the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
• The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion,
including any data-out during read bursts; the number of required clock pulses per access command depends on the device's AC timing
parameters and the clock frequency;
• The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;
• CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with CK held
LOW and /CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command have to be issued for at least one clock
cycle before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics.
Figure37 illustrates the clock stop mode:
• Initially the device is in clock stop mode;
• The clock is restarted with the rising edge of T0 and a NOP on the command inputs;
• With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this
access command has completed;
• Tn is the last clock pulse required by the access command latched with T1.
• The timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required by this
command and the clock is then stopped.
Figure 37 : Clock Stop Mode
T0
T1
T2
Tn
/CLK
CLK
High
CKE
Timing Condition
NOP
CMD
NOP
NOP
NOP
CMD
ADD
Valide
(High – Z)
DQ,DQS
Don’t Care
Vail
Command
Enter Clock
Stop Mode
Clock
stopped
Exit Clock
Stop Mode
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Ordering Information – VDD = 1.8V
Commercial Range: (0oC to +70oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
128Mx16
208
166
208
166
4.8
6
IS43LR16128B-5BL
IS43LR16128B-6BL
IS43LR32640B-5BL
IS43LR32640B-6BL
60-ball BGA, Lead-free
60-ball BGA, Lead-free
90-ball BGA, Lead-free
90-ball BGA, Lead-free
64Mx32
4.8
6
Industrial Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
128Mx16
208
166
208
166
4.8
6
IS43LR16128B-5BLI
IS43LR16128B-6BLI
IS43LR32640B-5BLI
IS43LR32640B-6BLI
60-ball BGA, Lead-free
60-ball BGA, Lead-free
90-ball BGA, Lead-free
90-ball BGA, Lead-free
64Mx32
4.8
6
Automotive A1: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
128Mx16
208
166
208
166
4.8
6
IS46LR16128B-5BLA1
IS46LR16128B-6BLA1
IS46LR32640B-5BLA1
IS46LR32640B-6BLA1
60-ball BGA, Lead-free
60-ball BGA, Lead-free
90-ball BGA, Lead-free
90-ball BGA, Lead-free
64Mx32
4.8
6
Automotive A2: (-40oC to +105oC)
Configuration
Frequency
(MHz)
Speed
(ns)
Order Part No.
Package
128Mx16
208
166
208
166
4.8
6
IS46LR16128B-5BLA2
IS46LR16128B-6BLA2
IS46LR32640B-5BLA2
IS46LR32640B-6BLA2
60-ball BGA, Lead-free
60-ball BGA, Lead-free
90-ball BGA, Lead-free
90-ball BGA, Lead-free
64Mx32
4.8
6
Note:
1. The -6 speed option supports -75 timing specifications.
2. The -5 speed option supports operation at 200MHz. Refer to timing specifications.
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