IS46R16160B-6TLA [ISSI]
Synchronous DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66;
| 型号： | IS46R16160B-6TLA |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66 动态存储器 光电二极管 |
| 文件： | 总38页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS46R83200B
IS46R16160B
32Mx8, 16Mx16
256Mb Synchronous DRAM
PRELIMINARY INFORMATION
MAY 2008
FEATURES:
•ꢀ Vd d =Vd d q = 2.5V+0.2V (-6, -75)
•ꢀ Double data rate architecture ; two data transfers
per clock cycle.
•ꢀ Bidirectional , data strobe (DQS) is transmitted/
received with data
•ꢀ Differential clock input (CLK and /CLK)
DESCRIPTION:
IS46R83200B is a 4-bank x 8,388,608-word x8bit,
IS46R16160B is a 4-bank x 4,194,304-word x 16bit
double data rate synchronous DRAM , with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The device
achieves very high speed clock rate up to 166 MHz.
•ꢀ DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
•ꢀ Commands entered on each positive CLK edge;
•ꢀ Data and data mask referenced to both edges of
KEY TIMING PARAMETERS
Parameter
-6
-75
Unit
DQS
Clk Cycle Time
•ꢀ 4 bank operation controlled by BA0 , BA1
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
6
6
7.5
7.5
7.5
7.5
ns
ns
ns
(Bank Address)
•ꢀ /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;
Burst length -2 / 4 / 8 (programmable)
Burst type -Sequential / Interleave (program-
mable)
Clk Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
166
166
143
143
143
143
MHz
MHz
MHz
•ꢀ Auto precharge/ All bank precharge controlled
by A10
Access Time from Clock
CAS Latency = 3
+0.70
+0.70
+0.75
+0.75
+0.75
+0.75
ns
ns
ns
•ꢀ 8192 refresh cycles / 64ms (4 banks concurrent
CAS Latency = 2.5
CAS Latency = 2
refresh)
•ꢀ Auto refresh and Self refresh
•ꢀ Row address A0-12 / Column address A0-9(x8)/
A0-8(x16)
•ꢀ SSTL_2 Interface
•ꢀ Package 400-mil, 66-pin Thin Small Outline
Package (TSOP II) with 0.65mm lead pitch
•ꢀ Temperature Range:
Automotive Grade, A: (0oC to +70oC)
Automotive Grade, A1: (-40oC to +85oC)
ADDRESS TABLE
Parameter
32M x 8
16M x 16
Configuration
8M x 8 x 4 banks
BA0, BA1
A10/AP
4M x 16 x 4 banks
BA0, BA1
A10/AP
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
A0 – A12
A0 – A12
A0 – A9
A0 – A8
8192 / 64ms
8192 / 64ms
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Pin Assignment (Top View) 66-pin TSOP
CLK, /CLK
CKE
: Master Clock
: Clock Enable
A0-12
BA0,1
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
/CS
/RAS
/CAS
/WE
: Chip Select
V
V
DD
: Row Address Strobe
: Column Address Strobe
: Write Enable
DDQ
Vss
Vss
Q
DQ0-15
DQ0-7
: Data I/O (x16)
: Data I/O (x8)
UDM, LDM
DM
: Write Mask (x16)
: Write Mask (x8)
UDQS, LDQS : Data Strobe (x16)
DQS : Data Strobe (x8)
2
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CLK, /CLK
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
Input
/CS
Input
Input
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
/RAS, /CAS, /WE
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
A0-12
Input
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
BA0,1
DQ0-7 (x8),
Input / Output
Input / Output
Data Input/Output: Data bus
DQ0-15 (x16),
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
DQS (x8)
UDQS, LDQS (x16)
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
DM (x8)
Input
UDM, LDM (x16)
V
DD, VSS
Power Supply
Power Supply
Input
Power Supply for the memory array and peripheral circuitry.
VDDQ,
VDDQ, and
V
VSSQ
SSQ are supplied to the Output Buffers only.
Vref
SSTL_2 reference voltage.
Integrated Silicon Solution, Inc.
3
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
DQ0 - 7
DQS
BLOCK DIAGRAM x8
DLL
I/O B uffer
Buffer
DQS
Memory
Array
Memory
Memory
Array
Memory
Array
Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register
Control C ircuitry
Address Buffer
Control Signal B uffer
Cl ock B uffer
CLK /CLK
/CS /RAS /CAS /WE D M
A0-12
BA 0,1
CKE
4
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
DQ 0 - 15
UDQS, LD QS
DQ S Buffer
BLOCK DIAGRAM x16
DLL
I/O B uffer
Memory
Array
Memory
Memory
Array
Memory
Array
Array
Bank #0
Ba nk #1
Ba nk #2
Ba nk #3
Mode Re gister
Control C ircu itry
Address B uffer
Control Signal B uffer
Cl ock B uffer
CLK /CLK
/CS /RAS /CAS /WE UDM ,
LD M
A0-12
BA 0,1
CKE
Integrated Silicon Solution, Inc.
5
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
BASIC FUNCTIONS
ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
CKE
A10
Command
define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
6
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
COMMAND TRUTH TABLE
CKE CKE
A10 A0-9,
/AP 11-12
note
COMMAND
MNEMONIC
/CS
/RAS /CAS /WE BA0,1
n-1
n
DESEL
NOP
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
Deselect
H
No Operation
Row Address Entry &
Bank Activate
ACT
H
H
L
L
H
H
V
V
V
PRE
H
H
H
H
L
L
L
L
H
H
L
L
V
X
L
X
X
Single Bank Precharge
Precharge All Banks
PREA
H
Column Address Entry
& Write
WRITE
H
H
L
H
L
L
V
L
V
Column Address Entry
& Write with
WRITEA
READ
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
V
V
V
H
L
V
V
V
Auto-Precharge
Column Address Entry
& Read
H
H
Column Address Entry
& Read with
READA
H
Auto-Precharge
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
X
H
H
L
L
L
X
H
H
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Self-Refresh Entry
H
H
H
H
Self-Refresh Exit
REFSX
L
1
2
Burst Terminate
TERM
MRS
H
H
Mode Register Set
L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the
op-code to be written to the selected Mode Register.
Integrated Silicon Solution, Inc.
7
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
Command
DESEL
Action
NOP
Notes
IDLE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
BA
TERM
ILLEGAL
ILLEGAL
Bank Active, Latch RA
NOP
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
H
H
L
L
PRE / PREA
REFA
4
5
L
H
X
Auto-Refresh
Op-Code, Mode-
Add
X
L
L
L
L
MRS
Mode Register Set
5
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
DESEL
NOP
NOP
NOP
X
BA
TERM
ILLEGAL
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
WRITE / WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
ACT
Bank Active / ILLEGAL
2
BA, A10
PRE / PREA
REFA
Precharge / Precharge All
ILLEGAL
H
X
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
READ(Auto-
Precharge
Disabled)
X
BA
TERM
Terminate Burst
Terminate Burst, Latch CA, Begin
New Read, Determine Auto-
Precharge
L
H
L
H
BA, CA, A10
READ / READA
3
2
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, A10
BA, RA
WRITE / WRITEA ILLEGAL
ACT
Bank Active / ILLEGAL
BA, A10
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
H
X
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
8
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
WRITE(Auto-
Precharge
Disabled)
X
BA
TERM
ILLEGAL
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge
Bank Active / ILLEGAL
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
3
WRITE / WRITEA
3
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
H
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
X
H
X
H
X
H
DESEL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
Auto-Precharge
X
NOP
L
L
L
L
H
H
H
L
H
L
L
H
L
H
L
BA
TERM
READ / READA
WRITE / WRITEA ILLEGAL
ACT
BA, CA, A10
BA, CA, A10
BA, RA
ILLEGAL
H
Bank Active / ILLEGAL
2
2
L
L
L
L
H
L
L
BA, A10
PRE / PREA
REFA
Precharge / ILLEGAL
ILLEGAL
H
X
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
X
H
X
H
X
H
DESEL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
Auto-Precharge
X
NOP
L
L
L
L
H
H
H
L
H
L
L
H
L
H
L
BA
TERM
READ / READA
WRITE / WRITEA ILLEGAL
ACT
BA, CA, A10
BA, CA, A10
BA, RA
ILLEGAL
H
Bank Active / ILLEGAL
2
2
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA
REFA
Precharge / ILLEGAL
ILLEGAL
H
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
Integrated Silicon Solution, Inc.
9
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
DESEL
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
ILLEGAL
ILLEGAL
PRE-
CHARGING
X
NOP
BA
TERM
READ / WRITE
ACT
2
2
2
4
BA, CA, A10
BA, RA
BA, A10
L
PRE / PREA
REFA
NOP (Idle after tRP)
ILLEGAL
L
H
X
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
DESEL
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL
ILLEGAL
ILLEGAL
ROW
X
NOP
ACTIVATING
BA
TERM
READ / WRITE
ACT
2
2
2
2
BA, CA, A10
BA, RA
BA, A10
L
PRE / PREA
REFA
ILLEGAL
L
H
X
ILLEGAL
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
DESEL
NOP
WRITE RE-
COVERING
X
NOP
NOP
BA
TERM
READ / WRITE
ACT
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
2
BA, CA, A10
BA, RA
BA, A10
L
PRE / PREA
REFA
L
H
X
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
10
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
REFRESHING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
DESEL
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
X
NOP
BA
TERM
READ / WRITE
ACT
BA, CA, A10
BA, RA
BA, A10
L
PRE / PREA
REFA
ILLEGAL
L
H
X
ILLEGAL
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
DESEL
NOP (Row Active after tRSC)
NOP (Row Active after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
MODE
REGISTER
SETTING
X
NOP
BA
TERM
READ / WRITE
ACT
BA, CA, A10
BA, RA
BA, A10
L
PRE / PREA
REFA
ILLEGAL
L
H
X
ILLEGAL
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Integrated Silicon Solution, Inc.
11
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
FUNCTION TRUTH TABLE for CKE
Current State CKE n-1 CKE n
/CS
X
H
L
/RAS
X
X
H
H
H
L
/CAS
X
X
H
H
L
/WE Address
Action
Notes
H
L
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
L
H
L
L
L
L
L
L
X
H
L
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
1
1
1
1
1
1
1
SELF-
REFRESHING
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
X
X
X
X
X
X
L
ILLEGAL
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
2
2
2
2
2
2
2
2
ALL BANKS
IDLE
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
Enter Power Down
L
ILLEGAL
L
X
X
X
X
X
X
X
ILLEGAL
L
X
X
X
X
X
X
ILLEGAL
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle
Exit CLK Suspend at Next Cycle
Maintain CLK Suspend
ANY STATE
other than listed
above
3
3
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
12
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
PRE
CHARGE
ALL
SELF
REFRESH
POWER
ON
PREA
REFS
MRS
MRS
REFSX
MODE
REGISTER
SET
AUTO
REFRESH
REFA
IDLE
ACT
CKEL
CKEH
Active
Power
Down
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
BURST
STOP
WRITE
READ
READ
WRITE
WRITEA
READA
READ
WRITE
READ
TERM
WRITEA
READA
READA
PRE
WRITEA
READA
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
Integrated Silicon Solution, Inc.
13
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
CLK
MODE REGISTER
/CLK
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when all banks are in idle state. After tMRD from a
MRS command, the DDR SDRAM is ready for new command.
/CS
/RAS
/CAS
/WE
BA0
BA1
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
LTMODE
BL
0
0
0
0
0
0
DR
0
BT
V
A12-A0
BL
BT=0
BT=1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
2
4
8
R
R
R
R
R
2
4
8
R
R
R
R
CL
/CAS Latency
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
Burst
Length
Latency
Mode
3
R
R
2.5
R
0
1
Sequential
Interleaved
Burst Type
0
NO
YES
DLL Reset
1
R: Reserved for Future Use
14
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks are
in idle state. After tMRD from a EMRS command, the DDR SDRAM is
ready for new command.
CLK
/CLK
/CS
/RAS
/CAS
/WE
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA0
DS DD
0
1
0
0
0
0
0
0
0
0
0
0
0
BA1
V
A12-A0
0
1
DLL Enable
DLL Disable
DLL Disable
Drive
Strength
0
1
Normal
Weak
Integrated Silicon Solution, Inc.
15
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
/CLK
CLK
Read
Y
Write
Y
Command
Address
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Burst
Length
Burst
Length
CL= 2
BL= 4
/CAS
Latency
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
16
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
Parameter
Supply Voltage
Conditions
Ratings
-0.5 ~ 3.7
-0.5 ~ 3.7
-0.5 ~ VDD+0.5
-0.5 ~ VDDQ +0.5
50
Unit
V
with respect to Vss
Supply Voltage for Output
Input Voltage
with respect to Vss
Q
V
with respect to Vss
V
VO
Output Voltage
with respect to Vss
Q
V
IO
Output Current
mA
mW
oC
oC
oC
Ta = 25 oC
Pd
Power Dissipation
Operating Temperature
1500
Topr
0to+70
A
-40 to +85
-65 ~ 150
A1
Tstg
Storage Temperature
OPERATING CONDITIONS
DC
(Ta=0 ~ 70oC, unless otherwise noted)
Limits
Notes
Parameter
Unit
Min.
Typ.
Max.
2.7
Supply Voltage
-6, -75
-6, -75
2.3
2.5
V
V
2.3
2.5
2.7
Supply Voltage for Output
Vref+0.15
-0.3
Vdd+0.3
Vref-0.15
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
V
V
-2
2
5
Any input 0V<VIN<VDD
(All other pins not under test = 0V)
Output Leakage Current:DQ are
disabled:0V<Vout<VddQ
Output Levels:
uA
-5
uA
V
2.4
Output high Voltage (Iout=-4mA)
Output Low Voltage(Iout=4mA)
0.4
V
CAPACITANCE
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V Vss = VssQ = 0V, unless otherwise noted)
Limits
Delta
Cap.(Max.)
Symbol
Parameter
Test Condition
Unit Notes
Min. Max.
1.3 2.5
1.3 2.5
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
VI=1.25v
pF
pF
pF
pF
0.75
f=100MHz
VI=25mVrms
1.3
2
2.5
4
0.25
1.3
I/O Capacitance, I/O, DQS, DM pin
Integrated Silicon Solution, Inc.
17
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
AVERAGE SUPPLY CURRENT fromVdd
(Vdd = Vd dQ = 2.5V + 0.2V , Vs s = Vs sQ = 0V, Output Open, unless otherwise noted)
Limits(Max.)
Parameter/Te st Conditions
Notes
Symbol
Unit
-6
-75
OPER ATI NG CURRENT : One Bank; Ac tive-Read-Precharge;B urst = 2;
IDD1 tRC = t RC MI N; t CK = t CK MI N; IOUT = 0mA; Address andcontrol
inputs changingonce per clock cycle
165
150
PR ECHARGE POWE R-DOWN STANDB Y CURRENT : All banks idle;
IDD2 P
25
55
45
90
20
50
40
75
<
power-down mode; CKE VI L (M AX ); t CK = t CK MI N
ID LE STANDB Y CURRENT : /CS > VI H (M IN ); All banks idle;
IDD2 N CKE > VI H (M IN ); t CK = t CK MI N; Address andother control inputs
changingonce per clock cycle
ACTIVE POWER DOWN STANDB Y CURRENT : One bankactive;power
IDD3 P
<
down mode ;C KE VI L( MA X) ;t CK = t CK MI N
AC TI VE STANDB Y CURRE NT : /CS > VI H (M IN ); CKE > VI H (M IN );
One bank; Ac tive-Precharge; t RC = t RA S MAX; t CK = t CK MI N;
DQ,DM andDQS inputs changingtwice per clock cycle; address andother
control inputs changingonce per clock cycle
mA
IDD3 N
OPER ATI NG CURRENT : Burst =2; Read ; Continuous burst;A ll banks
IDD4 R active; Address andcontrol inputs changingonce per clock cycle;t CK =
tCK MI N; IOUT = 0 mA
250
250
210
210
OPERATI NG CURRENT : Burst =2; Write ; Continuous burst;A ll banks
IDD4 W active; Address andcontrol inputs changingonce per clock cycle;t CK =
tCK MI N; DQ andDQS inputs changingtwice per clock cycle
160
5
150
5
IDD5 AUTO REFRESH CURRENT: t RC = t RFC (M IN )
IDD6 SELF REFRESH CURRENT : CKE < 0.2V
18
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
AC TIMING REQUIREMENTS
-6
-75
Symbol
tAC
AC Characteristics Parameter
Unit
Notes
Min.
Max
Min.
Max
DQ Output access time from CLK//CLK
-0.70
+0.70
-0.75
+0.75
ns
ns
tDQSCK DQS Output access time from CLK//CLK
-0.60
0.45
0.45
6
+0.60
0.55
0.55
12
-0.75
0.45
0.45
7.5
+0.75
0.55
0.55
12
tCH
tCL
CLK High level width
CLK Low level width
tCK
tCK
ns
CL=3.0
CL=2.5
CL=2.0
tCK
CLK cycle time
6
12
7.5
12
ns
7.5
12
7.5
12
ns
tDS
Input Setup time (DQ,DM)
Input Hold time(DQ,DM)
0.45
0.45
2.2
0.5
ns
tDH
0.5
ns
tIPW Control & address input pulse width (for each input)
tDIPW DQ and DM input pulse width (for each input)
2.2
ns
1.75
1.75
ns
tHZ
tLZ
Data-out-high impedance time from CLK//CLK
Data-out-low impedance time from CLK//CLK
+0.70
+0.70
0.45
+0.75
+0.75
0.5
ns
14
14
-0.70
-0.75
ns
tDQSQ DQ Valid data delay time from DQS
ns
tCLmin or
tCHmin
tCLmin or
tCHmin
tHP
Clock half period
ns
ns
20
tQH
DQ output hold time from DQS (per access)
tHP-tQHS
tHP-tQHS
tQHS Data hold skew factor (for DQS & associated DQ signals)
tDQSS Write command to first DQS latching transition
tDQSH DQS input High level width
0.55
1.25
0.75
1.25
0.75
0.35
0.35
0.2
0.2
2
0.75
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
tDQSL DQS input Low level width
tDSS DQS falling edge to CLK setup time
tDSH DQS falling edge hold time fromCLK
tMRD Mode Register Set command cycle time
tWPRES Write preamble setup time
0
0
16
15
tWPST Write postamble
0.4
0.25
0.75
0.75
0.4
0.9
0.6
0.4
0.25
0.9
0.9
0.4
0.9
0.6
tCK
tCK
ns
tWPRE Write preamble
tIS
Input Setup time (address and control)
Input Hold time (address and control)
19
19
tIH
ns
tRPST Read postamble
tRPRE Read preamble
0.6
1.1
0.6
1.1
tCK
tCK
Integrated Silicon Solution, Inc.
19
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
AC TIMING REQUIREMENTS(Continues)
-6
-75
Symbol
AC Characteristics Parameter
Unit
Notes
Min.
42
Max
Min.
45
Max
tRAS Row Active time
120,000
120,000
ns
ns
tRC
Row Cycle time(operation)
60
65
75
20
20
15
15
tRFC Auto Ref. to Active/Auto Ref. command period
tRCD Row to Column Delay
72
ns
18
ns
tRP
Row Precharge time
18
ns
tRRD Act to Act Delay time
12
ns
tWR Write Recovery time
15
ns
tDAL Auto Precharge write recovery + precharge time
tWTR Internal Write to Read Command Delay
tXSNR Exit Self Ref. to non-Read command
tXSRD Exit Self Ref. to -Read command
tXPNR Exit Power down to command
tXPRD Exit Power down to -Read command
tREFI Average Periodic Refresh interval
tWR+tRP
tWR+tRP
ns
1
75
200
1
1
75
200
1
tCK
ns
tCK
tCK
tCK
µs
1
1
18
17
7.8
7.8
Output Load Condition
VREF
VREF
DQS
V
TT=VREF
DQ
50W
VOUT
Zo=50W
V
REF
30pF
Output Timing
Measurement
Reference Point
20
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the
range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively
switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +
2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be
set equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level
of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) =
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE< 0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. Min (tCL,tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device.
Timing patterns:
tCK=min,tRRD=2*tCK,BL=4,tRCD=3*tCK,Read with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R3 A0 N A1 R0 – repeat the same timing with random address changing
*100% of data changing at every burst
Legend: A=Activate,R=Read,P=Precharge,N=NOP
Integrated Silicon Solution, Inc.
21
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
Valid Data
tRPST
tIH
Cmd &
Add.
VREF
tDQSCK
tQH
tRPRE
DQS
DQ
tDQSQ
tAC
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
tWPST
tDSS
tWPRES
DQS
tDQSL
tDS
tDQSH
tDH
tWPRE
DQ
Write Operation / tDQSS=min.
/CLK
CLK
tDSH
tDQSS
tWPST
tWPRES
DQS
tDQSL
tDS
tDQSH
tDH
tWPRE
DQ
22
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A0-12. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
tRCmin
ACT
ACT READ
PRE
ACT
Xb
Command
A0-9,11,12
tRP
tRRD
tRAS
BL/2
Xa
Xb
tRCD
Y
0
Xa
00
Xb
1
Xb
01
A10
BA0,1
01
00
DQS
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
Integrated Silicon Solution, Inc.
23
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A0-9(x8)/A0-8(x16), and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks.
When A10 is high at a READ command, the auto-precharge (READA) is performed. Any
command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is
complete. The internal precharge starts at BL/2 after READA. The next ACT command can be
issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11,12
A10
ACT
Xa
READ ACT
READ PRE
Y
tRCD
Y
0
Xb
Xb
Xa
0
0
00
00
10
10
00
BA0,1
DQS
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8
Burst Length
/CAS latency
24
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
READ with Auto-Precharge (BL=8, CL=2,2.5,3.0)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
BL/2 + tRP
Command
ACT
READ
tRCD
tRP
BL/2
Xa
Xa
Y
1
A0-9,11,12
A10
00
00
BA0,1
DQS
CL=2
Qa0 Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7
DQ
DQS
CL=2.5
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DQ
DQS
CL=3.0
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DQ
Internal Precharge Start Timing
Integrated Silicon Solution, Inc.
25
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A0-9(x8)/A0-8(x16), and the address
sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous input data by
interleaving the multiple banks. From the last data to the PRE command, the write recovery time
(tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
ACT
Xa
WRITE ACT
WRITE
PRE
PRE
Command
A0-9,11,12
tRCD
tRCD
Ya
0
Xb
Xb
Yb
0
Xa
Xa
0
0
A10
BA0,1
10
00
00
10
10
00
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
26
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
WRITE with Auto-Precharge (BL=8)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
ACT
Xa
WRITE
ACT
Xb
Command
A0-9,11,12
A10
tDAL
tRC
Y
1
Xa
Xb
00
00
00
BA0,1
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Integrated Silicon Solution, Inc.
27
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11,12
A10
READ READ
READ
Yk
READ
Yl
Yi
0
Yj
0
0
0
00
00
10
01
BA0,1
DQS
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
DQ
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
PRE
Command
DQS
READ
CL=2.0
Q0 Q1 Q2 Q3
DQ
Command
DQS
READ PRE
Q0 Q1
DQ
28
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
DQS
READ
PRE
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Command
DQS
READ
PRE
CL=2.5
Q0 Q1 Q2 Q3
DQ
Command
READ PRE
DQS
DQ
Q0 Q1
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
PRE
Command
DQS
READ
CL=3.0
Q0 Q1 Q2 Q3
DQ
Command
DQS
READ PRE
Q0 Q1
DQ
Integrated Silicon Solution, Inc.
29
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
READ
TERM
Command
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
TERM
READ
READ
Command
DQS
CL=2.0
Q0 Q1 Q2 Q3
DQ
TERM
Command
DQS
DQ
Q0 Q1
TERM
READ
READ
READ
Command
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
TERM
Command
DQS
CL=2.5
Q0 Q1 Q2 Q3
DQ
TERM
Command
DQS
DQ
Q0 Q1
30
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Read Interrupted by TERM (BL=8)
/CLK
CLK
READ
TERM
Command
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
TERM
READ
Command
DQS
CL=3.0
Q0 Q1 Q2 Q3
DQ
READ TERM
Command
DQS
DQ
Q0 Q1
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
READ
READ
TERM
WRITE
DQS
DQ
CL=2.0
CL=2.5
CL=3.0
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3
Command
TERM
TERM
WRITE
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3 D4 D5
Command
READ
WRITE
DQS
DQ
D0 D1 D2 D3 D4 D5
Q0 Q1 Q2 Q3
Integrated Silicon Solution, Inc.
31
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
WRITE WRITE
WRITE
Yk
WRITE
Yl
Command
A0-9,11,12
Yi
Yj
0
0
0
0
A10
BA0,1
00
00
10
00
DQS
DQ
Dai1 Daj0 Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
Dai0
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The
input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first
positive edge after the last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
READ
WRITE
Command
A0-9,11,12
Yi
0
Yj
0
A10
BA0,1
00
00
DM
tWTR
QS
Dai0 Dai1
Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
DQ
32
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column
access is allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
WRITE
Yi
PRE
Command
A0-9,11,12
A10
0
00
00
BA0,1
DM
tWR
QS
Dai0 Dai1
DQ
Integrated Silicon Solution, Inc.
33
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[Initialize and Mode Register sets]
Initialize and MRS
/CLK
CLK
CKE
Command
A0-12
A10
NOP
PRE
1
EMRS
Code
MRS
Code
PRE
1
AR
AR
MRS
ACT
Xa
Code
1 0
Code
0 0
Code
0 0
Xa
Xa
BA0,1
DQS
DQ
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
Extended Mode
Register Set
Mode Register Set,
Reset DLL
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh
256Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing
an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum
tRFC . Any command must not be supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-12
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
34
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-
refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are
disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the
self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
X
X
Y
Y
A0-12
BA0,1
tXSRD
tXSNR
Self Refresh Exit
Integrated Silicon Solution, Inc.
35
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-
refresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time
is NOT required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power Down
CKE
Command
PRE NOP
ACT NOP
NOP Valid
NOP Valid
tXPNR/tXPRD
Active Power Down
CKE
Command
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM
to write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
DM
WRITE
READ
Don't Care
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6
D0 D1
D3 D4 D5 D6
D7
masked by DM=H
36
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
ORDERING INFORMATION - Vd d = 2.5V
Automotive Grade, A: 0°C to +70°C
Frequency Speed (ns)
Order Part No.
Organization
32Mx8
Package
166 MHz
166 MHz
133 MHz
133 MHz
6
IS46R83200B-6TLA
IS46R16160B-6TLA
IS46R83200B-75TLA
IS46R16160B-75TLA
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
6
16Mx16
32Mx8
7.5
7.5
16Mx16
Automotive Grade, A1: -40°C to +85°C
Frequency Speed (ns)
Order Part No.
Organization
32Mx8
Package
166 MHz
166 MHz
133 MHz
133 MHz
6
IS46R83200B-6TLA1
IS46R16160B-6TLA1
IS46R83200B-75TLA1
IS46R16160B-75TLA1
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
66-pin TSOP-II, Lead-free
6
16Mx16
32Mx8
7.5
7.5
16Mx16
Please contact Product Manager for leaded part support.
Integrated Silicon Solution, Inc.
37
Rev. 00A
05/14/08
IS46R83200B
IS46R16160B
Plastic TSOP 66-pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
E
E1
package
.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Symbol Min
Max
Min
Max
Ref. Std.
No. Leads (N)
66
A
A1
A2
b
C
D
E1
E
e
—
1.20
—
0.047
0.05 0.15
—
0.002 0.006
—
—
—
0.24 0.40
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.65 BSC
0.009 0.016
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.026 BSC
L
0.40 0.60
0.016 0.024
L1
ZD
α
—
—
—
—
0.71 REF
0° 8°
0.028 REF
0°
8°
38
Integrated Silicon Solution, Inc.
Rev. 00A
05/14/08
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