IS49NLC96400A-33WBL [ISSI]
DDR DRAM, 64MX9, CMOS, PBGA144, WBGA-144;
| 型号： | IS49NLC96400A-33WBL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | DDR DRAM, 64MX9, CMOS, PBGA144, WBGA-144 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总36页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
64Mbx9, 32Mbx18, 16Mbx36
Common I/O RLDRAM 2 Memory
FEBURARY 2017
FEATURES
533MHz DDR operation (1.067 Gb/s/pin data rate)
38.4Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each 32ms)
8 internal banks
Non-multiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of WRITE
data; DM is sampled on both edges of DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C )
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball WBGA (lead-free)
Configuration:
64Mx9
32Mx18
16Mx36
Clock Cycle Timing:
Speed Grade
-18
15
-25E
15
-25
20
-33
20
Unit
ns
tRC
tCK
1.875
2.5
2.5
3.3
ns
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for
products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com –
Rev.A2, 02/09/2017
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
RLDRAM is a registered trademark of Micron Technology, Inc.
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Rev.A2, 02/09/2017
2
IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
1 Package Ball out and Description
1.1 576Mb (64Mx9) Common I/O BGA Ball-out (Top View)
12
TCK
VDD
VTT
1
2
3
4
5
6
7
8
9
10
11
VREF
VSS
VEXT
VSS
VSS
VEXT
TMS
A
B
C
D
E
F
VDD
DNU3
DNU3
DNU3
DNU3
DNU3
A6
DNU3
DNU3
DNU3
DNU3
DNU3
A7
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ0
DQ1
QK0#
DQ2
DQ3
A2
DNU3
DNU3
QK0
DNU3
DNU3
A1
VTT
A221
A21
A5
VSS
A20
QVLD
A0
A8
G
H
J
BA2
NF2
DK
A9
NF2
VSS
VSS
VSS
VSS
A4
A3
VDD
VDD
VDD
VDD
BA0
BA1
A14
CK
DK#
CS#
A16
VDD
VDD
VDD
VDD
CK#
A13
A10
K
L
REF#
WE#
VSS
VSS
VSS
VSS
A17
VDD
VDD
A12
A11
M
A18
A15
VSS
DNU3
DNU3
DNU3
DNU3
DNU3
ZQ
DNU3
DNU3
DNU3
DNU3
DNU3
VEXT
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ4
DQ5
DQ6
DQ7
DQ8
VEXT
DNU3
DNU3
DNU3
DNU3
DNU3
TD0
A19
DM
VSS
VTT
VDD
TDI
N
P
R
T
VTT
VDD
VREF
U
V
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND.
3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if
ODT is enabled, these pins are High-Z.
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Rev.A2, 02/09/2017
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
1.2 576Mb (32Mx18) Common I/O BGA Ball-out (Top View)
12
TCK
VDD
VTT
1
2
3
4
5
6
7
8
9
10
11
VREF
VSS
VEXT
VSS
VSS
VEXT
TMS
A
B
C
D
E
F
VDD
VTT
A221
A212
A5
DNU4
DNU4
DNU4
DNU4
DNU4
A6
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ0
DQ1
QK0#
DQ2
DQ3
A2
DNU4
DNU4
QK0
DNU4
DNU4
A1
VSS
A20
QVLD
A0
A8
G
H
J
BA2
NF3
DK
A9
NF3
VSS
VSS
VSS
VSS
A4
A3
VDD
VDD
VSS
VDD
VDD
VDD
BA0
BA1
A14
CK
DK#
CS#
A16
VDD
VDD
VDD
CK#
A13
A10
K
L
REF#
WE#
VSS
VSS
VSS
A17
VDD
VDD
A12
A11
M
A18
A15
VSS
DNU4
DNU4
QK1
DNU4
DNU4
ZQ
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
DNU4
DNU4
DNU4
DNU4
DNU4
TD0
A19
DM
VSS
VTT
VDD
TDI
N
P
R
T
VTT
VDD
VREF
U
V
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be
connected to GND.
3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if
ODT is enabled, these pins are High-Z .
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Rev.A2, 02/09/2017
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
1.3 576Mb (16Mx36) Common I/O BGA Ball-out (Top View)
12
TCK
VDD
VTT
1
2
3
4
5
6
7
8
9
10
11
VREF
VSS
VEXT
VSS
VSS
VEXT
TMS
A
B
C
D
E
F
VDD
VTT
A221
A212
A5
DQ8
DQ10
DQ12
DQ14
DQ16
A6
DQ9
DQ11
DQ13
DQ15
DQ17
A7
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ1
DQ3
QK0#
DQ5
DQ7
A2
DQ0
DQ2
QK0
DQ4
DQ6
A1
VSS
A202
QVLD
A0
A8
G
H
J
BA2
DK0
DK1
REF#
WE#
A9
VSS
VSS
VSS
VSS
A4
A3
DK0#
DK1#
CS#
VDD
VDD
VDD
VDD
BA0
BA1
A14
A11
CK
VDD
VDD
VDD
VDD
CK#
A13
A10
K
L
VSS
VSS
VSS
VSS
A16
A17
VDD
VDD
A12
M
A18
A15
VSS
DQ24
DQ22
QK1
DQ25
DQ23
QK1#
DQ21
DQ19
VEXT
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ35
DQ33
DQ31
DQ29
DQ27
VEXT
DQ34
DQ32
DQ30
DQ28
DQ26
TD0
A19
DM
VSS
VTT
VDD
TDI
N
P
R
T
VTT
DQ20
DQ18
ZQ
VDD
VREF
U
V
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be
connected to GND.
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Rev.A2, 02/09/2017
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
1.4 Ball Descriptions
Symbol
Type
Description
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a
MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising
edge of CK.
A0-A21
Input
Bank address inputs: Selects to which internal bank a command is being applied to.
BA0-BA2
CK, CK#
Input
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
CS#
Input
I/O
Data input: The DQ signals form the data bus. During READ commands, the data is referenced to both
edges of QK*. During WRITE commands, the data is sampled at both edges of DK.
DQ0-DQ35
Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to both
edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17 are
referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18
devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the
device.
DK, DK#
DM
Input
Input
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TCK
Input
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
TMS,TDI
WE#,
REF#
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
Input
Input
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VREF
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
ZQ
I/O
Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are
aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and
QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.
QKX, QKX# Output
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
QVLD
TDO
Output
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not
used.
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
Power supply: Nominally, 1.8V.
VDD
Supply
Supply
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
VDDQ
Power supply: Nominally, 2.5V.
VEXT
VSS
Supply
Supply
Ground.
DQ ground: Isolated on the device for improved noise immunity.
VSSQ
VTT
Supply
Supply
-
Power supply: Isolated termination supply. Nominally, VDDQ/2.
Reserved for future use: This signal is not connected and can be connected to ground.
A22
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
No function: These balls can be connected to ground.
DNU
NF
-
-
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
I/O Voltage
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Min
0.3
0.3
0.3
0.3
Max
VDDQ + 0.3
+ 2.8
Units
V
V
V
V
+ 2.1
+ 2.1
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Supply voltage
Supply voltage
Isolated output buffer
supply
Conditions
Symbol
VEXT
VDD
Min
2.38
1.7
Max
2.63
1.9
Units
V
V
Notes
2
VDDQ
1.4
VDD
V
2,3
Reference voltage
VREF
VTT
VIH
0.49 x VDDQ
0.95 x VREF
VREF + 0.1
0.51 x VDDQ
1.05 x VREF
VDDQ + 0.3
V
V
V
V
4,5,6
7,8
2
Termination voltage
Input high voltage
Input low voltage
VIL
2
VSSQ 0.3
(VDDQ/2)/
(1.15 x RQ/5)
(VDDQ/2)/
(1.15 x RQ/5)
VREF 0.1
(VDDQ/2)/
(0.85 x RQ/5)
(VDDQ/2)/
(0.85 x RQ/5)
5
9, 10,
11
9, 10,
11
Output high current
Output low current
VOH = VDDQ/2
VOL = VDDQ/2
IOH
IOL
A
A
Clock input leakage current
Input leakage current
Output leakage current
Reference voltage current
Notes:
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
ILC
ILI
ILO
IREF
µA
µA
µA
µA
5
5
5
5
5
5
5
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH (AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL (AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD
Control input signals may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ
.
5. Peak-to-peak AC noise on VREF must not exceed ±2 percent VREF (DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error and an additional ±2
percent VDDQ/2 for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF
.
8. On-die termination may be selected using mode register A9 (for non-multiplexed address mode) or Ax9 (for multiplexed address mode). A
resistance RTT from each data input signal to the nearest VTT can be enabled. RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ /2. IOH flows from the device, IOL flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
Test Conditions
Min
Max
Units
Address / Control Input capacitance
I/O, Output, Other capacitance (DQ, DM, QK,
QVLD)
CIN
VIN=0V
1.5
2.5
pF
CIO
VIO=0V
3.5
5.0
pF
Clock Input capacitance
JTAG pins
CCLK
CJ
VCLK=0V
VJ=0V
2.0
2.0
3.0
5.0
pF
pF
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.
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Rev.A2, 02/09/2017
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
2.4 Conditions and Maximum Limits
Descriptio
Condition
Symbol
-18
109
109
5
-25E
109
109
5
-25
109
109
5
-33
109
109
5
units
ISB1(VDD) x9/x18
Standby
current
mA
ISB1(VDD) x36
tCK = idle; All banks idle; No inputs toggling
ISB1(VEXT
)
ISB2(VDD) x9/x18
ISB2(VDD) x36
282
282
5
236
236
5
236
236
5
209
209
5
Active
standby
current
CS# =1; No commands; Bank address
incremented and half address/data change once
every 4 clock cycles
mA
mA
ISB2(VEXT
)
IDD1(VDD) x9/x18
IDD1(VDD) x36
BL=2; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
continuous data during WRITE commands
445
345
323
291
509
10
373
10
345
10
314
10
IDD1(VEXT
)
IDD2(VDD) x9/x18
IDD2(VDD) x36
486
364
336
309
BL = 4; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
Continuous data during WRITE commands
Operationa
mA
mA
491
10
400
10
368
10
336
10
l
current
IDD2(VEXT
)
IDD3 (VDD) x9/x18
IDD3 (VDD) x36
545
618
445
518
395
450
368
423
BL = 8; Sequential bank access; Bank transitions
once every tRC; half address transitions once every
tRC; Read followed by write sequence; continuous
data during WRITE commands
IDD3(VEXT
)
10
382
382
10
10
314
314
10
10
314
314
10
10
264
264
10
IREF1(VDD) x9/x18
IREF1(VDD) x36
Burst
refresh
current
Eight-bank cyclic refresh; Continuous
address/data; Command bus remains in refresh
for all eight banks
mA
mA
mA
mA
mA
mA
mA
mA
IREF1(VEXT
)
IREF2(VDD) x9/x18
IREF2(VDD) x36
355
355
10
295
295
10
282
282
10
250
250
10
Distributed Single-bank refresh; Sequential bank access; Half
refresh
current
address transitions once every tRC, continuous
data
IREF2(VEXT
)
IDD2W(VDD) x9/x18
IDD2W(VDD) x36
950
1014
20
768
818
15
768
818
15
614
655
10
BL=2; Cyclic bank access; Half of address bits
change every clock cycle; Continuous data;
measurement is taken during continuous WRITE
IDD2W(VEXT
)
Operating
burst
write
IDD4W(VDD) x9/x18
IDD4W(VDD) x36
705
759
10
564
609
10
564
609
10
464
500
10
BL=4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous WRITE
IDD4W(VEXT
)
current
IDD8W(VDD) x9/x18
IDD8W(VDD) x36
632
682
10
505
545
10
505
545
10
414
450
10
BL=8; Cyclic bank access; Half of address bits
change every 4 clock cycles; continuous data;
Measurement is taken during continuous WRITE
IDD8W(VEXT
)
IDD2R(VDD) x9/x18
IDD2R(VDD) x36
927
1100
20
727
836
15
727
836
15
582
664
10
BL=2; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
during continuous READ
IDD2R(VEXT
)
Operating
burst
read
current
IDD4R(VDD) x9/x18
IDD4R(VDD) x36
705
850
10
550
650
10
550
618
10
445
518
10
BL=4; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
during continuous READ
IDD4R(VEXT
)
IDD8R(VDD) x9/x18
IDD8R(VDD) x36
655
795
10
509
605
10
509
577
10
414
482
10
BL=8; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
during continuous READ
IDD8R(VEXT
)
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
Notes:
1) IDD specifications are tested after the device is properly initialized. +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ
≤ VDD, VREF = VDDQ/2.
2) tCK = tDK = MIN, tRC = MIN.
3) Definitions for IDD conditions:
a. LOW is defined as VIN ≤ VIL(AC) MAX.
b. HIGH is defined as VIN ≥ VIH(AC) MIN.
c. Stable is defined as inputs remaining at a HIGH or LOW level.
d. Floating is defined as inputs at VREF = VDDQ/2.
e. Continuous data is defined as half the D or Q signals changing between HIGH and LOW every half clock cycle (twice per clock).
f.
Continuous address is defined as half the address signals changing between HIGH and LOW every clock cycle (once per clock).
g. Sequential bank access is defined as the bank address incrementing by one every tRC
.
h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL
= 4 this is every other clock, and for BL = 8 this is every fourth clock.
4) CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
5) IDD parameters are specified with ODT disabled.
6) Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
7) IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#). Parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input
signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC).
2.5 Recommended AC Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted.)
Parameter
Input HIGH voltage
Input LOW voltage
Symbol
VIH(AC)
VIL(AC)
Min
VREF + 0.2
-
Max
-
VREF – 0.2
Units
V
V
Notes:
1. Overshoot: VIH (AC) ≤ VDDQ + 0.7V for t ≤ tCK/2
2. Undershoot: VIL (AC) ≥ – 0.5V for t ≤ tCK/2
3. Control input signals may not have pulse widths less than tCKH(MIN) or operate at cycle rates less than tCK(MIN.).
2.6 Temperature and Thermal Impedance
Temperature Limits
Parameter
Symbol
Min
0
0
Max
+110
+100
+95
Units
°C
°C
Reliability junction temperature 1
Operating junction temperature 2
Operating case temperature 3
TJ
TJ
TC
0
°C
Notes:
1. Temperatures greater than 110°C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
or above this is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability of the part.
2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow.
3. MAX operating case temperature; TC is measured in the center of the package. Device functionality is not guaranteed if the device exceeds
maximum TC during operation.
Thermal Resistance
Theta-ja
(Airflow =
1m/s)
Theta-ja
(Airflow =
2m/s)
Theta-ja
(Airflow = 0m/s)
Package
Substrate
4-layer
Unit
C/W
Theta-jc
2.4
144-ball FBGA
28.4
24.3
22.1
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2.7 AC Electrical Characteristics (1, 2, 3, 4)
-18 (1.875ns
@tRC=15ns)
-25E (2.5ns
@tRC=15ns)
-25 (2.5ns
@tRC=20ns)
-33 (3.3ns
@tRC=20ns)
Units
Description
Symbol
Min
1.875
tCK
Max
Min
2.5
Max
Min
2.5
Max
Min
3.3
Max
Input clock cycle time
Input data clock cycle time
Clock jitter: period (5, 6)
tCK
tDK
5.7
–
5.7
–
5.7
–
5.7
–
ns
ns
ps
tCK
–150
tCK
–150
tCK
–200
tJITPER
–100
100
150
150
200
Clock jitter:
cycle-to-cycle
tJITCC
–
200
–
300
–
300
–
400
ps
Clock HIGH time
Clock LOW time
tCKH/tDKH
tCKL/tDKL
tCKDK
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
Clock to input data
clock
–0.3
0.3
–0.45
0.5
–0.45
0.5
–0.45
1.2
ns
Mode register set
cycle time to any
command
tMRSC
tAS/tCS
tDS
6
–
6
–
6
–
6
–
tCK
Address/command
and input setup time
Data-in and data
mask to DK setup time
Address/command
and input hold time
Data-in and data
mask to DK
hold time
Output data clock
HIGH time
Output data clock
LOW time
0.3
0.17
0.3
–
–
–
0.4
0.25
0.4
–
–
–
0.4
0.25
0.4
–
–
–
0.5
0.3
0.5
–
–
–
ns
ns
ns
tAH/tCH
tDH
0.17
0.9
–
0.25
0.9
–
0.25
0.9
–
0.3
0.9
–
ns
tQKH
tQKL
tQHP
tCKQK
tQKQ0
1.1
1.1
–
1.1
1.1
–
1.1
1.1
–
1.1
1.1
–
tCKH
tCKL
0.9
0.9
0.9
0.9
MIN(tQKH
tQKL
,
MIN(tQKH
tQKL
,
MIN(tQKH
tQKL
,
MIN(tQKH,
tQKL)
Half-clock period
)
)
)
QK edge to clock
edge skew
QK edge to output
data edge (7)
–0.2
0.2
0.12
–0.25
–0.2
0.25
0.2
–0.25
–0.2
0.25
0.2
–0.3
0.3
0.25
ns
ns
,
–0.12
–0.25
tQKQ1
tQKQ
tQKVLD
QK edge to any
–0.22
–0.22
0.22
0.22
–0.3
–0.3
0.3
0.3
–0.3
–0.3
0.3
0.3
–0.35
–0.35
0.35
0.35
ns
ns
output data edge (8)
QK edge to QVLD
tQHP
-
tQHP
-
tQHP
-
tQHP
(tQKQx
[MAX] +
|tQKQx
[MIN]|)
-
(tQKQx
[MAX] +
|tQKQx
(tQKQx
(tQKQx
Data valid window
tDVW
–
[MAX] +
|tQKQx
–
[MAX] +
|tQKQx
–
–
[MIN]|)
[MIN]|)
[MIN]|)
Average periodic refresh
interval (9)
tREFI
–
0.24
–
0.24
–
0.24
–
0.24
μs
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address,
and data signals.
2. Outputs measured with equivalent load:
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VTT
50 Ω
DQ
Test Point
10 pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the
input signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. For a x36 device, DQ0-DQ17 is referenced to tQKQ0 and DQ18-DQ35 is referenced to tQKQ1. For a x18 device, DQ0-DQ8 is referenced to tQKQ0 and
DQ9-DQ17 is referenced to tQKQ1. For a x9 device, tQKQ0 is referenced to DQ0-DQ8.
8. tQKQ takes into account the skew between any QKx and any Q.
9. To improve efficiency, eight AREF commands (one for each bank) can be posted to the memory on consecutive cycles at periodic intervals of
1.95μs.
2.8 Clock Input Conditions
Differential Input Clock Operating Conditions
Min
-0.3
0.2
Max
Parameter
Clock Input Voltage Level
Symbol
VIN(DC)
VID(DC)
VID(AC)
Units
Notes
VDDQ+0.3
VDDQ+0.6
VDDQ+0.6
VDDQ/2+0.15
V
V
V
V
8
8
9
Clock Input Differential Voltage Level
Clock Input Differential Voltage Level
0.4
VDDQ/2-
0.15
Clock Input Crossing Point Voltage Level
VIX(AC)
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Clock Input Example
CK#
VDDQ/2+0.15V, VIX(AC) MAX
VDDQ/2
(10)
VID(DC)(11) VID(AC)(12)
VDDQ/2-0.15V, VIX(AC) MIN
CK
Notes:
1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to V
.
SS
3. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related
specifications and device operations are tested for the full voltage range specified.
4. AC timing and IDD tests may use a V -to-V swing of up to 1.5V in the test environment, but input timing is still referenced to V (or the
REF
IL
IH
crossing point for CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum
slew rate for the input signals used to test the device is 2V/ns in the range between V (AC) and V (AC).
IL
IH
5. The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal
crossing the AC input level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level).
6. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal
other than CK/CK# is V
.
REF
7. CK and CK# input slew rate must be ≥ 2V/ns (≥ 4V/ns if measured differentially).
8. is the magnitude of the difference between the input level on CK and input level on CK#.
9. The value of V is expected to equal V
V
ID
/2 of the transmitting device and must track variations in the DC level of the same.
DDQ
IX
10. CK and CK# must cross within the region.
11. CK and CK# must meet at least V (DC) (MIN.) when static and centered on V
/2.
DDQ
ID
12. Minimum peak-to-peak swing.
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3 Functional Descriptions
3.1 Power-up and Initialization (1)
The RLDRAM 2 Memory must be powered-up and initialized using the specific steps listed below:
1. Apply power by ramping up supply voltages VEXT, VDD, VDDQ, VREF, and VTT. Apply VDD and VEXT before or at the same
time as VDDQ (2). Power-up sequence begins when both VDD and VEXT approach their nominal levels. Afterwards, apply
VDDQ before or at the same time as VREF and VTT. Once the supply voltages are stable, clock inputs CK/CK# and
DK/DK# can be applied. Register NOP commands to the control pins to avoid issuing unwanted commands to the
device.
2. Keep applying stable conditions for a minimum of 200 µs.
3. Register at least three consecutive MRS commands consisting of two or more dummy MRS commands and one valid
MRS command. Timing parameter tMRSC is not required to be met during these consecutive MRS commands but
asserting a LOW logic to the address signals is recommended.
4. tMRSC timing delay after the valid MRS command, Auto Refresh commands to all 8 banks and 1,024 NOP commands
must be issued prior to normal operation. The Auto Refresh commands to the 8 banks can be issued in any order with
respect to the 1,024 NOP commands. Please note that the tRC timing parameter must be met between an Auto
Refresh command and a valid command in the same bank.
5. The device is now ready for normal operation.
Notes:
1. Operational procedure other than the one listed above may result in undefined operations and may permanently damage the device.
2.
V
can be applied before V but will result in all DQ data pin, DM, and output pins to go logic HIGH (instead of tri-state) and will remain HIGH
DDQ DD
until the V is the same level as V
. This method is not recommended to avoid bus conflicts during the power-up.
DDQ
DD
3.2 Power-up and Initialization Flowchart
VDD and VEXT
ramp up (1)
Issue dummy
VDDQ ramp up (1)
2nd MRS command (2)
Issue valid
VREF and VTT
ramp up (1)
3rd MRS command (2)
Apply stable
CK/CK# and DK/DK#
Assert NOP for tMRS
Issue AREF
commands to all 8
banks (3)
Wait 200µs minimum
Issue dummy
Issue 1,024 NOP
commands (3)
1st MRS command (2)
RLDRAM is now ready
for normal operation
Notes:
1. The supply voltages can be ramped up simultaneously.
2. The dummy and valid MRS commands must be issued in consecutive clock cycles. At least two dummy MRS commands are required. It is
recommended to assert a LOW logic on the address signals during the dummy MRS commands.
3. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met
before issuing any valid command in a bank after an AREF command to the same bank has been issued.
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3.3 Power-up and Initialization Timing Diagram
Non-multiplexed Address Mode
VEXT, VDD
VDDQ, VREF
,
,
VTT
tCKH
tCKL
tCK
CK
~~
~~
~~
~~
CK#
AREF-
BA0
AREF-
BA7
MRS1,2
MRS1,2
MRS2
NOP
Any5
NOP
Command
NOP
tMRSC
200us(Min)
Refresh all 8 banks
1024 NOPs
Don’t care
Notes:
1. It is recommended that the address input signals be driven LOW during the dummy MRS commands.
2. A10–A17 must be LOW.
3. DLL must be reset if tCK or VDD are changed.
4. CK and CK# must be separated at all times to prevent invalid commands from being issued.
5. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met
before issuing any valid command in a bank after an AREF command to the same bank has been issued.
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Multiplexed Address Mode
VEXT, VDD,
VDDQ
VREF, VTT
,
tCKH tCKL
tCK
CK
CK#
~
~
~~
~~
~~
~~
NOP
Any
Any
NOP
MRS
MRS
A1,2
MRS
A2,3
MRS
Ax2,4
NOP
Ay
AREF
AREF
Command
A1,2
Bank0
Bank7
ADDRESS
6
Refresh all 8
banks
tMRSC
tMRSC
200us(Min)
1024NOPs
Don’t care
Notes:
1. It is recommended that the address input signals be driven LOW during the dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enables the part to enter multiplexed address mode when in moon-multiplexed mode operation. Multiplexed address
mode can also be entered at some later time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH, tMRSC must be
satisfied before the two cycle multiplexed mode MRS command is issued.
4. Address A5 must be set HIGH. This and the following step set the desired mode register once the memory is in multiplexed address mode.
5. CK and CK# must be separated at all times to prevent invalid commands from being issued.
6. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter tRC must be met
before issuing any valid command (Any) in a bank after an AREF command to the same bank has been issued.
3.4 Mode Register Setting and Features
MRS - Non-Multiplexed Mode
MRS - Multiplexed Mode
CK
CK#
CS#
Any
Valid
Any
Valid
WE#
REF#
Valid
Ax
Ay
Valid
Code
ADD
tMRSC
tMRSC
Don’t care
Note: The MRS command can only be issued when all banks are idle and no bursts are in progress.
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The Mode Register Set command stores the data for controlling the various operating modes of the memory using
address inputs A0-A17 as mode registers. During the MRS command, the cycle time and the read/write latency of the
memory can be selected from different configurations. The MRS command also programs the memory to operate in either
Multiplexed Address Mode or Non-multiplexed Address Mode. In addition, several features can be enabled using the MRS
command. These are the DLL, Drive Impedance Matching, and On-Die Termination (ODT). tMRSC must be met before any
command can be issued. tMRSC is measured like the picture above in both Multiplexed and Non-multiplexed mode.
Mode Register Diagram (Non-multiplexed Address Mode)
Address
Field
On-Die Termination
Off (Default)
On
A9
0
1
Mode Register
0 1
ODT
IM
A10-17 M10-17
Drive Impedance
A8
0
1
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Internal 50Ω 5 (Default)
External(ZQ)
DLL Reset
A7
0
1
DLL
DLL reset4 (Default)
DLL enable
NA2
AM
Address MUX
Non-multiplexed (Default)
Multiplexed
A5
0
1
BL
Burst Length(BL)
A4
0
0
1
1
A3
0
1
0
1
2 (Default)
4
8
Reserved
Config
Read/Write Latency and Cycle Time Configuration6
Valid Frequency Range
(MHz)
Configuration
A2
0
A1
0
A0
0
tRC(tCK)
tRL(tCK)
tWL(tCK)
1 3 (Default)
266-175
266-175
4
4
6
4
4
6
5
5
7
1 3
2
0
0
1
400-175
0
1
0
533-1758
200-175
333-175
n/a
3
0
1
1
8
3
5
8
3
5
9
4
6
4 3,7
5
1
0
0
1
0
1
Reserved
Reserved
1
1
0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
1
1
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
A10-A17 must be set to zero; A18-An are "Don't cares."
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
±30 % temperature variation.
tRC < 20ns in any configuration is only available with -25E and -18 speed grades.
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles.
tCK must be met to use this configuration. For tCK values, please refer to AC Electrical Characteristics table.
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Mode Register Diagram (Multiplexed Address Mode)
A9
0
1
On-Die Termination
Off (Default)
On
Ax
Ay
Mode Register
0 1
ODT
IM
A10-18 A10-18 M10-18
A8
0
1
Drive Impedance
A9
A8
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Internal 50Ω 6 (Default)
External(ZQ)
A7
0
1
DLL Reset
A9
A8
DLL
DLL reset4 (Default)
DLL enable
NA5
AM
A5
0
1
Address MUX
Non-multiplexed (Default)
Multiplexed
A5
A4
A3
BL
A4
0
0
1
1
A3
Burst Length(BL)
0
1
0
1
2 (Default)
4
8
A4
A3
Reserved
Config
A0
Read/Write Latency and Cycle Time Configuration8
Valid Frequency
Range (MHz)
266-175
266-175
400-175
533-17510
200-175
333-175
n/a
Ay4
0
Ay3
0
Ax0
0
Configuration
tRC(tCK)
tRL(tCK)
tWL(tCK)
1 2 (Default)
4
4
6
5
5
7
6
6
8
1 2
2
0
0
1
0
1
0
0
1
1
3
8
3
5
9
4
6
10
5
7
4 2,9
5
1
0
0
1
0
1
1
1
0
Reserved
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
1
1
1
n/a
Notes:
1. A10-A18 must be set to zero; A18-An are "Don't cares."
2. BL = 8 is not available.
3. ±30 % temperature variation.
4. DLL RESET turns the DLL off.
5. Ay = 8 is not used in MRS.
6. BA0-BA2 are "Don't care."
7. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode.
8. tRC < 20ns in any configuration is only available with -25E speed grade.
9. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4
cycles.
10. tCK must be met to use this configuration. For tCK values, please refer to the AC Electrical Characteristics table.
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3.5 Mode Register Bit Description
Configuration
The cycle time and read/write latency can be configured from the different options shown in the Mode Register Diagram.
In order to maximize data bus utilization, the WRITE latency is equal to READ latency plus one. The read and write
latencies are increased by one clock cycle during multiplexed address mode compared to non-multiplexed mode.
Burst Length
The burst length of the read and write accesses to memory can be selected from three different options: 2, 4, and 8.
Changes in the burst length affect the width of the address bus and is shown in the Burst Length and Address Width
Table. The data written during a prior burst length setting is not guaranteed to be accurate when the burst length of the
device is changed.
Burst Length and Address Width Table
576Mb Address Bus
Burst Length
x9
x18
x36
2
4
8
A0-A21
A0-A20
A0-A19
A0-A20
A0-A19
A0-A18
A0-A19
A0-A18
A0-A17
DLL Reset
The default setting for this option is LOW, whereby the DLL is disabled. Once the mode register for this feature is set
HIGH, 1024 cycles (5μs at 200 MHz) are needed before a READ command can be issued. This time allows the internal
clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the
tCKQK parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has already been enabled. To reset
the DLL, an MRS command must be issued where the DLL Reset Mode Register is set LOW. After waiting tMRSC, a
subsequent MRS command should be issued whereby the DLL Reset Mode Register is set HIGH. 1024 clock cycles are
then needed before a READ command is issued.
Drive Impedance Matching
The RLDRAM 2 Memory is equipped with programmable impedance output buffers. The purpose of the programmable
impedance output buffers is to allow the user to match the driver impedance to the system. To adjust the impedance, an
external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times
the desired impedance. For example, a 300Ω resistor is required for an output impedance of 60Ω. The range of RQ is
125–300Ω, which guarantees output impedance in the range of 25–60Ω (within 15 percent). Output impedance updates
may be required because over time variations may occur in supply voltage and temperature. When the external drive
impedance is enabled in the MRS, the device will periodically sample the value of RQ. An impedance update is
transparent to the system and does not affect device operation. All data sheet timing and current specifications are met
during an update. When the Drive Impedance Mode Register is set LOW during the MRS command, the memory provides
an internal impedance at the output buffer of 50Ω (±30% with temperature variation). This impedance is also periodically
sampled and adjusted to compensate for variation in supply voltage and temperature.
Address Multiplexing
Although the RLDRAM 2 Memory is capable of accepting all the addresses in a single rising clock edge, this memory
can be programmed to operate in multiplexed address mode, which is very similar to a traditional DRAM. In multiplexed
address mode, the address can be sent to the memory in two parts within two consecutive rising clock edges. This
minimizes the number of address signal connections between the controller and the memory by reducing the address bus
to a maximum of only 11 lines. Since the memory requires two clock cycles to read and write the data, data bus efficiency
is affected when operating in continuous burst mode with a burst length of 2 setting. Bank addresses are provided to the
memory at the same time as the WRITE and READ commands together with the first address part, Ax. The second
address part, Ay, is then issued to the memory on the next rising clock edge. AREF commands only require the bank
address. Since AREF commands do not need a second consecutive clock for address latching, they may be issued on
consecutive clocks.
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Address Mapping in Multiplexed Address Mode
Address
A9
Data Width
Burst Length
Ball
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
A0
A0
X
A3
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
A5
X
A8
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A10
A10
A19
A10
X
A13
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A18
A15
A18
A15
X
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
2
4
8
2
4
8
2
4
8
A0
X
A5
X
x36
A0
X
A5
X
A10
X
A15
A18
A15
A18
A15
A18
A15
A18
A15
A18
A15
A18
A15
A0
A20
A0
X
A5
X
A10
A19
A10
A19
A10
X
A5
X
X18
A0
X
A5
X
A0
A20
A0
A20
A0
X
A5
A21
A5
X
A10
A19
A10
A19
A10
A19
X9
A5
X
Note: X = Don’t Care.
On-Die Termination (ODT)
If the ODT is enabled, the DQs and DM are terminated to VTT with a resistance RTT. The command, address, QVLD, and
clock signals are not terminated. Figure 3.1 shows the equivalent circuit of a DQ receiver with ODT. The ODT function is
dynamically switched off when a DQ begins to drive after a READ command is issued. Similarly, ODT is designed to
switch on at the DQs after the memory has issued the last piece of data. The DM pin will always be terminated.
ODT DC Parameters Table
Description
Symbol
Min
Max
Units
Notes
Termination Voltage
On-die termination
VTT
RTT
0.95 x VREF
125
1.05 x VREF
185
V
Ω
1, 2
3
Notes:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF
3. The RTT value is measured at 95°C TC.
.
VTT
Switch
RTT
Receiver
DQ
Figure 3.1 ODT Equivalent Circuit
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3.6 Deselect/No Operation (DESL/NOP)
The Deselect command is used to prevent unwanted operations from being performed in the memory device during wait
or idle states. Operations already registered to the memory prior to the assertion of the Deselect command will not be
cancelled.
3.7 Read Operation (READ)
The Read command performs burst-oriented data read accesses in a bank of the memory device. The Read command is
initiated by registering the WE# and REF# signals logic HIGH while the CS# is in logic LOW state. In non-multiplexed
address mode, both an address and a bank address must be provided to the memory during the assertion of the Read
command. In multiplexed mode, the bank address and the first part of the address, Ax, must be supplied together with the
Read command. The second part of the address, Ay, must be latched to the memory on the subsequent rising edge of the
CK clock. Data being accessed will be available in the data bus a certain amount of clock cycles later depending on the
Read Latency Configuration setting.
Data driven in the DQ signals are edge-aligned to the free-running output data clocks QKx and QKx#. A half clock cycle
before the read data is available on the data bus, the data valid signal, QVLD, will transition from logic LOW to HIGH. The
QVLD signal is also edge-aligned to the data clock QKx and QKx#.
If no other commands have been registered to the device when the burst read operation is finished, the DQ signals will go
to High-Z state. The QVLD signal transition from logic HIGH to logic LOW on the last bit of the READ burst. Please note
that if CK/CK# violates the VID (DC) specification while a READ burst is occurring, QVLD will remain HIGH until a dummy
READ command is registered. The QK clocks are free-running and will continue to cycle after the read burst is complete.
Back-to-back READ commands are permitted which allows for a continuous flow of output data.
Non-Multiplexed
Mode
Multiplexed
Mode
CK#
CK
CK#
CK
CS#
CS#
WE#
REF#
WE#
REF#
A
Ax
Ay
ADDRESS
ADDRESS
BANK
ADDRESS
BANK
ADDRESS
BA*
BA*
Don’t care
Read Command
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0
1
2
3
4
5
6
tCKH
tCKL
tCK
CK#
CK
RD
RD
NOP
NOP
NOP
NOP
NOP
Command
Address
BA2, A2
BA3, A3
Read Latency = 4
tQKVLD
tQKVLD
QVLD
DQ
tQKQ
Q2-1
tQKQ
Q2-2
Q3-1
Q3-2
tCKQK
tQKH
tQKL
QKx#
QKx
Don’t Care
Basic READ Burst with QVLD: BL=2 & RL=4
Notes:
1. Minimum READ data valid window can be expressed as MIN(tQKH, tQKL) – 2 x MAX(tQKQx).
2. tCKH and tCKL are recommended to have 50% / 50% duty.
3. tQKQ0 is referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18. tQKQ1 is referenced to DQ18–DQ35 in x36 and DQ9–DQ17 in x18.
4. tQKQ takes into account the skew between any QKx and any DQ.
5. tCKQK is specified as CK rising edge to QK rising edge.
3.8 Write Operation (WRITE)
The Write command performs burst-oriented data write accesses in a bank of the memory device. The Write command is
initiated by registering the REF# signal logic HIGH while the CS# and WE# signals are in logic LOW state. In non-
multiplexed address mode, both an address and a bank address must be provided to the memory during the assertion of
the Write command. In multiplexed mode, the bank address and the first part of the address, Ax, must be supplied
together with the Write command. The second part of the address, Ay, must be latched to the memory on the subsequent
rising edge of the CK clock. Input data to be written to the device can be registered several clock cycles later depending
on the Write Latency Configuration setting. The write latency is always one cycle longer than the programmed read
latency. The DM signal can mask the input data by setting this signal logic HIGH.
At least one NOP command in between a Read and Write commands is required in order to avoid data bus contention.
The setup and hold times for DM and data signals are tDS and tDH, which are referenced to the DK clocks.
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Non-Multiplexed
Mode
Multiplexed
Mode
CK#
CK
CK#
CK
CS#
CS#
WE#
REF#
WE#
REF#
A
Ax
Ay
ADDRESS
ADDRESS
BANK
ADDRESS
BANK
ADDRESS
BA*
BA*
Don’t care
Write Command
0
1
2
3
4
5
6
7
CK#
CK
tCKDK
DKx#
DKx
Command
Address
WR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
BA1, A1
Write Latency = 5
DM
DQ
tDS tDH
D1-2
D1-0
D1-3
D1-4
Masked Data
Don’t Care
Undefined
Basic WRITE Burst with DM Timing: BL=4 & WL=5
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0
1
2
3
4
5
6
7
8
9
CK#
CK
WR
NOP
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
Command
Address
BA1,A1
BA2, A2
BA3, A3
Read Latency = 4
Write Latency = 5
DKx
DKx#
D1-1 D1-2
Q2-1 Q2-2 Q3-1 Q3-2
DQ
QVLD
QKx
QKx#
Don’t Care
Undefined
Write Followed by Read: BL=2 RL=4 & WL=5
3.9 Auto Refresh Command (AREF)
The Auto Refresh command performs a refresh cycle on one row of a specific bank of the memory. Only bank addresses
are required together with the control the pins. Therefore, Auto Refresh commands can be issued on subsequent CK
clock cycles on both multiplexed and non-multiplexed address mode. Any command following an Auto Refresh command
must meet a tRC timing delay or later.
2
3
0
1
4
5
6
tCKH
tCKL
tCK
CK#
CK
QKx#
QKx
tRC
AREFx
BAx
AREFy
BAy
NOP
NOP
NOP
ANYCOMx
BAx
ANYCOMy
BAy
Command
tRC
Bank Address
Don’t Care
AREF example in tRC(tCK)=5 option: Configuration=5
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CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
BA*
ADDRESS
Don’t care
Auto Refresh Command
3.10 Command Truth Table
Operation
Device DESELECT/No Operation
Mode Register Set
Read
Write
Code
DESL/NOP
MRS
READ
WRITE
AREF
CS#
H
L
L
L
WE#
X
L
H
L
REF#
X
L
H
H
L
Ax
X
OPCODE
A
A
X
BAx
X
X
BA
BA
BA
Auto Refresh
L
H
Notes:
1. X = "Don't Care;" H = logic HIGH; L = logic LOW; A = Valid Address; BA = Valid Bank Address.
2. During MRS, only address inputs A0-A17 are used.
3. Address width changes with burst length.
4. All input states or sequences not shown are illegal or reserved.
5. All command and address inputs must meet setup and hold times around the rising edge of CK.
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3.11 On-Die Termination (ODT) Timing Examples
0
1
2
3
4
5
6
7
CK#
CK
RD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
BA2, A2
Address
Read Latency = 4
tQKVLD
tQKVLD
QVLD
DQ ODT on
DQ ODT Off
DQ ODT on
DQ ODT
Q2-0
Q2-1
Q2-2
Q2-3
DQ
QKx#
QKx
Don’t Care
Undefined
6
Read Operation with ODT: RL=4 & BL=4
0
1
2
3
4
5
7
CK#
CK
RD
WR
NOP
NOP
NOP
NOP
NOP
NOP
Command
Address
BA2, A2
BA1, A1
Read Latency = 4
DKx#
DKx
Write Latency = 5
tQKVLD
tQKVLD
QVLD
DQ ODT
DQ
DQ ODT on
DQ ODT Off
DQ ODT on
Q2-0 Q2-1
D1-0
D1-1
QKx#
QKx
Don’t Care
Undefined
Read to Write with ODT: RL=4 & BL=2
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4 IEEE 1149.1 TAP and Boundary Scan
RLDRAM 2 Memory devices have a serial boundary-scan test access port (TAP) that allow the use of a limited set of
JTAG instructions to test the interconnection between the memory I/Os and printed circuit board traces or other
components. In conformance with IEEE Standard 1149.1, the memory contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register. The TAP operates in accordance with IEEE Standard 1149.1-
2001 (JTAG) with the exception of the ZQ pin. To guarantee proper boundary-scan testing of the ZQ pin, MRS bit M8
needs to be set to 0 until the JTAG testing of the pin is complete. Note that on power up, the default state of MRS bit M8
is logic LOW.
If the memory boundary scan register is to be used upon power up and prior to the initialization of the device, the CK and
CK# pins meet VID(DC) or CS# be held HIGH from power up until testing. Not doing so could result in inadvertent MRS
commands to be loaded, and subsequently cause unexpected results from address pins that are dependent upon the
state of the mode register. If these measures cannot be taken, the part must be initialized prior to boundary scan testing. If
a full initialization is not practical or feasible prior to boundary scan testing, a single MRS command with desired settings
may be issued instead. After the single MRS command is issued, the tMRSC parameter must be satisfied prior to boundary
scan testing.
4.1 Disabling the JTAG feature
The RLDRAM 2 Memory can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied
LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They
may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device
will come up in a reset state, which will not interfere with device operation.
4.2 Test Access Port Signal List:
Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are captured on the
rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is sampled
on the rising edge of TCK.
Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information into the
registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any
register. For more information regarding instruction register loading, please see the TAP Controller State Diagram.
Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data out from
the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other
states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is connected to the least
significant bit (LSB) of any register. For more information, please see the TAP Controller State Diagram.
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4.3 TAP Controller State and Block Diagram
1
Test Logic Reset
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
0
Shift IR
1
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
Exit2 IR
1
0
0
1
Update DR
0
Update IR
1
0
Note1
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
Instruction Register (8 bits)
Control Signals
TDO
TMS
TCK
TAP Controller
Note: 113 boundary scan registers in RLDRAM 2 Memory
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4.4 Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM
is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a
high-Z state.
4.5 TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI
pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as
described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a
binary “01” pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be
shifted through the memory device with minimal delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the device. Several balls are also
included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the memory
Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on the device package.
The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into the device and can be shifted out when the TAP
controller is in the shift-DR state.
4.6 Scan Register Sizes
Register Name
Instruction Register
Bit Size
8
Bypass Register
1
Boundary Scan Register
Identification (ID) Register
113
32
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4.7 TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be used.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at
output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction.
Thus, during the update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the
output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places
the identification register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the
TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
High-Z
The High-Z instruction causes the bypass register to be connected between the TDI and TDO. This places all RLDRAM
2 Memory outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from
the values held in the boundary scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the capture-
DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must
be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the memory clock operates
significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the
capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible. To ensure that the boundary scan register will capture the correct value of a
signal, the memory signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS
plus tCH). The memory clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore
the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out
the data by putting the TAP into the shift-DR state. This places the boundary scan register between the TDI and TDO
balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass
register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
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4.8 TAP DC Electrical Characteristics and Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
Description
Conditions
Symbol
VIH
Min
Max
VDDQ + 0.3
VREF 0.15
5.0
Units Notes
VREF + 0.15
VSSQ 0.3
5.0
V
V
1, 2
1, 2
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
VIL
0V ≤ VIN ≤ VDD
ILI
µA
Output Disabled, 0V ≤ VIN ≤
Output leakage current
ILO
5.0
µA
5.0
VDDQ
Output low voltage
Output low voltage
Output high voltage
IOLC =100 µA
IOLT = 2mA
VOL1
VOL2
VOH1
VOH2
-
0.2
0.4
-
V
V
V
V
1
1
1
1
-
|IOHC| =100 µA
|IOHT | = 2mA
VDDQ - 0.2
VDDQ - 0.4
Output high voltage
-
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot = VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2; undershoot = VIL(AC) ≥ –0.5V for t ≤ tCK/2; during normal operation, VDDQ must not exceed VDD
.
4.9 TAP AC Electrical Characteristics and Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V)
Description
Symbol
Min
Max
Units
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
TDI/TDO times
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK High
TCK HIGH to TDI invalid
Setup times
20
ns
MHz
ns
tTHTH
fTF
tTHTL
tTLTH
50
10
10
ns
0
ns
ns
ns
ns
tTLOX
tTLOV
tDVTH
tTHDX
10
5
5
TMS Setup
5
5
ns
ns
tMVTH
tCS
Capture Setup
Hold Times
TMS hold
5
5
ns
ns
tTMHX
tCH
Capture hold
Note: tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
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4.10 TAP Timing
0
1
2
3
4
5
6
7
tTHTL
tTLTH
tTHTH
Test Mode
Clock (CK)
tMVTH tTHMX
Test Mode
Select (TMS)
tDVTH tTHDX
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
Don’t Care
Undefined
4.11 TAP Instruction Codes
Instruction
Code
Description
0000
0000
0010
0001
0000
0101
0000
0111
0000
0011
1111
1111
Captures Input and Output ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect device operations
Loads the ID register with the vendor ID code and places the register between TDI
and TDO; This operation does not affect device operations
Captures I/O ring contents; Places the boundary scan register between TDI and
TDO
Selects the bypass register to be connected between TDI and TDO; Data driven by
output balls are determined from values held in the boundary scan register
Selects the bypass register to be connected between TDI and TDO; All outputs are
forced into High-Z
Places the bypass register between TDI and TDO; This operation does not affect
device operations
EXTEST
IDCODE
SAMPLE/PRELOAD
CLAMP
High-Z
BYPASS
Note: All other remaining instruction codes not mentioned in the above table are reserved and should not be used.
4.12 Identification (ID) Register Definition
Instruction Field
All Devices
Description
ab = die revision
Revision number (31:28)
abcd
cd = 00 for x9, 01 for x18, 10 for x36
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for RLDRAM 2 Memory
Device ID (27:12)
00jkidef10100111
Vendor ID code (11:1)
ID register presence indicator (0)
000 0101 0101
1
Allows unique identification of vendor
Indicates the presence of an ID register
4.13 TAP Input AC Logic Levels
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
Description
Input high (logic 1) voltage
Symbol
VIH
Min
VREF + 0.3
-
Max
-
VREF - 0.3
Units
V
V
Input low (logic 0) voltage
VIL
Note: All voltages referenced to VSS (GND).
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
4.14 Boundary Scan Order
Signal name
Bump
ID
Signal name
x18
Bump
ID
Signal name
x18 x36
DNU DNU DQ2
DNU DNU DQ2
Bump
ID
Bit#
Bit#
Bit#
x9
DK
x18
x36
x9
x36
x9
1
2
3
4
5
6
7
8
DK
DK1
K1
K2
L2
L1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
DNU DNU DQ30 R11
DNU DNU DQ30 R11
DNU DNU DQ32 P11
DNU DNU DQ32 P11
DQ5 DQ10 DQ33 P10
DQ5 DQ10 DQ33 P10
DNU DNU DQ34 N11
DNU DNU DQ34 N11
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
C11
C11
C10
C10
B11
B11
B10
B10
B3
B3
B2
B2
C3
C3
C2
C2
D3
D3
D2
D2
E2
DK#
CS#
DK# DK1#
CS# CS#
DQ1
DQ1
DQ1
DQ1
DQ3
DQ3
REF# REF# REF#
WE# WE# WE#
M1
M3
M2
N1
P1
N3
N3
N2
N2
P3
P3
P2
P2
R2
R3
T2
T2
T3
DNU DNU DQ0
DNU DNU DQ0
A17
A16
A18
A15
A17
A16
A18
A15
A17
A16
A18
A15
DQ0
DQ0
DNU DQ4
DNU DQ4
DQ0
DQ0
DQ1
DQ1
DQ9
DQ9
9
DQ4
DQ4
DM
A19
A11
A12
A10
A13
A14
BA1
CK#
CK
DQ9 DQ35 N10
DQ9 DQ35 N10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DNU DQ14 DQ25
DNU DQ14 DQ25
DNU DNU DQ24
DNU DNU DQ24
DNU DQ15 DQ23
DNU DQ15 DQ23
DNU DNU DQ22
DNU DNU DQ22
DM
A19
A11
A12
A10
A13
A14
BA1
CK#
CK
DM
A19
A11
A12
A10
A13
A14
BA1
CK#
CK
BA0
A4
A3
A0
A2
P12
N12
M11
M10
M12
L12
DNU DNU DQ8
DNU DNU DQ8
DNU DQ5 DQ11
DNU DQ5 DQ11
DNU DNU DQ10
DNU DNU DQ10
DNU DQ6 DQ13
DNU DQ6 DQ13
DNU DNU DQ12
DNU DNU DQ12
DNU DNU DQ14
DNU DNU DQ14
DNU DQ7 DQ15
DNU DQ7 DQ15
DNU DNU DQ16
DNU DNU DQ16
DNU DQ8 DQ17
DNU DQ8 DQ17
A21 (A21) (A21)
L11
DNU
QK1
QK1
K11
K12
J12
DNU QK1# QK1#
DNU DNU DQ20
DNU DNU DQ20
DNU DQ16 DQ21
DNU DQ16 DQ21
DNU DNU DQ18
DNU DNU DQ18
DNU DQ17 DQ19
DNU DQ17 DQ19
BA0
A4
BA0
A4
J11
H11
H12
G12
G10
G11
E2
E3
E3
F2
F2
F3
F3
E1
T3
A3
A0
A2
A1
A3
A0
A2
A1
U2
U2
U3
U3
V2
A1
A20
A20 (A20) E12
QVLD QVLD QVLD F12
ZQ
ZQ
ZQ
DQ8 DQ13 DQ27 U10
DQ8 DQ13 DQ27 U10
DNU DNU DQ26 U11
DNU DNU DQ26 U11
DQ7 DQ12 DQ29 T10
DQ7 DQ12 DQ29 T10
DNU DNU DQ28 T11
DNU DNU DQ28 T11
DQ6 DQ11 DQ31 R10
DQ6 DQ11 DQ31 R10
DQ3
DQ3
DQ3
DQ3
DQ7
DQ7
F10
F10
F11
F11
E10
E10
E11
E11
D11
A5
A6
A7
A8
BA2
A9
NF
NF
A5
A6
A7
A8
BA2
A9
NF
NF
A5
A6
A7
A8
BA2
A9
F1
DNU DNU DQ6
DNU DNU DQ6
G2
G3
G1
H1
H2
J2
DQ2
DQ2
DQ2
DQ2
DQ5
DQ5
DNU DNU DQ4
DNU DNU DQ4
DK0#
DK0
QK0
QK0
QK0
J1
QK0# QK0# QK0# D10
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
ORDERING INFORMATION
Commercial Range: TC = 0° to +95°C
Frequency
Speed
Order Part No.
Organization
Package
533 MHz
1.875ns (tRC=15ns) IS49NLC96400A-18WBL
IS49NLC18320A-18WBL
64M x 9
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
32M x 18
16M x 36
IS49NLC36160A-18WBL
400 MHz
400 MHz
300 MHz
2.5ns (tRC=15ns)
2.5ns (tRC=20ns)
3.3ns (tRC=20ns)
IS49NLC96400A-25EWBL 64M x 9
IS49NLC18320A-25EWBL 32M x 18
IS49NLC36160A-25EWBL 16M x 36
IS49NLC96400A-25WBL
IS49NLC18320A-25WBL
IS49NLC36160A-25WBL
IS49NLC96400A-33WBL
IS49NLC18320A-33WBL
IS49NLC36160A-33WBL
64M x 9
32M x 18
16M x 36
64M x 9
32M x 18
16M x 36
Note: The -33 speed grade option is backward compatible with all timing specification for slower grades.
ORDERING INFORMATION
Industrial Range: TC = 40°C to 95°C; TA = 40°C to +85°C
Frequency
Speed
Order Part No.
Organization
Package
533 MHz
1.875ns (tRC=15ns) IS49NLC96400A-18WBLI
IS49NLC18320A-18WBLI
64M x 9
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
144 WBGA, Lead-free
32M x 18
16M x 36
IS49NLC36160A-18WBLI
400 MHz
400 MHz
300 MHz
2.5ns (tRC=15ns)
2.5ns (tRC=20ns)
3.3ns (tRC=20ns)
IS49NLC96400A-25EWBLI 64M x 9
IS49NLC18320A-25EWBLI 32M x 18
IS49NLC36160A-25EWBLI 16M x 36
IS49NLC96400A-25WBLI
IS49NLC18320A-25WBLI
IS49NLC36160A-25WBLI
IS49NLC96400A-33WBLI
IS49NLC18320A-33WBLI
IS49NLC36160A-33WBLI
64M x 9
32M x 18
16M x 36
64M x 9
32M x 18
16M x 36
Note: The -33 speed grade option is backward compatible with all timing specification for slower grades.
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IS49NLC96400A/IS49NLC18320A/IS49NLC36160A
Package drawing – 144-BALL WBGA
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相关型号：
IS49NLS18320-18BLI
DDR DRAM, 32MX18, 1.875ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144
ISSI
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