IS61C1024H-20K [ISSI]
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
| 型号： | IS61C1024H-20K |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61C1024H
128K x 8 HIGH-SPEED CMOS STATIC RAM
ISSI
JANUARY 1996
FEATURES
• High-speed access time: 15, 20, 25 ns
• Low active power: 750 mW (typical)
DESCRIPTION
The ISSI IS61C1024H is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM. They are fabricated
usingISSI'shigh-performanceCMOStechnology. Thishighly
reliable process coupled with innovative circuit design tech-
niques, yields higher performance and low power consump-
tion devices.
• Low standby power: 2 mW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
EasymemoryexpansionisprovidedbyusingtwoChipEnable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• Single 5V (±10%) power supply
The IS61C1024H is available in 32-pin 300-mil and 400-mil
plastic SOJ packages.
FUNCTIONAL BLOCK DIAGRAM
512 X 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1995, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
1
Rev. A 1/96
SR81995C024
®
IS61C1024H
ISSI
PIN CONFIGURATION
32-Pin SOJ
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
CE2
2
3
OE
4
WE
5
A6
6
I/O0-I/O7
Vcc
A5
7
A9
Power
A4
8
A11
OE
A3
9
GND
Ground
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A1
A0
I/O0
I/O1
I/O2
GND
OPERATING RANGE
(1)
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
TRUTH TABLE
Mode
WE
CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled H
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Read
Write
H
L
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
Temperature Under Bias
Storage Temperature
Power Dissipation
°C
°C
W
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
5
7
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
2
Integrated Silicon Solution, Inc.
Rev.A 1/96
SR81995C024
®
IS61C1024H
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
2.4
—
2.2
–0.3
–5
Max.
—
0.4
VCC + 0.5
Unit
V
V
V
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.8
5
5
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC, Outputs Disabled
µA
µA
ILO
Output Leakage
–5
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-15 ns
Min. Max.
-20 ns
Min. Max.
-25 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
VCC = Max.,
—
220
—
190
—
180
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
—
60
—
60
—
60
mA
VIN = VIH or VIL
CE1 ≥ VIH or
CE2 ≤ VIL, f = 0
ISB2
CMOS Standby
VCC = Max.,
—
50
—
50
—
50
mA
Current (CMOS Inputs)
CE1 ≥ VCC – 0.2V,
CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Integrated Silicon Solution, Inc.
3
Rev. A 1/96
SR81995C024
®
IS61C1024H
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-15 ns
Min.
-20 ns
Min.
-25 ns
Symbol Parameter
Max.
—
15
—
15
15
7
Max.
—
20
—
20
20
9
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
15
—
3
20
—
3
25
—
3
—
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
25
—
tOHA
tACE1
tACE2
tDOE
—
—
—
0
—
—
—
0
—
—
—
0
25
25
9
`
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
—
6
—
7
—
(2)
tHZOE
0
0
0
10
—
tLZCE1(2) CE1 to Low-Z Output
tLZCE2(2) CE2 to Low-Z Output
2
—
—
8
3
—
—
9
3
2
3
3
—
(2)
tHZCE
CE1 or CE2 to High-Z Output
0
0
0
10
—
(3)
tPU
CE1 or CE2 to Power-Up
0
—
12
0
—
18
0
(3)
tPD
CE1 or CE2 to Power-Down
—
—
—
20
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1a.
Figure 1b.
4
Integrated Silicon Solution, Inc.
Rev.A 1/96
SR81995C024
®
IS61C1024H
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
t
LZCE1/tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
t
PU
t
PD
ICC
ISB
50%
50%
SUPPLY
CURRENT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Silicon Solution, Inc.
5
Rev. A 1/96
SR81995C024
®
IS61C1024H
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-15 ns
Min.
-20 ns
-25 ns
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
7
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
—
25
20
20
20
0
—
tSCE1
tSCE2
tAW
CE1 to Write End
—
—
CE2 to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
—
tSA
0
0
—
0
—
(4)
tPWE
tSD
WE Pulse Width
10
8
12
10
0
—
15
12
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
tHD
0
—
—
(2)
tHZWE
—
2
—
2
10
—
—
2
12
—
(2)
tLZWE
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
DIN
6
Integrated Silicon Solution, Inc.
Rev.A 1/96
SR81995C024
®
IS61C1024H
ISSI
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
t
PWE
WE
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
SD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns) Order Part No.
Package
15
15
IS61C1024H-15J
300-mil Plastic SOJ
IS61C1024H-15K 400-mil Plastic SOJ
IS61C1024H-20J 300-mil Plastic SOJ
IS61C1024H-20K 400-mil Plastic SOJ
IS61C1024H-25J 300-mil Plastic SOJ
IS61C1024H-25K 400-mil Plastic SOJ
20
20
25
25
Integrated Silicon Solution, Inc.
7
Rev. A 1/96
SR81995C024
®
IS61C1024H
ISSI
300-mil Plastic SOIC (J-Bend)
Package Code: J
N
E1
E
1
SEATING PLANE
D
A
A2
S
b
C
e
B
A1
E2
300-mil Plastic SOIC (J-bend) (J)
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
28
32
A
A1
A2
B
b
C
D
E
E1
E2
e
0.128
0.020
0.095
0.016
0.026
0.008
0.700
0.321
0.292
0.245
0.140
0.030
0.105
0.022
0.032
0.014
0.730
0.347
0.305
0.285
—
0.140
—
0.020
0.095
0.016
0.026
0.008
0.815
0.325
0.295
0.247
0.105
0.022
0.032
0.014
0.835
0.345
0.305
0.287
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
0.050 BSC
0.023 0.045
0.050 BSC
0.023 0.035
S
8
Integrated Silicon Solution, Inc.
Rev.A 1/96
SR81995C024
®
IS61C1024H
ISSI
400-mil Plastic SOIC (J-Bend)
Package Code: K
N
E1
E
1
SEATING PLANE
D
A
S
b
C
A2
e
B
A1
E2
400-mil Plastic SOIC (J-bend) (K)
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
28
32
A
A1
A2
B
b
C
D
E
E1
E2
e
0.128
0.025
0.082
0.016
0.026
0.007
0.720
0.435
0.395
0.360
0.148
—
—
0.020
0.032
0.0125
0.730
0.445
0.405
0.380
0.131
0.025
0.082
0.013
0.024
0.006
0.820
0.430
0.395
0.354
0.145
—
—
0.021
0.032
0.012
0.830
0.445
0.405
0.380
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protru-
sions and should be measured from the bottom of the
package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
0.050 BSC
0.035
0.050 BSC
— 0.045
S
—
Integrated Silicon Solution, Inc.
9
Rev. A 1/96
SR81995C024
®
IS61C1024H
ISSI
NOTICE
Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits
arefreeofpatentinfringement. Chartsandschedulescontainedhereinreflectrepresentativeoperatingparameters,andmay
vary depending upon a user's specific application. While the information in this publication has been carefully checked,
Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission.
IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect
its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc.
receiveswrittenassurances, toitssatisfaction, that:(a)theriskofinjuryordamagehasbeenminimized;(b)theuserassumes
all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.
Copyright 1996 Integrated Silicon Solution, Inc.
Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.
Integrated Silicon Solution, Inc.
680 Almanor Avenue
Sunnyvale, CA 94086
Tel: (408) 733-4774
Fax: (408) 245-4774
10
Integrated Silicon Solution, Inc.
Rev.A 1/96
SR81995C024
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