IS61C256AH-15N [ISSI]

32K x 8 HIGH-SPEED CMOS STATIC RAM; 32K ×8高速CMOS静态RAM
IS61C256AH-15N
型号: IS61C256AH-15N
厂家: INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述:

32K x 8 HIGH-SPEED CMOS STATIC RAM
32K ×8高速CMOS静态RAM

存储 内存集成电路 静态存储器 光电二极管
文件: 总8页 (文件大小:64K)
中文:  中文翻译
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®
ISSI  
IS61C256AH  
32K x 8 HIGH-SPEED CMOS STATIC RAM  
MAY 1999  
FEATURES  
DESCRIPTION  
The ISSI IS61C256AH is a very high-speed, low power,  
32,768 word by 8-bit static RAMs. They are fabricated using  
ISSI's high-performance CMOS technology. This highly reli-  
able process coupled with innovative circuit design tech-  
niques, yields access times as fast as 10 ns maximum.  
• High-speed access time: 10, 12, 15, 20, 25 ns  
• Low active power: 400 mW (typical)  
• Low standby power  
— 250 µW (typical) CMOS standby  
— 55 mW (typical) TTL standby  
WhenCEisHIGH(deselected), thedeviceassumesastandby  
mode at which the power dissipation can be reduced down to  
250 µW (typical) with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
• TTL compatible inputs and outputs  
• Single 5V power supply  
Easy memory expansion is provided by using an active LOW  
ChipEnable(CE)inputandanactiveLOWOutputEnable(OE)  
input. The active LOW Write Enable (WE) controls both writing  
and reading of the memory.  
The IS61C256AH is pin compatible with other 32K x 8 SRAMs  
and are available in 28-pin PDIP, SOJ, and TSOP (Type I)  
packages.  
FUNCTIONAL BLOCK DIAGRAM  
32K X 8  
MEMORY ARRAY  
A0-A14  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which  
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
1
®
ISSI  
IS61C256AH  
PIN CONFIGURATION  
28-Pin DIP and SOJ  
PIN CONFIGURATION  
28-Pin TSOP  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
WE  
A13  
A8  
OE  
A11  
A9  
22  
23  
24  
25  
26  
27  
28  
1
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
A10  
CE  
2
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
GND  
I/O2  
I/O1  
I/O0  
A0  
3
A8  
A6  
4
A13  
WE  
VCC  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A5  
5
A9  
A4  
6
A11  
OE  
A3  
7
2
A2  
8
A10  
CE  
3
4
A1  
9
5
A0  
10  
11  
12  
13  
14  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
6
A1  
A2  
I/O0  
I/O1  
I/O2  
GND  
7
8
PIN DESCRIPTIONS  
TRUTH TABLE  
Mode  
WE  
CE OE I/O Operation Vcc Current  
A0-A14  
CE  
Address Inputs  
Not Selected  
(Power-down)  
X
H
X
High-Z  
ISB1, ISB2  
Chip Enable Input  
Output Enable Input  
Write Enable Input  
Bidirectional Ports  
Power  
OE  
Output Disabled H  
L
L
L
H
L
High-Z  
DOUT  
DIN  
ICC  
ICC  
ICC  
WE  
Read  
Write  
H
L
I/O0-I/O7  
Vcc  
X
GND  
Ground  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameter  
Value  
Unit  
V
VTERM  
TBIAS  
TSTG  
PT  
Terminal Voltage with Respect to GND  
Temperature Under Bias  
Storage Temperature  
–0.5 to +7.0  
–55 to +125  
–65 to +150  
1.5  
°C  
°C  
W
Power Dissipation  
IOUT  
DC Output Current (LOW)  
20  
mA  
Note:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of  
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended  
periods may affect reliability.  
2
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
®
ISSI  
IS61C256AH  
OPERATING RANGE  
Range  
Ambient Temperature  
Speed  
VCC  
Commercial  
0°C to +70°C  
-10, -12  
5V ± 5%  
-15, -20, -25  
5V ± 10%  
Industrial  
–40°C to +85°C  
-12  
5V ± 5%  
-15, -20, -25  
5V ± 10%  
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)  
Symbol Parameter  
Test Conditions  
Min.  
2.4  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
ILI  
Output HIGH Voltage  
VCC = Min., IOH = –4.0 mA  
VCC = Min., IOL = 8.0 mA  
0.4  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage(1)  
Input Leakage  
V
2.2  
–0.5  
–5  
VCC + 0.5  
0.8  
V
V
GND VIN VCC  
Com.  
5
µA  
Ind. –10  
10  
ILO  
Output Leakage  
GND VOUT VCC,  
Com.  
–5  
5
µA  
Outputs Disabled  
Ind. –10  
10  
Note:  
1. VIL = –3.0V for pulse width less than 10 ns.  
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)  
-10  
-12  
-15  
-20  
-25  
Symbol  
Parameter  
Test Conditions  
CC = Max., CE = VIL  
OUT = 0 mA, f = fMAX  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
ICC  
Vcc Dynamic Operating  
Supply Current  
V
I
Com.  
Ind.  
165  
155  
165  
145  
155  
135  
145  
125  
135  
mA  
I
SB  
SB  
1
TTL Standby Current  
(TTL Inputs)  
V
V
CC = Max.,  
IN = VIH or VIL  
Com.  
Ind.  
25  
25  
30  
25  
30  
25  
30  
25  
30  
mA  
CE VIH, f = 0  
CC = Max.,  
CE VCC – 0.2V,  
I
2
CMOS Standby  
Current (CMOS Inputs)  
V
Com.  
Ind.  
2
2
10  
2
10  
2
10  
2
10  
mA  
V
V
IN VCC – 0.2V, or  
IN 0.2V, f = 0  
Note:  
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.  
CAPACITANCE(1,2)  
Symbol  
CIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
8
Unit  
pF  
Input Capacitance  
Output Capacitance  
COUT  
VOUT = 0V  
10  
pF  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
3
®
ISSI  
IS61C256AH  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
-10  
-12  
-15  
-20  
-25  
Symbol  
Parameter  
Min. Max  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
RC  
Read Cycle Time  
Address Access Time  
Output Hold Time  
CE Access Time  
OE Access Time  
OE to Low-Z Output  
OE to High-Z Output  
CE to Low-Z Output  
CE to High-Z Output  
CE to Power-Up  
10  
2
10  
10  
5
12  
2
12  
12  
5
15  
2
15  
15  
7
20  
2
20  
20  
8
25  
2
25  
25  
9
AA  
OHA  
ACE  
DOE  
LZOE  
0
0
0
0
0
(2)  
(2)  
5
6
7
9
10  
10  
20  
HZOE  
2
3
3
3
3
(2)  
LZCE  
5
7
8
9
(2)  
HZCE  
0
0
0
0
0
(3)  
PU  
10  
12  
15  
18  
(3)  
PD  
CE to Power-Down  
Notes:  
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of  
0 to 3.0V and output loading specified in Figure 1.  
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
3. Not 100% tested.  
AC TEST CONDITIONS  
Parameter  
Unit  
0V to 3.0V  
3 ns  
Input Pulse Level  
Input Rise and Fall Times  
Input and Output Timing  
and Reference Levels  
1.5V  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
480 Ω  
480  
5V  
5V  
OUTPUT  
OUTPUT  
255 Ω  
255 Ω  
30 pF  
Including  
jig and  
5 pF  
Including  
jig and  
scope  
scope  
Figure 1  
Figure 2  
4
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
®
ISSI  
IS61C256AH  
AC WAVEFORMS  
READ CYCLE NO. 1(1,2)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
t
OHA  
DATA VALID  
DOUT  
PREVIOUS DATA VALID  
READ1.eps  
READ CYCLE NO. 2(1,3)  
t
RC  
ADDRESS  
OE  
t
AA  
t
OHA  
t
HZOE  
t
DOE  
t
t
LZOE  
ACE  
CE  
t
HZCE  
t
LZCE  
HIGH-Z  
DOUT  
DATA VALID  
CE_RD2.eps  
Notes:  
1. WE is HIGH for a Read Cycle.  
2. The device is continuously selected. OE, CE = VIL.  
3. Address is valid prior to or coincident with CE LOW transitions.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
5
®
ISSI  
IS61C256AH  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)  
-10  
-12  
-15  
-20  
-25  
Symbol Parameter  
Min. Max  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
t
t
t
WC  
SCE  
AW  
Write Cycle Time  
CE to Write End  
10  
9
12  
10  
10  
15  
10  
12  
20  
13  
15  
25  
15  
20  
ns  
Address Setup Time  
to Write End  
9
ns  
t
HA  
Address Hold  
from Write End  
0
0
0
0
0
ns  
t
t
t
t
t
t
t
SA  
Address Setup Time  
0
8
6
0
8
6
0
10  
8
7
0
13  
10  
10  
0
8
0
15  
12  
12  
0
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PWE  
PWE  
SD  
1
2
WE Pulse Width (OE LOW)  
WE Pulse Width (OE HIGH)  
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
6.5  
7
7
7
9
HD  
0
0
0
(2)  
HZWE  
0
0
0
0
0
(2)  
LZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and  
output loading specified in Figure 1.  
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,  
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling  
edge of the signal that terminates the write.  
AC WAVEFORMS  
WRITE CYCLE NO. 1 (WE Controlled)(1,2)  
t
WC  
VALID ADDRESS  
SCE  
ADDRESS  
CE  
t
SA  
t
t
HA  
t
AW  
t
t
PWE1  
PWE2  
WE  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
D
OUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
CE_WR1.eps  
6
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
®
ISSI  
IS61C256AH  
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)  
tWC  
ADDRESS  
OE  
VALID ADDRESS  
tHA  
LOW  
CE  
WE  
tAW  
tPWE1  
tSA  
tHZWE  
tLZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
DIN  
tSD  
tHD  
DATAIN VALID  
CE_WR2.eps  
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)  
t
WC  
ADDRESS  
VALID ADDRESS  
t
HA  
LOW  
LOW  
OE  
CE  
t
t
AW  
t
PWE2  
WE  
t
SA  
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
CE_WR3.eps  
Notes:  
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,  
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling  
edge of the signal that terminates the Write.  
2. I/O will assume the High-Z state if OE VIH.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  
7
®
ISSI  
IS61C256AH  
ORDERING INFORMATION: IS61C256AH  
ORDERING INFORMATION: IS61C256AH  
Industrial Range: –40°C to +85°C  
Commercial Range: 0°C to +70°C  
Speed (ns) Order Part Number  
Package  
Speed (ns) Order Part Number  
Package  
12  
15  
20  
25  
IS61C256AH-12NI  
IS61C256AH-12JI  
IS61C256AH-12TI  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
10  
12  
15  
20  
25  
IS61C256AH-10N  
IS61C256AH-10J  
IS61C256AH-10T  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-15NI  
IS61C256AH-15JI  
IS61C256AH-15TI  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-12N  
IS61C256AH-12J  
IS61C256AH-12T  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-20NI  
IS61C256AH-20JI  
IS61C256AH-20TI  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-15N  
IS61C256AH-15J  
IS61C256AH-15T  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-25NI  
IS61C256AH-25JI  
IS61C256AH-25TI  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-20N  
IS61C256AH-20J  
IS61C256AH-20T  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
IS61C256AH-25N  
IS61C256AH-25J  
IS61C256AH-25T  
300-mil Plastic DIP  
300-mil Plastic SOJ  
TSOP (Type 1)  
®
ISSI  
Integrated Silicon Solution, Inc.  
2231 Lawson Lane  
Santa Clara, CA 95054  
Tel: 1-800-379-4774  
Fax: (408) 588-0806  
E-mail: sales@issi.com  
www.issi.com  
8
Integrated Silicon Solution, Inc. — 1-800-379-4774  
SR020-1O  
05/24/99  

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