IS61FSCS51236-9B [ISSI]
Standard SRAM, 512KX36, 7.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209;
| 型号： | IS61FSCS51236-9B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 512KX36, 7.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器 内存集成电路 |
| 文件： | 总32页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61FSCS25672
IS61FSCS51236
®
ISSI
ADVANCE INFORMATION
SRAM 256K X 72, 512K X 36
18MB SYNCHRONOUS SRAM
JUNE 2002
FEATURES
• JEDEC SigmaRam pinout and package standard
• Single 1.8V power supply (VCC): 1.7V (min) to
1.9V (max)
• Dedicated output supply voltage (VCCQ): 1.8V
or 1.5V typical
• LVCMOS-compatible I/O interface
• Common data I/O pins (DQs)
• Single Data Rate (SDR) data transfers
• Late Write Flow Through read operations
• Burst and non-burst read and write operations,
selectable via dedicated control pin (ADV)
• Internally controlled Linear Burst address
sequencing during burst operations
Bottom View
• Full read/write coherency
• Byte write capability
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
• Single cycle deselect
• Single-ended input clock (CLK)
SIGMARAM FAMILY OVERVIEW
• Selectable output driver impedance via dedi-
cated control pin (ZQ)
The IS61FSCS series SRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
The implementations are 18,874,368-bit (18Mb) SRAMs.
These are the first in a family of wide, very low voltage CMOS
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking
systems.
• Depth expansion capability (2 or 4 banks) via
programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard
1149.1)
• 209 Ball (11x19), 1mm pitch, 14mm x 22mm Ball
Grid Array (BGA) package
ISSI’s SRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBTRAMs, LateWrite, orDoubleDataRate(DDR)SRAMs.
The logical differences between the protocols employed by
theseRAMshingemainlyonvariouscombinationsofaddress
bursting, output data registering and write cueing. SRAMs
allowausertoimplementtheinterfaceprotocolbestsuitedto
the task at hand.
This specific product is Common I/O, SDR, Flow Through
and in the family is identified as 1x1Lf.
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANDED INFORMATION Rev. 00A
1
06/13/02
IS61FSCS25672
IS61FSCS51236
®
ISSI
FUNCTIONAL DESCRIPTION
IS61FSCS series SRAMs are implemented with ISSI’s
high performance CMOS technology and are packaged in
a 209-Ball BGA.
Because SigmaRAM is a synchronous device, address,
data Inputs, and read/write control inputs are captured on
therisingedgeoftheinputclock.Writecyclesareinternally
self-timedandinitiatedbytherisingedgeoftheclockinput.
This feature eliminates complex off-chip write pulse gen-
eration required by asynchronous SRAMs and simplifies
input signal timing.
IS61NSCS25672 PINOUT
256K x 72 COMMON I/O—TOP VIEW
1
2
3
4
5
6
7
8
9
A
10
11
A
B
C
DQg
DQg
A
E2
A
ADV
A
E3
DQb
DQb
(16M)
(8M)
DQg
DQg
DQg
DQg
Bc
Bh
Bg
Bd
NC
NC
W
E1
A
Bb
Be
NC
Bf
Ba
DQb
DQb
DQb
DQb
NC
(128M)
NC
D
E
F
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQg
DQPc
DQc
DQc
DQc
DQc
NC
GND
NC
MCL
NC
GND
DQb
DQPf
DQf
DQb
DQPb
DQf
V
CCQ
VCCQ
VCC
VCC
VCC
VCCQ
VCCQ
GND
GND
GND
ZQ
EP2
EP3
M4
GND
GND
GND
G
H
J
V
CCQ
VCCQ
VCC
V
CC
VCCQ
VCCQ
DQf
DQf
GND
GND
GND
GND
GND
GND
DQf
DQf
V
CCQ
VCCQ
VCC
V
CC
VCCQ
VCCQ
DQf
DQf
K
L
CLK
NC
GND
VCC
GND
VCC
GND
MCL
M2
GND
NC
NC
NC
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
VCCQ
VCCQ
V
CC
VCCQ
VCCQ
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
M
N
P
R
T
GND
GND
M3
GND
GND
GND
VCCQ
VCCQ
MCH
MCL
V
CC
VCCQ
VCCQ
GND
GND
GND
GND
GND
V
CCQ
VCCQ
VCC
VCC
VCC
VCCQ
VCCQ
GND
NC
NC
A
NC
MCL
A
NC
NC
A
GND
NC
U
NC
NC
(64M)
(32M)
V
DQd
DQd
DQd
DQd
A
A
A
A
A1
A0
A
A
A
A
DQe
DQe
DQe
DQe
W
TMS
TDI
TDO
TCK
2
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ADVANCE INFORMATION Rev. 00A
06/13/02
IS61FSCS25672
IS61FSCS51236
®
ISSI
IS61NSCS51236 PINOUT
512K X 36 COMMON I/O—TOP VIEW
1
2
3
4
5
6
7
A
8
9
A
10
11
A
B
C
NC
NC
A
E2
A
(16M)
ADV
E3
DQb
DQb
DQb
DQb
NC
NC
NC
NC
Bc
NC
NC
Bd
A
(x36)
W
E1
A
Bb
NC
NC
NC
Ba
DQb
DQb
NC
(128M)
NC
D
E
F
NC
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
GND
NC
NC
MCL
NC
GND
DQb
NC
DQb
DQPb
NC
V
CCQ
VCCQ
VCC
VCC
VCC
VCCQ
VCCQ
DQc
DQc
DQc
DQc
NC
GND
GND
GND
ZQ
EP2
EP3
M4
GND
GND
GND
NC
G
H
J
V
CCQ
VCCQ
VCC
VCC
VCCQ
VCCQ
NC
NC
GND
GND
GND
GND
GND
GND
NC
NC
V
CCQ
VCCQ
VCC
VCC
VCCQ
VCCQ
NC
NC
K
L
CLK
NC
GND
MCL
M2
GND
NC
NC
NC
NC
NC
NC
V
CCQ
V
CCQ
VCC
VCC
V
CCQ
V
CCQ
DQa
DQa
DQa
DQa
DQPa
NC
DQa
DQa
DQa
DQa
NC
M
N
P
R
T
NC
NC
GND
GND
GND
M3
GND
GND
GND
NC
NC
V
CCQ
V
CCQ
VCC
MCH
MCL
VCC
V
CCQ
V
CCQ
NC
NC
GND
GND
GND
GND
GND
GND
DQPd
DQd
DQd
NC
V
CCQ
V
CCQ
VCC
VCC
VCC
V
CCQ
V
CCQ
DQd
DQd
GND
NC
NC
A
NC
MCL
A
NC
NC
A
GND
NC
NC
U
NC
NC
NC
NC
(64M)
(32M)
V
DQd
DQd
DQd
DQd
A
A
A
A
A1
A0
A
A
A
A
NC
NC
NC
NC
W
TMS
TDI
TDO
TCK
11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
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IS61FSCS25672
IS61FSCS51236
®
ISSI
PIN DESCRIPTION TABLE
Symbol
Pin Location
Description
Type
Comments
A
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W6, W7
Address
Input
—
A
B5
A6
Address
Advance
Input
Input
x36 version
Active High
ADV
Bx
B3, C9
B8, C4
B4, B9, C3, C8
K3
Byte Write Enable
Byte Write Enable
Byte Write Enable
Clock
Input
Active Low (all versions)
Bx
Input
Active Low (x36 and x72 versions)
Active Low (x72 version only)
Active High
Bx
Input
CK
DQ
Input
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
Data I/O
Input/Output
x36, and x72 versions
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
Data I/O
Data I/O
Input/Output
Input/Output
DQ
A1, A2, B1, B2, C1, C2,
D1, D2, E1, E10, F10,
F11, G10, G11, H10,
H11, J10, J11, L1, L2,
M1, M2, N1, N2, P1, P2,
R2, R11, T10, T11, U10,
U11, V10, V11, W10,
W11
x72 version only
E1
C6
A4, A8
G6, H6
W9
Chip Enable
Chip Enable
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Active Low
E2 & E3
EP2 & EP3
TCK
Programmable Active High or Low
Chip Enable Program Pin
Test Clock
—
Active High
TDI
W4
Test Data In
—
TDO
W8
Test Data Out
—
TMS
W3
Test Mode Select
Mode Control Pins
Must Connect Low
Must Connet high
—
M2, M3 & M4
MCL
L6, M6, J6
D6, K6, P6,T6
N6
Must tie to Low,Low, and High
—
—
MCH
4
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ADVANCE INFORMATION Rev. 00A
06/13/02
IS61FSCS25672
IS61FSCS51236
®
ISSI
PIN DESCRIPTION TABLE
Symbol
Pin Location
Description
Type
Comments
C5, D4, D5, D7, D8, K4,
K8, K9, T4, T5, T7,
T8, U3, U5, U7, U9
NC
No Connect
—
Not connected to die (all versions)
NC
NC
B5
C7
No Connect
No Connect
—
—
Not connected to die (x72 version)
Not connected to die (x72/x36 versions)
A1, A2, B1, B2, B4, B9,
C1, C2, C3, C8, D1, D2,
E1, E10, F10, F11, G10,
G11, H10, H11, J10, J11,
L1, L2, M1, M2, N1, N2,
P1, P2, R2, R11, T10,
T11, U10, U11, V10,
V11, W10, W11
NC
No Connect
—
Not connected to die (x36 version)
W
B6
Write
Input
Input
Active Low
E5, E6, E7, G5, G7,
J5, J7, L5, L7, N5,
N7, R5, R6, R7
VCC
Core Power Supply
1.8 V Nominal
E3, E4, E8, E9, G3, G4,
VCCQ
G8, G9, J3, J4, J8, J9 Output Driver Power Supply
L3, L4, L8, L9, N3, N4
Input
1.8 V or 1.5 V Nominal
N8, N9, R3, R4, R8, R9
D3, D9, F3, F4, F5, F7,
F8, F9, H3, H4, H5, H7,
GND
ZQ
H8, H9, K5, K7, M3, M4,
M5, M7, M8, M9, P3, P4,
P5, P7, P8, P9, T3, T9
Ground
Input
Input
—
F6
Output Impedance Control
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
Default = High
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ADVANCE INFORMATION Rev. 00A
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IS61FSCS25672
IS61FSCS51236
®
ISSI
BACKGROUND
ThecentralcharacteristicsoftheISSIΣRAMsarethatthey
areextremelyfastandconsumelittlepower.Becauseboth
operating and interface power is low, ΣRAMs can be
implemented in a wide (x72) configuration, providing very
high single package bandwidth (in excess of 20 Gb/s in
ordinary pipelined configuration) and very low random
access time (~6 ns). The use of very low voltage circuits in
the core and 1.8V or 1.5V interface voltages allow the
speed, power and density performance of ΣRAMs.
SigmaRAM standard. This data sheet covers the single
data rate (non-DDR), Flow Through Read SigmaRAM.
The character of the applications for fast synchronous
SRAMs in networking systems are extremely diverse.
ΣRAMs have been developed to address the diverse
needs of the networking market in a manner that can be
supported with a unified development and manufacturing
infrastructure. ΣRAMs address each of the bus protocol
options commonly found in networking systems. This
allows the ΣRAM to find application in radical shrinks and
speed-ups of existing networking chip sets that were
designed for use with older SRAMs, like the NBT and Late
Write, or Double Data Rate SRAMs, as well as with new
chip sets and ASIC’s that employ the Echo Clocks and
realize the full potential of the ΣRAMs.
Although the SigmaRAM family pinouts have been de-
signed to support a number of different common read and
write protocol options, not all SigmaRAM implementations
will support all possible protocols. The following timing
diagrams provide a quick comparison between read and
write protocols options available in the context of the
COMMON I/O SigmaRAM FAMILY MODE COMPARISON—LATE WRITE VS. DOUBLE LATE WRITE
DOUBLE LATE WRITE—PIPELINED READ (S1x1Dp). For reference only.
CK
Address
Control
DQ
A
R
B
C
R
D
E
R
F
W
W
W
QA
DB
QC
DD
QE
CQ
LATE WRITE—PIPELINED READ (S1x1Lp). For reference only.
CK
Address
Control
DQ
A
R
B
X
C
D
R
E
X
F
W
W
QA
DC
QD
DF
CQ
6
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ADVANCE INFORMATION Rev. 00A
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IS61FSCS25672
IS61FSCS51236
®
ISSI
DOUBLE DATA RATE WRITE—DOUBLE DATA RATE READ (S1x2Lp). For reference only.
CK
Address
Control
DQ
A
R
B
X
C
D
R
E
X
F
W
W
DC0
DC1
DF0
QA0
QA1
QD0
QD1
CQ
READ OPERATIONS
Flow through Read
WRITE OPERATIONS
Write operation occurs when the following conditions are
satisfied at the rising edge of clock: All three chip enables
(E1,E2,andE3)areactiveandthewriteenableinputsignal
(W) is asserted low.
Read operation is initiated when the following conditions
are satisfied at the rising edge of clock: All three chip
enables (E1, E2, and E3) are active, the write enable input
signal (W) is deasserted high, and ADV is asserted low.
The address presented to the address inputs is latched into
the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to output.
Data is taken at next rising edge, as a Late Write.
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ADVANCE INFORMATION Rev. 00A
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IS61FSCS25672
IS61FSCS51236
®
ISSI
SINGLE DATA RATE FLOW THROUGH READ
CLK
A
XX
C
D
E
Address
E1
F
W
QC
QD
QA
DQ
CQ
QE
Read
Read
Deselect
Read
Read
Read
FLOW THROUGH WRITE AND READ
CLK
A
B
Address
E1
C
D
W
QA
QC
DQ
CQ
DD
DB
Read
Write
Read
Write
8
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ADVANCE INFORMATION Rev. 00A
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IS61FSCS25672
IS61FSCS51236
®
ISSI
SPECIAL FUNCTIONS
Burst Cycles
Linear Burst Order
SRAMs provide an on-chip burst address generator that
can be utilized, if desired, to further simplify burst read or
write implementations. The ADV control pin, when driven
high, commands the SRAM to advance the internal ad-
dress counter and use the counter generated address to
read or write the SRAM. The starting address for the first
cycle in a burst cycle series is loaded into the SRAM by
driving the ADV pin low, into Load mode.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Note:
1. The burst counter wraps to initial state on the 5th rising edge
of clock.
Burst Order
The burst address counter wraps around to its initial state
after four addresses (the loaded address and three more)
have been accessed. SigmaRAMs always count in linear
burst order.
SIGMA FLOW THROUGH BURST READS WITH COUNTER WRAP-AROUND
CLK
A2
Address
XX
A1
XX
A2
XX
A3
XX
XX
A0
Internal
Address
A2
A3
Counter Wraps
E1
W
ADV
10
11
00
01
DQ
QA2
QA3
QA0
QA1
QA2
Read
Continue
Continue
Continue
Continue
Continue
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IS61FSCS25672
IS61FSCS51236
®
ISSI
FLOW THROUGH READ BANK SWITCH WITH E1 DESELECT
CLK
A
Address
D
E
XX
F
C
E1
E2 Bank 1
E2 Bank 2
DQ Bank 1
DQ Bank 2
QA
QD
QC
No Op
Read
Read
Read
Read
Read
Note:
E1 does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
OUTPUT DRIVER IMPEDANCE CONTROL
SigmaRAMs may be supplied with either selectable (high) impedance output drivers. The ZQ pin of SigmaRAMs supplied
with selectable impedance drivers, allows selection between ΣRAM nominal drive strength (ZQ low) for multi-drop bus
applications and low drive strength (ZQ floating or high) point-to-point applications. The impedance of the data and clock
output drivers in these devices can be controlled via the static input ZQ. When ZQ is tied "low", output driver impedance
is set to ~25 Ω. When ZQ is tied "high" or left unconnected, output driver impedeance is set to ~50Ω. See the DC Electrical
Characteristics section for further information. The SRAM requires 32K cycles of power-up time after VCC reaches its
operating range.
OUTPUT DRIVER CHARACTERISTICS - TBD
10
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IS61FSCS25672
IS61FSCS51236
®
ISSI
PROGRAMMABLE ENABLES
Programmability of E2 and E3 allows four banks of depth
expansion to be accomplished with no additional logic. By
programming the enable inputs of four SRAMs in binary
sequence (00, 01, 10, 11) and driving the enable inputs
with two address inputs, four SRAMs can be made to look
like one larger RAM to the system.
SRAMs feature two user-programmable chip enable inputs,
E2 and E3. The sense of the inputs, whether they function
as active low or active high inputs, is determined by the
state of the programming inputs, EP2 and EP3. For ex-
ample, if EP2 is held at VCC , E2 functions as an active high
enable.IfEP2isheldtoGND,E2functionsasanactivelow
chip enable input.
BANK ENABLE TRUTH TABLE
EP2
GND
GND
Vcc
EP3
GND
Vcc
E2
E3
Bank 0
Bank 1
Bank 2
Bank 3
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
GND
Vcc
Vcc
EXAMPLE FOUR BANK DEPTH EXPANSION SCHEMATIC
A0-An
E1
CLK
W
DQ0-DQn
Bank 3
Bank 0
Bank 1
Bank 2
A
0
-
A
n
-
2
A
0
-
A
n
-
2
A
0
-
A
n
-
2
A0-An-2
An-1
A
E3
E2
An-1
An-1
A
n
-
1
An
An
An
An
E1
E1
CLK
W
DQ
W
DQ
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IS61FSCS25672
IS61FSCS51236
®
ISSI
SYNCHRONOUS TRUTH TABLE
CLK
E
ADV
W
BW
Previous
Current Operation
DQ
DQ
(tn) (tn) (tn) (tn) (tn)
Operation
(tn)
(tn+1)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0®1
0®1
0®1
0®1
0®1
X
X
1
F
X
T
X
T
0
1
0
1
0
X
X
X
X
0
X
X
X
X
T
X
Bank Deselect
Bank Deselect (Continue)
Deselect
***
Hi-Z
***
Bank Deselect
X
Deselect
X
X
0
Deselect (Continue)
Hi-Z
***
Write
Dn
Loads new address
Stores DQx if BWx = 0
(tn)
0®1
0®1
0®1
0
X
X
T
X
X
0
1
1
0
X
X
F
T
F
X
Write (Abort)
Loads new address
No data stored
***
Hi-Z
Write
Write
Write Continue
Increments address by 1
Stores DQx if BWx = 0
Dn-1
(tn-1)
Dn
(tn)
Write Continue (Abort)
Increments address by 1
No data stored
Dn-1
(tn-1)
Hi-Z
0®1
0®1
0
T
X
0
1
1
X
X
X
Read
Loads new address
***
Qn
(tn)
X
X
Read
Read Continue
Increments address by 1
Qn-1
(tn-1)
Qn
(tn)
Notes
:
1. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
2. If one or more BWx = 0 then BW = “T” else BW = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement/output state are determined by the previous operation.
5. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. Up to 3 Continue operations may be initiated after iniating a Read or Write operation to burst transfer up to 4 distinct pieces of data per single
external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
12
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®
ISSI
READ/WRITE CONTROL STATE DIAGRAM
0,T,0,0
0,T,0,1
0,T,0,1
0,T,0,0
READ
WRITE
X,F,0,X
1,T,0,X
X,F,0,X
0,T,0,1
X,F,0,X or
1,T,0,X
0,T,0,0
X,X,1,X
X,X,1,X
X,X,1,X
BANK
DESELECT
0,T,0,1
0,T,0,0
0,T,0,0
0,T,0,1
X,F,0,X
1,T,0,X
X,X,1,X
X,F,0,X
READ
CONTINUE
WRITE
CONTINUE
0,T,0,1
X,X,1,X
1,T,0,X
X,F,0,X
1,T,0,X
1,T,0,X or
X,X,1,X
0,T,0,0
DESELECT
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
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ISSI
CURRENT STATE & NEXT STATE DEFINITION FOR READ/WRITE CONTROL STATE DIAGRAM
n
n+1
n+2
n+3
CK
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
KEY
Input Command Code
ƒ Transition
Current State (n)
Next State (n+1)
ABSOLUTE MAXIMUM RATINGS
(All voltages reference to GND )
Symbol
VCC
VCCQ
VI/O
VIN
Description
Value
Unit
V
Voltage on VCC Pins
Voltage in VCCQ Pins
Voltage on I/O Pins
–0.5 to 2.5
–0.5 to 2.3V
V
–0.5 to VCCQ +0.5 (≤ 2.3 V max.)
V
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any Pin
Maximum Junction Temperature
Storage Temperature
–0.5 to VCCQ +0.5 (≤ 2.3 V max.)
V
IIN
±100
±100
mA dc
mA dc
°C
IOUT
TJ
125
TSTG
-55 to 125
°C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Operation should be limited to Recom-
mended Operating Conditions. Exposure to conditions exceeding Recommended Operating Conditions, for an extended
period of time, may affect reliability of this component.
POWER SUPPLY CHARACTERISTICS (TA = 0 min., 25 typ, 70 max °C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
1.7
1.8
1.9
V
(1)
VCCQ
1.8 V I/O Supply Voltage
1.5 V I/O Supply Voltage
1.7
1.4
1.8
1.5
VCC
1.6 V
V
V
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VCCQ ≤ 1.6V
(i.e., 1.5 V I/O) and 1.7 V ≤ VCCQ ≤ 1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
14
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ISSI
CMOS I/O DC INPUT CHARACTERISTICS
Symbol
Parameter
VCCQ
Min.
Typ.
Max.
Unit
VIH
CMOS Input High Voltage
1.8
1.5
1.2
1.0
—
—
V
V
CCQ + 0.3
CCQ + 0.3
V
VIL
CMOS Input Low Voltage
1.8
1.5
–0.3
–0.3
—
—
0.6
0.5
V
Note:
For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
V
CC + 1.0V
GND
50%
50%
VCC
GND - 1.0V
20% tKC
VIL
I/O CAPACITANCE (TA = 25 °C, f = 1 MHZ)
Symbol
Parameter
Test conditions
Min.
Max.
Unit
CA
CB
CCK
Address
Control
Clock
Input Capacitance
Input Capacitance
Input Capacitance
VIN = 0 V
VIN = 0 V
VIN = 0 V
—
—
—
3.5
3.5
3.5
pF
pF
pF
CDQ
Data
Output Capacitance
VOUT = 0 V
—
4.5
pF
Note: These parameters are sampled and not 100% tested.
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ISSI
AC TEST CONDITIONS
(VCC = 1.8V ± 0.1V, TA = 0 to 85°C)
Parameter
Symbol
Conditions
Units
V
VCCQ
1.5V±0.1
1.8 ±0.1
1.4
Input High Level
VIH
VIL
1.25
0.25
V
Input Low Level
0.4
V
Input Rise & Fall Time
Input Reference Level
Clock Input High Voltage
Clock Input Low Voltage
Clock Input Rise & Fall Time
Clock Input Reference Level
Output Reference Level
Output Load Conditions ZQ = VIH
2.0
2.0
V/ns
V
0.75
0.9
VKIH
VKIL
1.25
1.4
V
0.25
0.4
V
2.0
2.0
V/ns
V
0.75
0.9
0.75
0.9
V
see below
see below
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown unless otherwise noted.
AC TEST LOADS
VCCQ = 1.5V
0.75V
VCCQ = 1.8V
0.9V
50Ω
50Ω
16.7Ω
16.7Ω
16.7Ω
16.7Ω
50Ω
50Ω
50Ω
50Ω
16.7Ω
16.7Ω
5 pF
5 pF
DQ
DQ
5 pF
50Ω
5 pF
50Ω
0.75V
0.9V
Figure 1 (VCCQ = 1.5V)
Figure 2 (VCCQ = 1.8V)
16
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ISSI
SELECTABLE IMPEDANCE OUTPUT DRIVER DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
IOHL = –4 mA
IOLL = 4 mA
Min.
VCCQ – 0.4
—
Max.
—
Units
(1)
VOHL
Low Drive Output High Voltage
Low Drive Output Low Voltage
High Drive Output High Voltage
High Drive Output Low Voltage
V
V
V
V
(1)
VOLL
0.4
—
(2)
VOHH
IOHH = –8 mA
IOLH = 8 mA
VCCQ – 0.4
—
(2)
VOLH
0.4
Notes:
1. ZQ = 1; High Impedance output driver setting
2. ZQ = 0; Low Impedance output driver setting
OUTPUT RESISTANCE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
ROUT
Output Resistance
VOH, VOL = VCCQ/2
17
25
33
Ω
ZQ = VIL
VOH, VOL = VCCQ/2
35
50
65
Ω
ZQ = VIH
OPERATING CURRENTS
Symbol
Parameter
Test Conditions
-7.2
-7.5
Units
Com. Ind.
Com. Ind.
ICC
Operating Current
E1 < VIL Max.
tKHKH > tKHKH Min.
All other inputs
VIL > VIN > VIH
Pipeline x72
x36
600
450
600
450
mA
ISB1
&
ISB2
Bank Deselect Current
&
Chip Disable Current
E1 < VIH Min. or
E2 or E3 False
tKHKH > tKHKH Min.
All other inputs
VIL > VIN > VIH
Pipeline x72
x36
250
225
250
225
mA
mA
ISB3
CMOS Deselect Current
Device Deselected
All inputs
Pipeline x72
x36
150
150
150
150
GND+0.10V > VIN > VCC–0.10V
Note: Com. = 0°C to 70°C
Ind. = –40°C to +85°C
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ISSI
OPERATING CURRENTS (continued)
Symbol
Parameter
Test Conditions
-8.0
-8.5
-9.0
Units
Com. Ind.
Com. Ind.
Com. Ind.
ICC
Operating Current
E1 < VIL Max.
tKHKH > tKHKH Min.
All other inputs
VIL > VIN > VIH
Pipeline x72
x36
500
350
500
350
500
350
mA
ISB1
&
ISB2
Bank Deselect Current
&
Chip Disable Current
E1 < VIH Min. or
E2 or E3 False
tKHKH > tKHKH Min.
All other inputs
VIL > VIN > VIH
Pipeline x72
x36
250
225
250
350
250
225
mA
mA
ISB3
CMOS Deselect Current
Device Deselected
All inputs
Pipeline x72
x36
150
150
150
150
150
150
GND+0.10V > VIN > VCC–0.10V
Note: Com. = 0°C to 70°C
Ind. = –40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V ±0.1V, GND = 0V, TA = 0° to 85°C)
Symbol
Parameter
Test Conditions
Min
-5
Typ
Max
5
Units
uA
ILI
Input Leakage Current
VIN = GND to VCCQ
—
(Address, Control, Clock)
IMLI
Input Leakage Current
(EP2, EP3, M2, M3, M4, ZQ)
VMIN = GND to VCC
VDIN = GND to VCCQ
-10
-10
—
—
10
10
uA
uA
IDLI
Input Leakage Current
(Data)
18
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AC ELECTRICAL CHARACTERISTICS
-7.2
Min Max
-7.5
Min Max
-8
Symbol
tKHKH
Parameter
Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
7.2
2.8
2.8
0.5
—
—
—
—
—
5.0
—
7.5
3.0
3.0
0.5
—
—
—
—
—
5.5
—
8.0
3.2
3.2
0.5
—
—
—
—
—
6.7
—
tKHKL
Clock HIGH Time
tKLKH
Clock LOW Time
tKHQX1(1)
Clock High to Output in Low-Z
Clock High to Output Valid
Clock High to Output Invalid
Clock High to Output in High-Z
Address Valid to Clock High
Clock High to Address Don’t Care
Enable Valid to Clock High
Clock High to Enable Don’t Care
Write Valid to Clock High
Clock High to Write Don’t Care
Byte Write Valid to Clock High
Clock High to Byte Write Don’t Care
Data In Valid to Clock High
Clock High to Data In Don’t Care
ADV Valid to Clock High
Clock High to ADV Don’t Care
tKHQV
tKHQX
1.0
1.0
1.0
(1)
tKHQZ
1.0 5.0
1.0 5.5
1.0 6.7
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tBVKH
tKHBX
tDVKH
tKHDX
tadvVKH
tKHadvX
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
—
—
—
—
—
—
—
—
—
—
—
—
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
—
—
—
—
—
—
—
—
—
—
—
—
0.8
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.8
0.5
—
—
—
—
—
—
—
—
—
—
—
—
Notes:
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage tKHCZ < tKHCX1.
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AC ELECTRICAL CHARACTERISTICS
-8.5
-9
Symbol
tKHKH
Parameter
Min Max
Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
8.5
3.4
3.4
0.5
—
—
—
—
—
7.2
—
7.2
—
—
—
—
—
—
—
—
—
—
—
—
9.0
3.6
3.6
0.5
—
—
—
—
—
7.5
—
7.5
—
—
—
—
—
—
—
—
—
—
—
—
tKHKL
Clock HIGH Time
tKLKH
Clock LOW Time
tKHQX1(1)
Clock High to Output in Low-Z
Clock High to Output Valid
Clock High to Output Invalid
Clock High to Output in High-Z
Address Valid to Clock High
Clock High to Address Don’t Care
Enable Valid to Clock High
Clock High to Enable Don’t Care
Write Valid to Clock High
Clock High to Write Don’t Care
Byte Write Valid to Clock High
Clock High to Byte Write Don’t Care
Data In Valid to Clock High
Clock High to Data In Don’t Care
ADV Valid to Clock High
Clock High to ADV Don’t Care
tKHQV
tKHQX
1.0
—
1.0
—
(1)
tKHQZ
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tBVKH
tKHBX
tDVKH
tKHDX
tadvVKH
tKHadvX
1.1
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
Notes:
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage tKHCZ < tKHCX1.
20
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TIMING PARAMETER KEY—FLOW THROGH READ CYCLE TIMING
t
KHKH
t
KHKL
CK
t
KHAX
t
KLKH
t
AVKH
C
D
E
t
KHQZ
t
KHQX
t
t
KHQV
KHQX1
DQ
QC
TIMING PARAMETER KEY—WRITE MODE CONTROL AND DATA IN TIMING
CK
t
KHAX
t
AVKH
A
B
A
C
t
AVKH
t
KHAX
E1,E2,E3
W, Bn, ADV
t
t
DVKH
KHDX
DA
DQ
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
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JTAG PORT OPERATION
Overview
three Data Registers (ID, Bypass, and Boundary Scan
Registers).
These devices provide a JTAG Test Access Port (TAP) and
Boundary Scan interface using a limited set of IEEE std.
1149.1 functions. This test mode is intended to provide a
mechanism for testing the interconnect between master
(processor, controller, etc.), SRAMs, other components,
and the printed circuit board.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG
port. The port is reset at power-up and will remain inactive
unless clocked. To assure normal operation of the RAM
with the JTAG Port unused, TCK should be tied Low, TDI
andTMSmaybeleftfloatingortiedtoVCC . TDOshouldbe
left unconnected.
In conformance with a subset of IEEE std. 1149.1, these
devices contain a TAP Controller and four TAP Registers.
The TAP Registers consist of one Instruction Register and
JTAG PIN DESCRIPTIONS
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
Test Mode Select
Test Data In
In
In
The TMS input is sampled on the rising edge of TCK. This is the command input
for the TAP controller. An undriven TMS input will produce the same result as a
logic one input level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the
serial registers placed between TDI and TDO. The register placed between TDI
andTDOisdeterminedbythestateoftheTAPControllerandtheinstructionthat
is currently loaded in the TAP Instruction Register (refer to the TAP Controller
State Diagram). An undriven TDI pin will produce the same result as a logic one
input level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP Controller. Output
changesinresponsetothefallingedgeofTCK.Thisistheoutputsideoftheserial
registers placed between TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered
while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
22
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JTAG PORT REGISTERS
Overview
Bypass Register
The JTAG registers, refered to as Test Access Port (TAP)
registers, areselected(oneatatime)viathesequencesof
1s and 0s applied to TMS as TCK is strobed. Each of the
TAP registers are serial shift registers that capture serial
input data on the rising edge of TCK and push serial data
out on the next falling edge of TCK. When a register is
selected, it is placed between the TDI and TDO pins.
The Bypass Register is a single-bit register that can be
placed between TDI and TDO. It allows serial test data to
bepassedthroughtheRAM’sJTAGPorttoanotherdevice
in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can
be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found
can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder
flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is
describedinthefollowingScanOrderTable. TheBoundaryScan
Register, under the control of the TAP Controller, is loaded with
the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO
pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to
activate the Boundary Scan Register.
Instruction Register
The Instruction Register holds the instructions that are
executed by the TAP controller when it is moved into the
Run, Test/Idle, or the various data register states. Instruc-
tionsare3bitslong.TheInstructionRegistercanbeloaded
when it is placed between the TDI and TDO pins. The
Instruction Register is automatically preloaded with the
IDCODE instruction at power-up or whenever the control-
ler is placed in Test-Logic-Reset state.
JTAG TAP BLOCK DIAGRAM
0
Bypass Register
2 1 0
Instruction Register
TDI
TDO
. . .
31 30 29
2 1 0
ID Code Register
. . . . .
n
2 1 0
Boundary Scan Register
TMS
TCK
Test Access Port (TAP) Controller
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IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
between the TDI and TDO pins when the controller is
moved into Shift-DR state. Bit 0 in the register is the LSB
and the first to reach TDO when shifting begins.
ID REGISTER CONTENTS
Die
Revision
Code
I/O
Configuration
ISSI Technology
JEDEC Vendor
ID Code
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
x72
9
0
8
1
7
1
6
0
5
1
4
0
3
1
2
0
1
1
0
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1
1
JTAG TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
0
1
Update DR
0
1
Update IR
0
24
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TAP CONTROLLER INSTRUCTION SET
Overview
When the TAP controller is placed in Capture-IR state, the
two least significant bits of the instruction register are
loadedwith001. WhenthecontrollerismovedtotheShift-IR
state, the Instruction Register is placed between TDI and
TDO. In this state the desired instruction is serially loaded
through the TDI input (while the previous contents are
shifted out at TDO). For all instructions, the TAP executes
newlyloadedinstructionsonlywhenthecontrollerismoved
to Update-IR state. The TAP instruction set for this device
is listed in the JTAG TAP Instruction Set Summary.
There are two classes of instructions defined in the Stan-
dard1149.1-1990;standard(public)instructions,anddevice
specific (private) instructions. Some public instructions are
mandatory for 1149.1 compliance. Optional public instruc-
tions must be implemented in prescribed ways. The TAP
on this device may be used to monitor all input and I/O
pads.ThisdevicewillnotperformINTESTbutcanpreform
thepreloadportionoftheSAMPLE/PRELOADcommand.
JTAG TAP INSTRUCTION SET SUMMARY
Instruction
Code
Description
EXTEST(1)
000
Places the Boundary Scan Register between TDI and TDO. When EXTEST is
selected, data will be driven out of the DQ pad.
IDCODE(1,2)
001
010
Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z(1)
Captures I/O ring contents. Places the Boundary Scan Register between TDI
and TDO. Forces all Data and Clock output drivers to High-Z.
RFU(1)
011
Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruc-
tion. Places Bypass Register between TDI and TDO.
SAMPLE/PRELOAD(1) 100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Private instruction.
Private(1)
RFU(1)
101
110
111
Do not use this instruction; Reserved for Future Use.
Places Bypass Register between TDI and TDO.
BYPASS(1)
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
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JTAG DC RECOMMENDED OPERATING CONDITIONS (TA = 0 to 85°C)
Symbol
VTIH
Parameter
Test Conditions
Min.
1.2
Max.
VCC +0.3
0.6
Unit
V
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Voltag
VTIL
-0.3
V
VTOH
CMOS
TTL
ITOH = -100µΑ
ITOH = -8mΑ
VCC-0.1
VCC-0.4
—
—
V
VTOL
JTAG Output Low Voltage
CMOS
TTL
ITOL = 100µΑ
ITOL = 8mΑ
—
—
0.1
0.4
V
ITLI
JTAG Input Leakage Current
VTIN=GND to VCC
-10
10
µΑ
JTAG AC TEST CONDITIONS (VCC = 1.8V ±0.1V, TA = 0 to 85°C)
Symbol
VTIH
Parameter
Test Conditions
Unit
V
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Input Rise & Fall Time
JTAG Input Reference Level
1.6
0.2
1.0
0.9
VTIL
V
V/ns
V
JTAG Output Reference Level
JTAG Output Load Condition
0.9
V
see AC TEST LOADS
26
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JTAG PORT AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Min
20
8
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tDVTH
tTHDX
tTLQV
tTLQX
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Setup Time
TMS Hold Time
TDI Set Up Time
—
8
—
5
—
5
—
5
—
TDI Hold Time
5
—
TCK Low to TDO Valid
TCK Low to TDO Hold
—
0
10
—
JTAG PORT TIMING DIAGRAM
t
THTL
t
TLTH
tTHTH
TCK
TMS
t
MVTH tTHMX
t
DVTH
tTHDX
TDI
TDO
t
TLQX
TLQV
t
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INSTRUCTION DESCRIPTIONS
BYPASS
Typically, the Boundary Scan Register is loaded with the
desired pattern of data with the SAMPLE/PRELOAD com-
mand. Then the EXTEST command is used to output the
Boundary Scan Register’s contents, in parallel, on the
RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
When the BYPASS instruction is loaded to the Instruction
Register, the Bypass Register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
Shift-DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
Alternately, the Boundary Scan Register may be loaded in
parallel using the EXTEST command. When the EXTEST
instruction is selected, the state of all the RAM’s input and
I/O pins, as well as the default values at Scan Register
locations not associated with a pin (pin marked NC), are
transferred in parallel into the Boundary Scan Register on
the rising edge of TCK in the Capture-DR state. Boundary
ScanRegistercontentsmaythenbeshiftedseriallythrough
the register using the Shift-DR command or the controller
can be skipped to the Update-DR command. When the
controllerisplacedintheUpdate-DRstate,aRAMthathas
fullycompliantEXTESTfunctiondrivesoutthevalueofthe
Boundary Scan Register location associated with each
output pin.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller
intotheCapture-DRstateloadsthedataintheRAMsinput
and I/O buffers into the Boundary Scan Register. Some
Boundary Scan Register locations are not associated with
an input or I/O pin, and are loaded with the default state
identified in the BSDL file. Because the RAM clock is
independentfromtheTAPClock(TCK)itispossibleforthe
TAP to attempt to capture the I/O ring contents while the
input buffers are in transition (i.e. in a metastable state).
AlthoughallowingtheTAPtosamplemetastableinputswill
not harm the device, repeatable results cannot be ex-
pected. RAM input signals must be stabilized for long
enough to meet the TAP’s input data capture set-up plus
hold time (tTS plus tTH ). The RAM’s clock inputs need not
be paused for any other TAP operation except capturing
the I/O ring contents into the Boundary Scan Register.
Moving the controller to Shift-DR state then places the
Boundary Scan Register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
to the ID register when the controller is in Capture-DR
modeandplacestheIDregisterbetweentheTDIandTDO
pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in at power up and any time the
controller is placed in the Test-Logic-Reset state.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction.
It is to be executed whenever the instruction register is
loaded with all logic 0s. The EXTEST command does not
block or override the RAM’s input pins; therefore, the
RAM’s internal state is still determined by its input pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded to the instruction
register, all RAM outputs are forced to inactive state (high-
Z) and the Boundary Scan Register is connected between
TDIandTDOwhentheTAPcontrollerismovedtotheShift-
DR state.
RFU
These instructions are reserved for future use. In this
device they replicate the BYPASS instruction.
28
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BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) PH =Place Holder
X72
Ball Loc.
X36
Sequence
Pkg. Ball
Sequence
Pkg. Ball
1
A0
W6
V7
V8
U8
V9
U6
U5
W7
U7
T6
M6
J6
1
A0
2
A
2
A
3
A
3
A
4
A
4
A
5
A
5
A
6
A
6
A
(1)
(1)
7
PH
7
PH
8
A
8
A
(1)
(1)
9
PH
9
PH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
MCL
M3
10
11
12
13
14
15
MCL
M3
M4
M4
MCL
MCL
K6
D6
C7
C8
C9
B8
B9
B6
A6
B7
A8
A9
F6
A3
A4
A5
A7
B5
B3
B4
C3
C4
C5
C6
G6
H6
K3
L6
MCL
MCL
(1)
(1)
PH
PH
Be
Ba
Bb
Bf
16
17
Ba
Bb
W
18
19
20
21
22
23
24
25
26
27
28
29
W
ADV
A
ADV
A
E3
A
E3
A
ZQ
A
ZQ
A
E2
A
E2
A
A
A
AO36
Bc
30
31
32
33
34
35
36
37
38
39
Bc
Bg
Bh
Bd
30
31
32
33
34
35
36
Bd
(1)
(1)
PH
PH
CE1
CP2
CP3
CK
CE1
CP2
CP3
CK
M2
M2
Note:
1. Input of PH register connected to Vss.
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BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:
X72
Ball Loc.
X36
Sequence
Pkg. Ball
NC
Sequence
Pkg. Ball
NC
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
N6
P6
V3
U4
V4
V5
W5
V6
W2
W1
V2
V1
U2
U1
T2
T1
R1
R2
P2
P1
N2
N1
M2
M1
L2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
MCL
A
MCL
A
A
A
A
A
A
A
A
A
A1
A1
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
DQPh
DQh
DQh
DQh
DQh
DQh
DQh
DQh
DQh
NC
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
L1
K2
K1
J2
54
55
56
57
58
59
60
61
62
63
64
NC
NC
NC
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQPc
DQPg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQPc
J1
H2
H1
G2
G1
F2
F1
E2
E1
D2
D1
C2
C1
30
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®
ISSI
BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:
X72
Ball Loc.
X36
Sequence
Pkg. Ball
Sequence
Pkg. Ball
82
83
DQg
DQg
DQg
DQg
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
DQPf
DQf
B2
B1
84
A2
85
A1
86
A10
A11
B10
B11
C10
C11
D10
D11
E11
E10
F10
F11
G10
G11
H10
H11
J10
J11
K11
K10
L10
L11
M10
M11
N10
N11
P10
P11
R10
R11
T10
T11
U10
U11
V10
V11
W10
W11
65
66
67
68
69
70
71
72
73
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
87
88
89
90
91
92
93
94
95
96
97
DQf
98
DQf
99
DQf
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQf
DQf
DQf
DQf
NC
74
75
76
77
78
79
80
81
82
83
84
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa8
DQPa9
DQPe1
DQe2
DQe3
DQe4
DQe5
DQe6
DQe7
DQe8
DQe9
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa8
DQPa9
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ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Cycle Time
Order Part No.
Package
256K x 72
9
IS61FSCS25672-9B
IS61FSCS25672-8.5B
IS61FSCS25672-8B
IS61FSCS25672-7.5B
IS61FSCS25672-7.2B
IS61FSCS51236-9B
IS61FSCS51236-8.5B
IS61FSCS51236-8B
IS61FSCS51236-7.5B
IS61FSCS51236-7.2B
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
209-Ball BGA
8.5
8
7.5
7.2
9
512K x 36
8.5
8
7.5
7.2
Industrial Range: -40°C to 85°C
FrequencySpeed (ns) Order Part No.
Package
TBD
32
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