IS61LF51218D-6.5TQI [ISSI]
Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | IS61LF51218D-6.5TQI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
61LF25632T/D/J
IS
IS61LF25636T/D/J IS61LF51218T/D/J ISSI
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW THROUGH
OCTOBER 2002
-
STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are
high-speed, low-power synchronous static RAMs designed to
provide a burstable, high-performance and memories for
commucationandnetworkingapplications.TheIS61LF25632
isorganizedas262,144wordsby32bitsandtheIS61LF25636
isorganizedas262,144wordsby36bits.TheIS61LF51218is
organized as 524,288 words by 18 bits. Fabricated with ISSI's
advanced CMOS technology, the device integrates a 2-bit
burstcounter,high-speedSRAMcore,andhigh-drivecapability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers that are controlled by a positive-edge-
triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global
Write
• Clock controlled, registered address, data
and control
• Interleaved or linear burst sequence control
using MODE input
•
Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
Writecyclesareinternallyself-timedandareinitiatedbytherising
edgeoftheclockinput.Writecyclescanbefromonetofourbytes
wide as controlled by the write control inputs.
• JEDEC 100-Pin TQFP and
119-pin PBGA package
Separatebyteenablesallowindividualbytestobewritten.Byte
write operation is performed by using byte write enable
(BWE).input combined with one or more individual byte write
signals (BWx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
controls.
• Power Supply
+ 3.3V VDD
+ 3.3V or 2.5V VDDQ (I/0)
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• J version (PBGA Package with JTAG)
• D version (two chip selects)
• JTAG Boundary Scan for PBGA.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins.Subsequentburstaddressescanbegeneratedinternally
and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear
burst is achieved when this pin is tied LOW. Interleave burst is
achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
1
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
BLOCK DIAGRAM
MODE
Q0
A0'
A1'
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
256K x 32; 256K x 36;
512K x 18
ADSC
ADSP
CLR
MEMORY ARRAY
18/19
16/17
18/19
A
D
Q
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
BWd
(x32/x36)
DQd
BYTE WRITE
REGISTERS
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BWc
(x32/x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BWb
(x32/x36/x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
CE (T,D)
CE2 (T,D)
CE2 (T)
32, 36,
or 18
4
INPUT
REGISTERS
D
Q
DQa - DQd
ENABLE
OE
REGISTER
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) (D Version)
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
A
B
C
D
E
F
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
VDDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
NC
NC
CE2
A
A
A
NC
NC
GND
DQb
DQb
DQb
DQb
GND
A
VDD
A
A
DQc
DQc
NC
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
VDDQ
V
DDQ
DQc
DQc
NC
V
DDQ
OE
VDDQ
DQb
DQb
GND
NC
G
H
J
DQc
DQc
ADV
GW
DQb
DQb
V
DD
VDD
NC
GND
DQd
DQd
ZZ
DQa
DQa
V
DDQ
VDD
VDD
VDD
VDDQ
K
L
DQd
DQd
DQd
DQd
DQd
DQd
NC
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
GND
A
DQa
DQa
DQa
DQa
NC
DQa
DQa
VDDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
M
N
P
R
T
V
DDQ
BWE
A1
VDDQ
DQd
DQd
NC
DQa
DQa
NC
A0
VDDQ
V
DDQ
DQd
DQd
NC
DQa
DQa
NC
A
V
DD
A
NC
NC
A
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
256K x 32
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
SynchronousChipEnable
OutputEnable
CE, CE2
OE
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
CLK
ADSP
SynchronousProcessorAddress
Status
GND
Ground
ADSC
Synchronous Controller Address
Status
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
3
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
VDDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
GND
DQb
DQb
DQb
DQb
GND
VDDQ
V
DDQ
DQc
DQc
NC
DQb
DQb
GND
NC
V
DD
VDD
NC
GND
DQd
DQd
ZZ
DQa
DQa
VDDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
VDDQ
V
DDQ
DQd
DQd
NC
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
Synchronous Controller Address
Status
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWa-BWd
BWE
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
100-pin TQFP (T Version)
100-Pin TQFP (D Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
DQPc
DQc
DQc
V
DDQ
VDDQ
VDDQ
VDDQ
GND
DQb
DQb
DQb
DQb
GND
GND
DQc
DQc
DQc
DQc
GND
GND
DQb
DQb
DQb
DQb
GND
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
V
DDQ
DQc
DQc
NC
V
DDQ
V
DDQ
DQc
DQc
NC
DQb
DQb
GND
NC
DQb
DQb
GND
NC
V
DD
V
DD
V
ZZ
DD
NC
GND
DQd
DQd
V
DD
NC
GND
DQd
DQd
ZZ
DQa
DQa
DQa
DQa
V
DDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
V
DQa
DDQ
VDDQ
DQd
DQd
DQPd
V
DDQ
VDDQ
DQa
DQPa
DQa
DQa
DQPa
DQd
DQd
DQPd
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
256K x 36
PIN DESCRIPTIONS
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
A
Synchronous Address Inputs
SynchronousClock
CE, CE2
OE
SynchronousChipEnable
OutputEnable
CLK
ADSP
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
5
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
PIN CONFIGURATION
119-pin PBGA (Top View) (J Version)
119-pin PBGA (Top View) (D Version)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
NC
NC
CE2
A
A
A
NC
NC
NC
NC
CE2
A
A
A
NC
NC
A
V
DD
A
A
A
VDD
A
A
DQc
DQc
DQPc
DQc
DQc
DQc
DQc
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQc
DQc
DQPc
DQc
DQc
DQc
DQc
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
V
DDQ
OE
VDDQ
V
DDQ
DQc
DQc
OE
VDDQ
G
H
J
G
H
J
DQc
DQc
ADV
GW
DQb
DQb
ADV
GW
DQb
DQb
V
DDQ
V
DD
VDD
VDD
VDDQ
V
DDQ
DQd
DQd
VDD
VDD
VDD
VDDQ
K
L
K
L
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
A
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
GND
A
DQa
DQa
DQa
DQa
DQPa
A
DQa
DQa
DQd
DQd
DQd
DQd
DQPd
A
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
GND
A
DQa
DQa
DQa
DQa
DQPa
A
DQa
DQa
M
N
P
R
T
M
N
P
R
T
V
DDQ
BWE
A1
VDDQ
VDDQ
BWE
A1
VDDQ
DQd
DQd
NC
DQa
DQa
NC
DQd
DQd
NC
DQa
DQa
NC
A0
A0
V
DD
VDD
NC
NC
A
NC
ZZ
NC
NC
A
NC
ZZ
U
U
V
DDQ
TMS
TDI
TCK
TDO
NC
VDDQ
V
DDQ
NC
NC
NC
NC
NC
VDDQ
256K x 36
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
GW
SynchronousGlobalWriteEnable
A
Synchronous Address Inputs
SynchronousClock
CE, CE2
OE
SynchronousChipEnable
OutputEnable
CLK
ADSP
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) (J Version)
119-pin PBGA (Top View) (D Version)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
NC
NC
CE2
A
A
A
A
NC
NC
NC
NC
CE2
A
A
A
A
NC
NC
A
V
DD
A
A
V
DD
A
DQb
NC
NC
DQb
NC
DQb
NC
GND
GND
GND
BWb
GND
NC
NC
CE
GND
GND
GND
GND
GND
NC
DQPa
NC
NC
DQb
NC
NC
DQb
NC
DQb
NC
GND
GND
GND
BWb
GND
NC
NC
CE
GND
GND
GND
GND
GND
NC
DQPa
NC
NC
DQa
DQa
V
DDQ
OE
DQa
NC
VDDQ
V
DDQ
OE
DQa
NC
VDDQ
G
H
J
G
H
J
NC
ADV
GW
DQa
NC
NC
ADV
GW
DQa
NC
DQb
DQa
DQb
DQa
V
DDQ
V
DD
V
DD
V
DD
VDDQ
V
DDQ
V
DD
VDD
VDD
VDDQ
K
L
K
L
NC
DQb
NC
GND
GND
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
GND
A
NC
DQa
NC
DQa
NC
A
DQa
NC
NC
DQb
NC
GND
GND
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
GND
A
NC
DQa
NC
DQa
NC
A
DQa
NC
DQb
DQb
M
N
P
R
T
M
N
P
R
T
V
DDQ
DQb
NC
BWE
A1
VDDQ
VDDQ
DQb
NC
BWE
A1
VDDQ
DQb
NC
NC
DQa
NC
DQb
NC
NC
DQa
NC
DQPb
A
A0
DQPb
A
A0
NC
VDD
NC
VDD
NC
A
NC
A
ZZ
NC
A
NC
NC
A
ZZ
U
U
V
DDQ
TMS
TDI
TCK
TDO
NC
VDDQ
V
DDQ
NC
NC
NC
NC
VDDQ
512K x 18
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
GW
SynchronousGlobalWriteEnable
A
Synchronous Address Inputs
SynchronousClock
CE, CE2
SynchronousChipEnable
OutputEnable
CLK
ADSP
OE
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
7
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
PIN CONFIGURATION
100-Pin TQFP (D Version)
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
GND
NC
DQPa
DQa
DQa
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
A
NC
NC
V
GND
NC
DQPa
DQa
DQa
GND
NC
NC
NC
DDQ
V
DDQ
DDQ
V
DDQ
GND
NC
NC
DQb
DQb
GND
DDQ
DQb
DQb
GND
GND
NC
NC
DQb
DQb
GND
DDQ
DQb
DQb
GND
V
DDQ
V
V
DDQ
V
DQa
DQa
GND
NC
V
ZZ
DQa
DQa
V
GND
DQa
DQa
NC
NC
GND
V
NC
NC
NC
DQa
DQa
GND
NC
V
ZZ
DQa
DQa
V
GND
DQa
DQa
NC
NC
GND
V
NC
NC
NC
V
DD
V
DD
DD
NC
GND
DQb
DQb
DDQ
GND
DQb
DQb
DQPb
NC
DD
NC
GND
DQb
DQb
DDQ
GND
DQb
DQb
DQPb
NC
DDQ
V
DDQ
V
GND
GND
DDQ
V
DDQ
NC
NC
NC
DDQ
V
DDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 18
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
GW
SynchronousGlobalWriteEnable
A
Synchronous Address Inputs
SynchronousClock
CE, CE2, CE2 SynchronousChipEnable
CLK
ADSP
OE
OutputEnable
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
TRUTHTABLE
Address
Operation
Used
CE
CE2
CE2 ADSP ADSC ADV WRITE OE
DQ
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
None
None
None
None
None
External
External
External
Next
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
Q
X
L
L
X
L
X
L
H
H
L
X
L
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
Q
L
L
L
D
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
D
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
H
H
H
H
H
H
Q
H
L
High-Z
Q
H
X
X
High-Z
D
D
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
9
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VDDQ or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
Parameter
Value
–55 to +150
1.6
Unit
°C
W
StorageTemperature
PowerDissipation
OutputCurrent(perI/O)
PD
IOUT
100
mA
V
VIN, VOUT
VIN
Voltage Relative to GND for I/O Pins
–0.5 to VDDQ + 0.3
–0.5 to VDD + 0.5
Voltage Relative to GND for
for Address and Control Inputs
V
VDD
Voltage on Vdd Supply Relatiive to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
OPERATING RANGE
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V, +10%, –5%
2.375–3.6V
Industrial
–40°Cto+85°C
3.3V, +10%, –5%
2.375–3.6V
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
TestConditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
IOH = –1.0 mA, VDDQ = 2.5V
IOH = –4.0 mA, VDDQ = 3.3V
2.0
2.4
—
—
V
V
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
IOL = 1.0 mA, VDDQ = 2.5V
IOL = 8.0 mA, VDDQ = 3.3V
—
—
0.4
0.4
V
V
VDDQ = 2.5V
VDDQ = 3.3V
1.7
2.0
VDD + 0.3
VDD + 0.3
V
V
VDDQ = 2.5V
VDDQ = 3.3V
–0.3
–0.3
0.7
0.8
V
V
(2)
InputLeakageCurrent
OutputLeakageCurrent
GND ≤ VIN ≤ VDDQ
Com.
Ind.
–5
–5
5
5
µA
ILO
GND ≤ VOUT ≤ VDDQ, OE = VIH
Com.
Ind.
–5
–5
5
5
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
6.5
7.5
Symbol Parameter
Test Conditions
Max.
Max.
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
Com.
Ind.
110
120
100
110
mA
mA
All Inputs < VIL or > VIH
OE = VIH, ZZ < VIL
Cycle Time ≥ tKC min.
Standby Current
Device Deselected,
VDD = Max.,
All Inputs < VIL or > VIH
ZZ < VIL, f = fmax
Com.
Ind.
55
60
55
60
mA
mA
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
30
40
30
40
mA
mA
VIN
≤ GND + 0.2V or ≥ VDD -0.2V
f = 0
Notes:
1. The MODE pin should be tied to VDD or GND. It exhibits ±30 µA maximum leakage current when tied to< GND + 0.2V
or ≥ VDD – 0.2V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
11
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
351 Ω
1.5V
Figure 2
Figure 1
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
13
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
6.5
7.5
Symbol Parameter
Min. Max.
Min. Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMAX
tKC
ClockFrequency
—
7.5
2.2
2.2
—
133
—
—
8.5
2.5
2.5
—
117
—
Cycle Time
tKH
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
—
—
tKL
—
—
tKQ
tKQX
6.5
—
7.5
—
(1)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
2
2
(1,2)
(1,2)
tKQLZ
0
—
0
—
tKQHZ
tOEQ
—
3.5
3.5
—
—
3.5
3.5
—
—
—
(1,2)
tOELZ
tOEHZ
tAS
0
0
(1,2)
—
3.5
—
—
3.5
—
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
tSS
Address Status Setup Time
Write Setup Time
—
—
tWS
—
—
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
—
—
—
—
—
—
tSH
Address Status Hold Time
Write Hold Time
—
—
tWH
tCEH
tAVH
—
—
Chip Enable Hold Time
Address Advance Hold Time
—
—
—
—
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
t
SS
tSH
t
SS
tSH
ADV
A
t
AS
tAH
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
t
WS
tWH
WR1
BWd-BWa
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
t
OEHZ
OE
t
KQX
t
OEQX
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQX
KQHZ
t
KQ
t
High-Z
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Flow-through
Unselected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
15
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
6.5
7.5
Symbol
tKC
Parameter
Min. Max.
Min. Max.
Unit
Cycle Time
7.5
2.0
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKH
Clock High Pulse Width
Clock Low Pulse Width
Address Setup Time
Address Status Setup Time
Write Setup Time
tKL
tAS
tSS
tWS
tDS
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
tCES
tAVS
tAH
tSH
Address Status Hold Time
Data In Hold Time
tDH
tWH
tCEH
tAVH
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
A17-A0
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BWd-BWa
WR1
WR2
CE1 Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
17
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
ISB2
CurrentduringSLEEPMODE
ZZ ≥ VIH
ZZ ≥ VIH
Com.
Ind.
—
—
30
40
mA
tPDS
tPUS
tZZI
ZZ active to input ignored
2
2
2
0
—
—
—
—
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
tRZZI
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
18
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Rev. A
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IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP) - Test Clock
TheIS61LF25636T/D/Jand IS61LF51218T/D/JT/D/JT/D/
JhaveaserialboundaryscanTestAccessPort(TAP)inthe
PBGA package only. (Not available in TQFP package or
withtheIS61LPS25632T/D/J.)Thisportoperatesinaccor-
dance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
oftheSRAM.TheTAPcontrolleroperatesinamannerthat
does not conflict with the performance of other devices
using1149.1fullycompliantTAPs.TheTAPoperatesusing
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All
inputsarecapturedontherisingedgeofTCKandoutputs
are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information to the
registersandcanbeconnectedtotheinputofanyregister.
The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
canbedisconnectediftheTAPisunusedinanapplication.
TDI is connected to the Most Significant Bit (MSB) on any
register.
Disabling the JTAG Feature
TheSRAMcanoperatewithoutusingtheJTAGfeature.To
disable the TAP controller, TCK must be tied LOW (GND)
to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to VDD through a pull-up resistor.
TDOshouldbeleftdisconnected.Onpower-up,thedevice
will start in a reset state which will not interfere with the
deviceoperation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.A
19
10/06/02
IS61LF25632T/D/J
®
IS61LF25636T/D/J IS61LF51218T/D/J
ISSI
Boundary Scan Register
Test Data Out (TDO)
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect(NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register and the x18 configuration has a 51-bit-long regis-
ter. Theboundaryscanregisterisloadedwiththecontents
of the RAM Input and Output ring when the TAP controller
isintheCapture-DRstateandthenplacedbetweentheTDI
and TDO pins when the controller is moved to the Shift-DR
state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z
instructions can be used to capture the contents of the
Input and Output ring.
The TDO output pin is used to serially clock data-out from
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
TAP Registers
Registers are connected between the TDI and TDO pins
andallowdatatobescannedintoandoutoftheSRAMtest
circuitry. Only one register can be selected at a time
throughtheinstructionregisters.Dataisseriallyloadedinto
theTDIpinontherisingedgeofTCKandoutputontheTDO
pin on the falling edge of TCK.
Scan Register Sizes
Instruction Register
Register Name
Instruction
Bypass
Bit Size (x18)
Bit Size (x36)
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
3
1
3
1
ID
32
51
32
70
Boundary Scan
When the TAP controller is in the CaptureIR state, the two
leastsignificantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
is set LOW (GND) when the BYPASS instruction is ex-
ecuted.
20
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IDENTIFICATION (ID) REGISTER
a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
betweentheTDIandTDOpinswhenthecontrollerismoved
into Shift-DR state. Bit 0 in the register is the LSB and the
first to reach TDO when shifting begins.
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
ID REGISTER CONTENTS
Die
Revision
Code
Vendor
Defomotopm
ISSI Technology
JEDECVendor
ID Code
PartConfiguration
Part # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
256K
512K
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
SAMPLE Z
clockinputiscapturedcorrectly,designsneedawaytostop
(or slow) the clock during a SAMPLE/PRELOAD instruc-
tion. If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented,sotheTAPcontrollerisnotfully1149.1compliant.
When the SAMPLE/PRELOAD instruction is loaded to the
instructionregisterandtheTAPcontrollerisintheCapture-
DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
Note that since the PRELOAD part of the command is not
implemented,puttingtheTAPintotheUpdatetotheUpdate-DR
state while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clockrunsmorethananorderofmagnitudefaster.Because
oftheclockfrequencydifferences, itispossiblethatduring
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
orrepeatableresults.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
TheadvantageoftheBYPASSinstructionisthatitshortens
the boundary scan path when multiple devices are con-
nected together on a board.
Reserved
Theseinstructionsarenotimplementedbutarereservedfor
future use. Do not use these instructions.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lizedlongenoughtomeettheTAPcontroller’scaptureset-
up plus hold times (tCS and tCH). To insure that the SRAM
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INSTRUCTION CODES
Code
Instruction
Description
001
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
010
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register be-
tween TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
22
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TAP ELECTRICAL CHARACTERISTICS Over the Operating Range(1,2)
Symbol
VOH1
VOH2
VOL1
VOL2
VIH
Parameter
Test Conditions
IOH = –2.0 mA
IOH = –100 mA
IOL = 2.0 mA
Min.
1.7
2.1
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
InputLoadCurrent
—
V
0.7
V
IOL = 100 mA
—
0.2
V
1.7
–0.3
–5
VDD +0.3
0.7
V
VIL
IOLT = 2mA
V
IX
GND ≤ V I ≤ VDDQ
5
mA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot:VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol
tTCYC
fTF
Parameter
Min.
100
—
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
TCK Clock cycle time
TCK Clock frequency
MHz
ns
tTH
TCK Clock HIGH
40
40
10
10
10
10
10
10
—
tTL
TCK Clock LOW
ns
tTMSS
tTDIS
tCS
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
ns
ns
ns
tTMSH
tTDIH
tCH
ns
ns
ns
tTDOV
tTDOX
ns
0
ns
Notes:
1. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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ISSI
TAP AC TEST CONDITIONS
TAP OUTPUT LOAD EQUIVALENT
Input pulse levels
0 to 2.5V
1ns
Input rise and fall times
Input timing reference levels
Output reference levels
Test load termination supply voltage
1.25V
1.25V
1.25V
50Ω
1.25V
TDO
20 pF
GND
Z0
= 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
t
TLTH
TCK
TMS
t
THTL
t
t
MVTH
DVTH
t
THMX
t
THDX
TDI
t
TLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
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ISSI
BOUNDARY SCAN ORDER (256K X 36)
Signal Bump
Signal Bump
Bit # Name
Signal Bump
Signal Bump
Bit # Name
ID
2R
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
ID
7G
6F
7E
7D
7H
6G
6E
6D
6A
5A
4G
4A
4B
4F
4M
4H
4K
6B
Bit # Name
ID
Bit # Name
ID
2K
1L
1
2
A
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
BWa
BWb
BWc
BWd
CE2
CE
5L
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
5G
3G
3L
3
A
2M
1N
1P
1K
2L
4
A
5
A
2B
4E
3A
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
5R
6
A
7
A
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
2N
2P
3R
2C
3C
5C
6C
4N
4P
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
A
ADV
ADSP
ADSC
OE
6K
7P
6N
6L
A
A
A
BWE
GW
CLK
A
A1
7K
7T
6H
A0
DQb
BOUNDARY SCAN ORDER (512K X 18)
Signal Bump
Signal Bump
Bit # Name
Signal Bump
Signal Bump
Bit # Name
ID
2R
2T
3T
5T
6R
3B
5B
7P
6N
6L
ID
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
4M
4H
Bit # Name
ID
4K
6B
5L
Bit # Name
ID
2K
1L
1
2
A
A
14
15
16
17
18
19
20
21
22
23
24
25
26
DQa
DQa
DQa
DQa
A
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
A
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
DQb
DQb
DQb
MODE
A
3
A
BWa
BWb
CE2
CE
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
4
A
3G
2B
4E
3A
2A
1D
2E
2G
1H
5R
5
A
6
A
A
7
A
A
A
8
DQa
DQa
DQa
DQa
ZZ
DQa
ADV
ADSP
ADSC
OE
A
A
9
DQb
DQb
DQb
DQb
NC
A
10
11
12
13
A
7K
7T
6H
A1
BWE
GW
A0
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ISSI
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
6.5 ns
IS61LF25632T-6.5TQ
IS61LF25632D-6.5TQ
TQFP
TQFP
6.5 ns
IS61LF25632T-6.5TQI
IS61LF25632D-6.5TQI
TQFP
TQFP
7.5 ns
IS61LF25632T-7.5TQ
IS61LF25632D-7.5TQ
IS61LF25632D-7.5B
TQFP
TQFP
PBGA
7.5 ns
IS61LF25632T-7.5TQI
IS61LF25632D-7.5TQI
TQFP
TQFP
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
6.5 ns
IS61LF25636T-6.5TQI
IS61LF25636D-6.5TQI
TQFP
TQFP
Speed
OrderPartNumber
Package
6.5 ns
IS61LF25636T-6.5TQ
IS61LF25636D-6.5TQ
IS61LF25636D-6.5B
TQFP
TQFP
PBGA
7.5 ns
IS61LF25636T-7.5TQI
IS61LF25636D-7.5TQI
TQFP
TQFP
IS61LF25636D-7.5BI
IS61LF25636J-7.5BI
TQFP
TQFP
IS61LF25636J-6.5B
PBGA
7.5 ns
IS61LF25636T-7.5TQ
IS61LF25636D-7.5TQ
IS61LF25636D-7.5B
TQFP
TQFP
PBGA
IS61LF25636J-7.5B
PBGA
Industrial Range: –40°C to +85°C
Speed
OrderPartNumber
Package
6.5 ns
IS61LF51218T-6.5TQI
IS61LF51218D-6.5TQI
TQFP
TQFP
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
7.5 ns
IS61LF51218T-7.5TQI
IS61LF51218D-7.5TQI
TQFP
TQFP
6.5 ns
IS61LF51218T-6.5TQ
IS61LF51218D-6.5TQ
IS61LF51218D-6.5B
TQFP
TQFP
PBGA
IS61LF51218D-7.5BI
IS61LF51218J-7.5BI
TQFP
TQFP
IS61LF51218J-6.5B
PBGA
7.5 ns
IS61LF51218T-7.5TQ
IS61LF51218D-7.5TQ
IS61LF51218D-7.5B
TQFP
TQFP
PBGA
IS61LF51218J-7.5B
PBGA
26
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相关型号：
IS61LF51236A-6.5B2LI
Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, LEAD FREE, PLASTIC, BGA-119
ISSI
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