IS61LPD51218T-225TQ [ISSI]
Cache SRAM, 512KX18, 2.8ns, CMOS, PQFP100, TQFP-100;
| 型号： | IS61LPD51218T-225TQ |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 512KX18, 2.8ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总29页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LPD25632T/D/J
IS61LPD25636T/D/J
IS61LPD51218T/D/J
®
ISSI
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINED,
APRIL 2003
DOUBLE-CYCLE DESELECT STATIC RAM
DESCRIPTION
FEATURES
The ISSI IS61LPD25632T/D/J,IS61LPD25636T/D/J,and
IS61LPD51218T/D/Jare high-speed, low-power synchro-
nous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LPD25632T/D/J is organized as
262,144 words by 32 bits and the IS61LPD25636T/D/J is
organizedas262,144wordsby36bits.TheIS61LPD51218T/
D/J is organized as 524,288 words by 18 bits. Fabricated
with ISSI's advanced CMOS technology, the device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drivecapabilityoutputsintoasinglemonolithiccircuit.
Allsynchronousinputspassthroughregisterscontrolledby
a positive-edge-triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE
input
•
Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
Writecyclesareinternallyself-timedandareinitiatedbythe
risingedgeoftheclockinput.Writecyclescanbeonetofour
bytes wide as controlled by the write control inputs.
• Power Supply
+3.3V VDD
Separate byte enables allow individual bytes to be written.
Bytewriteoperationisperformedbyusingbytewriteenable
(BWE). Input combined with one or more individual byte
write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
+3.3V or 2.5 VDDQ (I/O)
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• T Version (three chips selects)
• D Version (two chips selects)
• J Version (PBGA Package with JTAG)
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-250
2.6
4
-225
2.8
-200
3.1
5
-166
3.5
6
Units
ns
Clock Access Time
Cycle Time
tKC
4.4
ns
Frequency
250
225
200
166
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
1
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
BLOCK DIAGRAM
MODE
A0'
Q0
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
A1'
ADV
A1
256Kx32; 256Kx36;
512Kx18
ADSC
ADSP
CLR
MEMORY ARRAY
18/19
16/17
18/19
D
Q
A
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQd
BYTE WRITE
REGISTERS
BWd
(x32/x36)
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BWc
(x32/x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BWb
(x32/x36/x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
CE (T,D)
CE2 (T,D)
CE2 (T)
4
32, 36,
or 18
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa - DQd
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
PIN CONFIGURATION
119-pin PBGA (D Version)
(Top View)
1
2
3
4
5
6
7
A
B
C
D
E
F
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
NC
NC
CE2
A
A
A
NC
NC
A
VDD
A
A
DQc
DQc
NC
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
VDDQ
OE
VDDQ
G
H
J
DQc
DQc
ADV
GW
DQb
DQb
VDDQ
VDD
VDD
VDD
VDDQ
K
L
DQd
DQd
DQd
DQd
DQd
DQd
NC
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
NC
DQa
DQa
DQa
DQa
NC
DQa
DQa
M
N
P
R
T
VDDQ
BWE
A1
VDDQ
DQd
DQd
NC
DQa
DQa
NC
A0
A
VDD
A
NC
NC
A
A
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
3
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
PIN CONFIGURATION
100-Pin TQFP (D Version)
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
V
DDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
GND
DQb
DQb
DQb
DQb
GND
GND
DQb
DQb
DQb
DQb
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
DDQ
DQc
DQc
NC
VDDQ
V
DDQ
DQc
DQc
NC
DQb
DQb
GND
NC
DQb
DQb
GND
NC
V
DD
V
DD
V
DD
NC
GND
DQd
DQd
VDD
NC
GND
DQd
DQd
ZZ
DQa
DQa
ZZ
DQa
DQa
V
DDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
V
DDQ
DQd
DQd
NC
VDDQ
V
DDQ
DQd
DQd
NC
DQa
DQa
NC
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
PIN CONFIGURATION
119-pin PBGA (D Version)
(Top View)
119-pin PBGA (J Version)
(Top View)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
NC
NC
CE2
A
A
A
NC
NC
NC
NC
CE2
A
A
A
NC
NC
A
V
DD
A
A
A
VDD
A
A
DQc
DQc
DQPc
DQc
DQc
DQc
DQc
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQc
DQc
DQPc
DQc
DQc
DQc
DQc
GND
GND
GND
BWc
GND
NC
NC
CE
GND
GND
GND
BWb
GND
NC
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
V
DDQ
DQc
DQc
OE
V
DDQ
DQb
DQb
V
DDQ
DQc
DQc
OE
VDDQ
G
H
J
G
H
J
ADV
GW
ADV
GW
DQb
DQb
V
DDQ
DQd
DQd
V
DD
V
DD
V
DD
V
DDQ
DQa
DQa
V
DDQ
DQd
DQd
V
DD
VDD
V
DD
VDDQ
K
L
K
L
DQd
DQd
DQd
DQd
DQPd
A
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
NC
DQa
DQa
DQa
DQa
DQPa
A
DQd
DQd
DQd
DQd
DQPd
A
GND
BWd
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
NC
DQa
DQa
DQa
DQa
DQPa
A
DQa
DQa
M
N
P
R
T
M
N
P
R
T
V
DDQ
DQd
DQd
NC
BWE
A1
V
DDQ
DQa
DQa
NC
VDDQ
BWE
A1
VDDQ
DQd
DQd
NC
DQa
DQa
NC
A0
A0
V
DD
VDD
NC
NC
A
A
NC
ZZ
NC
NC
A
A
NC
ZZ
U
U
V
DDQ
TMS
TDI
TCK
TDO
NC
VDDQ
V
DDQ
NC
NC
NC
NC
NC
VDDQ
256K x 36
PIN DESCRIPTIONS
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
SynchronousGlobalWriteEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
A
Synchronous Address Inputs
SynchronousClock
CE, CE2, CE2 SynchronousChipEnable
CLK
ADSP
OE
OutputEnable
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
5
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
PIN CONFIGURATION
100-Pin TQFP (T Version)
100-Pin TQFP (D Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
DQPb
DQb
DQb
DQPc
DQc
DQc
DQPc
DQc
DQc
V
DDQ
VDDQ
V
DDQ
VDDQ
GND
DQb
DQb
DQb
DQb
GND
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
GND
DQc
DQc
DQc
DQc
GND
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
V
DDQ
VDDQ
DQb
DQb
GND
NC
DQc
DQc
NC
DQc
DQc
NC
V
DD
NC
VDD
V
DD
NC
ZZ
DQa
DQa
GND
DQd
DQd
GND
DQd
DQd
V
DDQ
VDDQ
V
DDQ
VDDQ
GND
DQa
DQa
DQa
DQa
GND
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
DQd
DQd
DQd
DQd
GND
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
V
DDQ
VDDQ
DQa
DQa
DQPa
DQd
DQd
DQPd
DQd
DQd
DQPd
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
PIN CONFIGURATION
119-pin PBGA (J Version)
(Top Version)
119-pin PBGA (D Version)
(Top Version)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
V
DDQ
A
A
A
A
A
V
DDQ
ADSP
ADSC
V
DDQ
A
A
A
ADSP
ADSC
A
A
V
DDQ
NC
NC
CE2
A
A
A
A
NC
NC
NC
NC
CE2
A
A
A
A
NC
NC
A
A
V
DD
A
VDD
A
DQb
NC
NC
DQb
NC
DQb
NC
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
NC
DQPa
NC
NC
NC
CE
DQb
NC
NC
DQb
NC
DQb
NC
GND
GND
GND
BWb
GND
NC
NC
CE
GND
GND
GND
GND
GND
NC
DQPa
NC
NC
DQa
DQa
V
DD
Q
DQa
NC
V
DDQ
DQa
NC
OE
V
DDQ
OE
DQa
NC
V
DDQ
DQa
NC
G
H
J
G
H
J
NC
ADV
GW
NC
ADV
GW
DQb
DQa
DQb
DQa
V
DDQ
V
DD
V
DD
V
DDQ
DQa
NC
V
DD
V
DDQ
V
DD
VDD
VDD
V
DDQ
DQa
NC
K
L
K
L
NC
DQb
NC
GND
GND
GND
GND
GND
MODE
A
GND
BWa
GND
GND
GND
NC
NC
DQa
NC
DQa
NC
A
CLK
NC
NC
DQb
NC
GND
GND
GND
GND
GND
MODE
A
CLK
NC
GND
BWa
GND
GND
GND
NC
NC
DQa
NC
DQa
NC
A
DQb
DQb
M
N
P
R
T
M
N
P
R
T
V
DDQ
DQb
NC
DQb
NC
V
DDQ
BWE
A1
V
DDQ
DQb
NC
DQb
NC
BWE
A1
V
DDQ
NC
NC
DQPb
A
DQa
NC
A0
DQPb
A
A0
DQa
NC
NC
V
DD
NC
VDD
NC
A
A
A
ZZ
NC
NC
NC
A
NC
A
A
ZZ
U
U
V
DDQ
NC
NC
NC
NC
VDDQ
V
DDQ
TMS
TDI
TCK
TDO
NC
VDDQ
512K x 18
PIN DESCRIPTIONS
TMS, TDI
TCK, TDO
JTAG BoundryScan Pins
SynchronousGlobalWriteEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
A
Synchronous Address Inputs
SynchronousClock
CE, CE2, CE2 SynchronousChipEnable
CLK
ADSP
OE
OutputEnable
SynchronousProcessorAddress
Status
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSC
SynchronousControllerAddress
Status
GND
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
BWa-BWd
BWE
Synchronous Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
DQPa-DQPd
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
7
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
PIN CONFIGURATION
100-Pin TQFP (D Version)
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
GND
NC
DQPa
DQa
DQa
GND
NC
NC
NC
DDQ
NC
NC
VDDQ
V
DDQ
V
GND
NC
DQPa
DQa
DQa
GND
GND
NC
NC
DQb
DQb
GND
GND
NC
NC
DQb
DQb
GND
VDDQ
V
DDQ
V
DDQ
V
DDQ
DQa
DQa
GND
NC
DQb
DQb
DQa
DQa
GND
NC
V
ZZ
DQa
DQa
V
GND
DQa
DQa
NC
NC
GND
V
NC
NC
NC
DQb
DQb
VDD
V
V
DD
V
DD
DD
VDD
NC
GND
DQb
DQb
DD
NC
GND
DQb
DQb
ZZ
DQa
DQa
VDDQ
VDDQ
DDQ
V
DDQ
GND
DQa
DQa
NC
NC
GND
GND
DQb
DQb
DQPb
NC
GND
DQb
DQb
DQPb
NC
GND
GND
VDDQ
V
DDQ
NC
NC
NC
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE
CE2
X
X
H
X
H
X
L
CE2
X
L
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc
and DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte
write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for
clarification.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
9
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
OPERATING RANGE
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
Industrial
-40°Cto+85°C
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
ExternalAddress
A1 A0
1stBurstAddress
A1 A0
2ndBurstAddress
A1 A0
3rdBurstAddress
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–55 to +150
1.6
Unit
°C
W
TSTG
PD
StorageTemperature
PowerDissipation
IOUT
OutputCurrent(perI/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
VIN
Voltage Relative to GND for
for Address and Control Inputs
V
VDD
Voltage on Vdd Supply Relatiive to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
DCELECTRICALCHARACTERISTICS(OverOperatingRange)
2.5V (I/O)
3.3V (I/O)
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
1.7
–0.3
–5
VDD + 0.3
2.0
–0.3
–5
VDD + 0.3
V
V
0.7
5
0.8
5
(1)
Input Leakage Current
Output Leakage Current
GND ≤VIN ≤VDD
µA
µA
ILO
GND ≤VOUT ≤VDDQ, OE = VI
–5
5
–5
5
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250
-225
Max
x18
Max
x36
Max
x18
Max
x36
Symbol Parameter
Test Conditions
Unit
ICC
AC Operating
Supply Current
Device Selected,
Com.
IND.
135 140
130
140
135
145
mA
mA
mA
OE = VIH, ZZ ≤VIL,
All Inputs ≤VIL or ≥ VIH,
Cycle Time ≥ tKC min.
ISB
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤VIL or ≥ VIH,
ZZ ≤VIL, f = Max.
COM.
Ind.
65
—
65
—
60
65
60
65
ISBI
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
30
—
30
—
30
40
30
40
VIN ≤GND + 0.2V or ≥ VDD – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits ±30 µA maximum leakage current when tied to
≤GND + 0.2V or ≥ Vdd – 0.2V.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200
-166
Max
x18
Max
x36
Max
x18
Max
x36
Symbol
Parameter
Test Conditions
Unit
ICC
AC Operating
Supply Current
Device Selected,
Com.
IND.
125 130
135 140
120
130
125
135
mA
mA
mA
OE = VIH, ZZ ≤VIL,
All Inputs ≤VIL or ≥ VIH,
Cycle Time ≥ tKC min.
ISB
ISBI
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤VIL or ≥ VIH,
ZZ ≤VIL, f = Max.
COM.
Ind.
55
60
55
60
50
55
50
55
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
30
40
30
40
30
40
30
40
VIN ≤GND + 0.2V or ≥ VDD – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or GND. It exhibits ±30 µA maximum leakage current when tied to
≤GND + 0.2V or ≥ VDD – 0.2V.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
13
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
ZO = 50Ω
+2.5V
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
1,538 Ω
1.25V
Figure 4
Figure 3
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
Read/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-200
Min.
-225
Min.
-250
Min.
Symbol Parameter
Min.
Max.
166
—
Max.
200
—
Max
225
—
Max
250
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
fMAX
tKC
tKH
tKL
Clock Frequency
—
—
5
—
4.4
1.8
1.8
—
—
4
Cycle Time
6
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
2.3
2.3
—
—
2
—
—
1.7
1.7
—
—
—
2
—
—
—
tKQ
3.5
—
—
3.1
—
2.8
—
2.6
—
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
1.5
0
1.0
0
1.0
0
0.8
0
(1,2)
(1,2)
tKQLZ
—
—
—
—
tKQHZ
tOEQ
—
3.5
3.5
—
—
3.0
3.1
—
—
2.8
2.8
—
—
2.6
2.6
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1,2)
tOELZ
tOEHZ
tAS
0
0
0
0
(1,2)
—
3.5
—
—
3.0
—
—
2.8
—
—
2.6
—
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
tSS
Address Status Setup Time
Write Setup Time
—
—
—
—
tWS
—
—
—
—
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
—
—
—
—
—
—
—
—
—
—
—
—
tSH
Address Status Hold Time
Write Hold Time
—
—
—
—
tWH
tCEH
tAVH
—
—
—
—
Chip Enable Hold Time
Address Advance Hold Time
—
—
—
—
—
—
—
—
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 1,2,3,4.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
15
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
BWx
WH
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-200
Min.
-225
Min.
-250
Min.
Symbol Parameter
Min.
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKC
Cycle Time
6
5
4.4
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
4
tKH
Clock High Pulse Width
Clock Low Pulse Width
Address Setup Time
Address Status Setup Time
Write Setup Time
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
tKL
2
tAS
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
tSS
tWS
tDS
Data In Setup Time
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
tSH
Address Status Hold Time
Data In Hold Time
tDH
tWH
tCEH
tAVH
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
17
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
ISB2
CurrentduringSNOOZEMODE
ZZ ≥ Vih, Com.
ZZ ≥ Vih, Ind.
—
—
30
40
mA
tPUS
tZZI
ZZ inactive to input sampled
2
—
0
—
2
cycle
cycle
ns
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
tRZZI
—
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
IEEE1149.1SERIALBOUNDARYSCAN(JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
The IS61LPD25636T/D/J and IS61LPD51218T/D/JT/D/
JT/D/JhaveaserialboundaryscanTestAccessPort(TAP)
inthePBGApackageonly.(NotavailableinTQFPpackage
or with the IS61LPD25632T/D/J.) This port operates in
accordancewithIEEEStandard1149.1-1900,butdoesnot
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
oftheSRAM.TheTAPcontrolleroperatesinamannerthat
does not conflict with the performance of other devices
using1149.1fullycompliantTAPs.TheTAPoperatesusing
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controllerandissampledontherisingedgeofTCK.Thispin
may be left disconnected if the TAP is not used. The pin is
internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registersandcanbeconnectedtotheinputofanyregister.
The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
ControllerStateDiagram.TDIisinternallypulledupandcan
bedisconnectediftheTAPisunusedinanapplication.TDI
is connected to the Most Significant Bit (MSB) on any
register.
DISABLING THE JTAG FEATURE
TheSRAMcanoperatewithoutusingtheJTAGfeature.To
disable the TAP controller, TCK must be tied LOW (GND)
to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to VDD through a pull-up resistor.
TDOshouldbeleftdisconnected.Onpower-up,thedevice
will start in a reset state which will not interfere with the
deviceoperation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
20
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Rev. A
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ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z in-
structions can be used to capture the contents of the Input
and Output ring.
TheBoundaryScanOrdertablesshowtheorderinwhichthe
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
Scan Register Sizes
RegisterName
Instruction
Bypass
BitSize(x18)
BitSize(x36)
3
1
3
1
TAP REGISTERS
RegistersareconnectedbetweentheTDIandTDOpinsand
allow data to be scanned into and out of the SRAM test
circuitry.Onlyoneregistercanbeselectedatatimethrough
theinstructionregisters.DataisseriallyloadedintotheTDI
pinontherisingedgeofTCKandoutputontheTDOpinon
the falling edge of TCK.
ID
32
51
32
70
BoundaryScan
TAP INSTRUCTION SET
Instruction Register
Eight instructions are possible with the three-bit instruction
registerandallcombinationsarelistedintheInstructionCode
table.ThreeinstructionsarelistedasRESERVEDandshould
not be used and the other five instructions are described
below. The TAP controller used in this SRAM is not fully
compliantwiththe1149.1conventionbecausesomeman-
datory instructions are not fully implemented. The TAP
controller cannot be used to load address, data or control
signals and cannot preload the Input or Output buffers. The
SRAMdoesnotimplementthe1149.1commandsEXTESTor
INTESTorthePRELOADportionofSAMPLE/PRELOAD;instead
itperformsacaptureoftheInputsandOutputringwhenthese
instructions are executed. Instructions are loaded into the
TAPcontrollerduringtheShift-IRstatewhentheinstruction
register is placed between TDI and TDO. During this state,
instructionsareshiftedfromtheinstructionregisterthrough
the TDI and TDO pins. To execute an instruction once it is
shifted in, the TAP controller must be moved into the
Update-IRstate.
Three-bitinstructionscanbeseriallyloadedintotheinstruc-
tion register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinaresetstate
as previously described.
When the TAP controller is in the CaptureIR state, the two
leastsignificantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
is set LOW (GND) when the BYPASS instruction is ex-
ecuted.
SAMPLE Z
Boundary Scan Register
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
all SRAM outputs into a High-Z state.
The boundary scan register is connected to all input and
output pins on theSRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
registerandthex18configurationhasa51-bit-longregister.
The boundary scan register is loaded with the contents of
the RAM Input and Output ring when the TAP controller is
intheCapture-DRstateandthenplacedbetweentheTDIand
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ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
betweentheTDIandTDOpinswhenthecontrollerismoved
into Shift-DR state. Bit 0 in the register is the LSB and the
first to reach TDO when shifting begins.The IDCODE
instructionisloadedintotheinstructionregisteruponpower-
uporwhenevertheTAPcontrollerisgivenatestlogicreset
state.
ID REGISTER CONTENTS
Die
Revision
Code
Vendor
Defomotopm
ISSI Technology
JEDECVendor
ID Code
PartConfiguration
Part # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
256K
512K
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented,sotheTAPcontrollerisnotfully1149.1compliant.
When the SAMPLE/PRELOAD instruction is loaded to the
instructionregisterandtheTAPcontrollerisintheCapture-
DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented,puttingtheTAPintotheUpdatetotheUpdate-DR
state while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clockrunsmorethananorderofmagnitudefaster.Because
oftheclockfrequencydifferences, itispossiblethatduring
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
orrepeatableresults.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
TheadvantageoftheBYPASSinstructionisthatitshortens
the boundary scan path when multiple devices are con-
nected together on a board.
RESERVED
Theseinstructionsarenotimplementedbutarereservedfor
future use. Do not use these instructions.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lizedlongenoughtomeettheTAPcontroller’scaptureset-
up plus hold times (tCS and tCH). To insure that the SRAM
clockinputiscapturedcorrectly,designsneedawaytostop
(or slow) the clock during a SAMPLE/PRELOAD instruc-
tion. If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
22
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Rev. A
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ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
INSTRUCTION CODES
Code
Instruction
Description
001
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
010
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
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04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
VOH1
VOH2
VOL1
Parameter
TestConditions
IOH = –2.0 mA
IOH = –100 mA
IOL = 2.0 mA
Min.
1.7
2.1
—
Max.
—
Units
V
OutputHIGHVoltage
OutputHIGHVoltage
OutputLOWVoltage
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLoadCurrent
—
V
0.7
V
VOL2
IOL = 100 mA
—
0.2
V
VIH
1.7
–0.3
–5
VDD +0.3
0.7
V
VIL
IX
IOLT = 2mA
V
GND ≤V I ≤VDDQ
5
mA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤VDD +1.5V for t ≤tTCYC/2,
Undershoot:VIL (AC) ≤0.5V for t ≤tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1) (OVER OPERATING RANGE)
Symbol Parameter
Min.
100
—
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
tTCYC
fTF
TCK Clock cycle time
TCK Clock frequency
MHz
ns
tTH
TCK Clock HIGH
40
40
10
10
10
10
10
10
—
tTL
TCK Clock LOW
ns
tTMSS
tTDIS
tCS
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMSholdafterTCKClockRise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
ns
ns
ns
tTMSH
tTDIH
tCH
ns
ns
ns
tTDOV
tTDOX
ns
0
ns
Notes:
1. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
TAP AC TEST CONDITIONS
Input pulse levels
0 to 2.5V
1ns
Input rise and fall times
Input timing reference levels
Output reference levels
1.25V
1.25V
1.25V
Test load termination supply voltage
TAP Output Load Equivalent
50Ω
1.25V
TDO
20 pF
GND
Z0 = 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
t
TLTH
TCK
TMS
t
THTL
t
t
MVTH
DVTH
tTHMX
t
THDX
TDI
t
TLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
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04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
BOUNDARY SCAN ORDER (256K X 36)
Signal Bump
Signal Bump
Bit # Name
Signal Bump
Signal Bump
Bit # Name
ID
2R
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
ID
7G
6F
7E
7D
7H
6G
6E
6D
6A
5A
4G
4A
4B
4F
4M
4H
4K
6B
Bit # Name
ID
Bit # Name
ID
2K
1L
1
2
A
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
BWa
BWb
BWc
BWd
CE2
CE
5L
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
5G
3G
3L
3
A
2M
1N
1P
1K
2L
4
A
5
A
2B
4E
3A
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
5R
6
A
7
A
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
2N
2P
3R
2C
3C
5C
6C
4N
4P
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
A
ADV
ADSP
ADSC
OE
6K
7P
6N
6L
A
A
A
BWE
GW
CLK
A
A1
7K
7T
6H
A0
DQb
BOUNDARY SCAN ORDER (512K X 18)
Signal Bump
Signal Bump
Bit # Name
Signal Bump
Signal Bump
Bit # Name
ID
2R
2T
3T
5T
6R
3B
5B
7P
6N
6L
ID
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
4M
4H
Bit # Name
ID
4K
6B
5L
Bit # Name
ID
2K
1L
1
2
A
A
14
15
16
17
18
19
20
21
22
23
24
25
26
DQa
DQa
DQa
DQa
A
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
A
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
DQb
DQb
DQb
MODE
A
3
A
BWa
BWb
CE2
CE
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
4
A
3G
2B
4E
3A
2A
1D
2E
2G
1H
5R
5
A
6
A
A
7
A
A
A
8
DQa
DQa
DQa
DQa
ZZ
DQa
ADV
ADSP
ADSC
OE
A
A
9
DQb
DQb
DQb
DQb
NC
A
10
11
12
13
A
7K
7T
6H
A1
BWE
GW
A0
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
ORDERING INFORMATION
ORDERING INFORMATION
(T Version)
Industrial Range: -40°C to +85°C
(T Version)
Commercial Range: 0°C to +70°C
Speed
166Mhz
200Mhz
OrderPartNumber
Package
TQFP
Speed
166Mhz
200Mhz
225Mhz
OrderPartNumber
Package
TQFP
IS61LPD25632T-166TQI
IS61LPD25632T-200TQI
IS61LPD25632T-166TQ
IS61LPD25632T-200TQ
IS61LPD25632T-225TQ
TQFP
TQFP
TQFP
225Mhz
IS61LPD25632T-225TQI
TQFP
250Mhz
IS61LPD25632T-250TQ
TQFP
(D Version)
(D Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166 MHz
166Mhz
IS61LPD25632D-166B
IS61LPD25632D-166TQ
BGA
TQFP
166 MHz
166Mhz
IS61LPD25632D-166BI
IS61LPD25632D-166TQI
BGA
TQFP
200 MHz
200Mhz
IS61LPD25632D-200B
IS61LPD25632D-200TQ
BGA
TQFP
200 MHz
200Mhz
IS61LPD25632D-200BI
IS61LPD25632D-200TQI
BGA
TQFP
225 MHz
225Mhz
IS61LPD25632D-225B
IS61LPD25632D-225TQ
BGA
TQFP
225 MHz
225Mhz
IS61LPD25632D-225BI
IS61LPD25632D-225TQI
BGA
TQFP
250 MHz
250Mhz
IS61LPD25632D-250B
IS61LPD25632D-250TQ
BGA
TQFP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
27
04/01/03
ISSI ®
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
ORDERING INFORMATION
ORDERING INFORMATION
(T Version)
(T Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
166Mhz
200Mhz
225Mhz
OrderPartNumber
Package
TQFP
Speed
166Mhz
200Mhz
OrderPartNumber
Package
TQFP
IS61LPD25636T-166TQ
IS61LPD25636T-200TQ
IS61LPD25636T-225TQ
IS61LPD25636T-166TQI
IS61LPD25636T-200TQI
TQFP
TQFP
TQFP
225Mhz
IS61LPD25636T-225TQI
TQFP
250Mhz
IS61LPD25636T-250TQ
TQFP
(D Version)
(D Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166 MHz
166Mhz
IS61LPD25636D-166B
IS61LPD25636D-166TQ
BGA
TQFP
166 MHz
166Mhz
IS61LPD25636D-166BI
IS61LPD25636D-166TQI
BGA
TQFP
200 MHz
200Mhz
IS61LPD25636D-200B
IS61LPD25636D-200TQ
BGA
TQFP
200 MHz
200Mhz
IS61LPD25636D-200BI
IS61LPD25636D-200TQI
BGA
TQFP
225 MHz
225Mhz
IS61LPD25636D-225B
IS61LPD25636D-225TQ
BGA
TQFP
225 MHz
225Mhz
IS61LPD25636D-225BI
IS61LPD25636D-225TQI
BGA
TQFP
250 MHz
250Mhz
IS61LPD25636D-250B
IS61LPD25636D-250TQ
BGA
TQFP
(J Version)
(J Version)
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed
166 MHz
200 MHz
OrderPartNumber
IS61LPD25636J-166BI
IS61LPD25636J-200BI
Package
BGA
Speed
OrderPartNumber
IS61LPD25636J-166B
IS61LPD25636J-200B
IS61LPD25636J-225B
Package
BGA
166 MHz
200 MHz
225 MHz
BGA
BGA
BGA
225 MHz
IS61LPD25636J-225BI
BGA
250 MHz
IS61LPD25636J-250B
BGA
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
04/01/03
ISSI ®
IS61LPD25632T/D/J,IS61LPD25636T/D/J,IS61LPD51218T/D/J
ORDERING INFORMATION
ORDERING INFORMATION
(T Version)
(T Version)
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed
166Mhz
200Mhz
225Mhz
OrderPartNumber
Package
TQFP
Speed
166Mhz
200Mhz
OrderPartNumber
Package
TQFP
IS61LPD51218T-166TQ
IS61LPD51218T-200TQ
IS61LPD51218T-225TQ
IS61LPD51218T-166TQI
IS61LPD51218T-200TQI
TQFP
TQFP
TQFP
225Mhz
IS61LPD51218T-225TQI
TQFP
250Mhz
IS61LPD51218T-250TQ
TQFP
(D Version)
(D Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166 MHz
166Mhz
IS61LPD51218D-166B
IS61LPD51218D-166TQ
BGA
TQFP
166 MHz
166Mhz
IS61LPD51218D-166BI
IS61LPD51218D-166TQI
BGA
TQFP
200 MHz
200Mhz
IS61LPD51218D-200B
IS61LPD51218D-200TQ
BGA
TQFP
200 MHz
200Mhz
IS61LPD51218D-200BI
IS61LPD51218D-200TQI
BGA
TQFP
225 MHz
225Mhz
IS61LPD51218D-225B
IS61LPD51218D-225TQ
BGA
TQFP
225 MHz
225Mhz
IS61LPD51218D-225BI
IS61LPD51218D-225TQI
BGA
TQFP
250 MHz
250Mhz
IS61LPD51218D-250B
IS61LPD51218D-250TQ
BGA
TQFP
(J Version)
(J Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
IS61LPD51218J-166B
IS61LPD51218J-200B
IS61LPD51218J-225B
Package
BGA
Speed
OrderPartNumber
IS61LPD51218J-166BI
IS61LPD51218J-200BI
IS61LPD51218J-225BI
Package
BGA
166 MHz
200 MHz
225 MHz
166 MHz
200 MHz
225 MHz
BGA
BGA
BGA
BGA
250 MHz
IS61LPD51218J-250B
BGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
29
04/01/03
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