IS61LPS102418A-200B3I [ISSI]
256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM; 256K X 72 ， 512K ×36 ， 1024K ×18 18MB同步流水式，单曲循环DESELECT静态RAM
| 型号： | IS61LPS102418A-200B3I |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 文件： | 总34页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61VPS25672A IS61LPS25672A
IS61VPS51236A IS61LPS51236A
IS61VPS102418A IS61LPS102418A
®
ISSI
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
FEBRUARY 2005
DESCRIPTION
FEATURES
The ISSIIS61LPS/VPS51236A,IS61LPS/VPS102418A,
andIS61LPS/VPS25672Aarehigh-speed,low-powersyn-
chronous staticRAMs designedtoprovideburstable, high-
performance memory for communication and networking
applications. The IS61LPS/VPS51236A is organized as
524,288 words by 36 bits, the IS61LPS/VPS102418A is
organizedas1,048,576wordsby18bits,andtheIS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with ISSI's advanced CMOS technology, the
deviceintegratesa2-bitburstcounter,high-speedSRAM
core,andhigh-drivecapabilityoutputsintoasinglemono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
Write cycles are internally self-timed and are initiated by
therisingedgeoftheclockinput. Writecyclescanbeone
tofourbyteswideascontrolledbythewritecontrolinputs.
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
Separatebyteenablesallowindividualbytestobewritten.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
PBGA, and 209-ball (x72) packages
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
inputpins.Subsequentburstaddressescanbegenerated
internally and controlled by the ADV (burst address
advance) input pin.
• Lead-free available
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
250
2.6
4
200
3.1
5
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
250
200
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
1
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
BLOCK DIAGRAM
MODE
A0'
Q0
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
A1'
ADV
A1
256Kx72;
512Kx36;
ADSC
ADSP
CLR
1024Kx18
MEMORY ARRAY
19/20
17/18
19/20
D
Q
A
ADDRESS
REGISTER
CE
CLK
36,
or 18
or 72
36,
or 18
or 72
D
Q
GW
BWE
DQ(a-h)
BYTE WRITE
REGISTERS
BW(a-h)
x18: a,b
x36: a-d
x72: a-h
CLK
36,
or 18
or 72
CE
CE2
CE2
2/4/8
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa - DQd
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
165-PIN BGA
119-PIN BGA
119-Ball, 14x22 mm BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 7x17 Ball Array
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
BOTTOM VIEW
209-BALL BGA
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
3
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
A
CE2
BWg
BWd
NC
ADSP
NC
ADSC
BWE
CE
ADV
A
CE2
BWb
BWe
NC
A
DQb
DQb
DQb
DQb
DQPf
DQf
DQb
DQb
DQb
DQb
DQPb
DQf
BWc
BWh
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CLK
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
BWf
BWa
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
NC
NC
NC
OE
VDD
NC
GW
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
G
H
J
NC
DQf
DQf
NC
DQf
DQf
NC
DQf
DQf
K
L
NC
NC
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
M
N
P
R
T
NC
NC
ZZ
VDD
MODE
A
U
V
W
A
A
A
A
A
A
A
A1
A
A
A
TMS
TDI
A
A0
A
TDO
TCK
11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
OutputEnable
Synchronous Burst Address
Advance
ZZ
PowerSleepMode
MODE
Burst Sequence Selection
JTAG Pins
ADSP
Address Status Processor
Address Status Controller
GlobalWriteEnable
TCK, TDO
TMS, TDI
ADSC
GW
NC
NoConnect
CLK
SynchronousClock
DQx
DQPx
VDD
DataInputs/Outputs
DataInputs/Outputs
3.3V/2.5V Power Supply
CE, CE2, CE2
Synchronous Chip Select
BWx (x=a,b,c,d Synchronous Byte Write
e,f,g,h) Controls
VDDQ
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
Vss
Vss
BWb
Vss
NC
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CE
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
Vss
BWd
Vss
Vss
Vss
MODE
A
Vss
BWa
Vss
Vss
Vss
NC
M
N
P
R
T
BWE
A1*
A0*
VDD
A
NC
NC
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
OE
Pin Name
Address Inputs
Output Enable
Power Sleep Mode
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Synchronous Burst Address
Advance
MODE
TCK, TDO
TMS, TDI
NC
Burst Sequence Selection
JTAG Pins
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
GlobalWriteEnable
No Connect
DQa-DQd
DQPa-Pd
VDD
Data Inputs/Outputs
Output Power Supply
Power Supply
CLK
CE
SynchronousClock
Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Controls
BWE Byte Write Enable
VDDQ
Output Power Supply
Vss
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
5
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
119 BGA PACKAGE PIN CONFIGURATION
1MX18 (TOP VIEW)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
VDDQ
NC
A
B
C
D
E
F
VDDQ
NC
A
A
A
A
NC
A
A
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CE
DQa
VDDQ
DQa
NC
VDDQ
NC
OE
G
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
Vss
Vss
Vss
Vss
Vss
MODE
A
DQb
VDDQ
DQb
NC
M
N
P
R
T
BWE
A1*
VDDQ
NC
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
OE
Pin Name
Symbol
A
Pin Name
Address Inputs
OutputEnable
PowerSleepMode
A0, A1
ADV
Synchronous Burst Address Inputs
ZZ
Synchronous Burst Address
Advance
MODE
TCK, TDO
TMS, TDI
NC
Burst Sequence Selection
JTAG Pins
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
GlobalWriteEnable
NoConnect
DQa-DQb
DQPa-Pb
VDD
DataInputs/Outputs
Output Power Supply
PowerSupply
CLK
CE
SynchronousClock
Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Controls
BWE Byte Write Enable
VDDQ
Output Power Supply
Vss
Ground
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
165 PBGA PACKAGE PIN CONFIGURATION
512K X 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
TDO
TCK
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
NC
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
DQPc
DQc
DQc
DQc
DQc
NC
NC
DQc
DQc
DQc
DQc
Vss
DQd
DQd
DQd
DQd
NC
NC
NC
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
A
K
L
M
N
P
R
TDI
TMS
A1*
A0*
MODE
A
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
Output Enable
Synchronous Burst Address
Advance
ZZ
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
MODE
ADSP
Address Status Processor
Address Status Controller
GlobalWriteEnable
TCK, TDO
TMS, TDI
ADSC
GW
NC
No Connect
CLK
SynchronousClock
DQx
DQPx
VDD
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
CE, CE2, CE2
Synchronous Chip Select
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
VDDQ
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
7
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
165 PBGA PACKAGE PIN CONFIGURATION
1M X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
CE
BWb
NC
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
TDO
TCK
ADSC
OE
Vss
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vss
A
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
A
NC
A
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
DQb
DQb
DQb
DQb
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
NC
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
A
K
L
M
N
P
R
A1*
A0*
MODE
A
A
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Symbol
Pin Name
Address Inputs
BWE
Byte Write Enable
A0, A1
ADV
Synchronous Burst Address Inputs
OE
Output Enable
Synchronous Burst Address
Advance
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
JTAG Pins
ADSP
ADSC
GW
Address Status Processor
Address Status Controller
GlobalWriteEnable
TCK, TDO
TMS, TDI
NC
No Connect
CLK
SynchronousClock
DQx
DQPx
VDD
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b)
Synchronous Byte Write
Controls
VDDQ
Isolated Output Power Supply
3.3V/2.5V
Vss
Ground
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
PIN CONFIGURATION
100-PIN TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQa-DQd
DQPa-DQPd
GW
Synchronous Data Input/Output
Parity Data Input/Output
SynchronousGlobalWriteEnable
Burst Sequence Mode Selection
OutputEnable
A
Synchronous Address Inputs
MODE
OE
ADSC
Synchronous Controller Address
Status
ADSP
Synchronous Processor Address
Status
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
BWa-BWd
BWE
Vss
ZZ
Ground
Snooze Enable
CE, CE2, CE2 SynchronousChipEnable
CLK SynchronousClock
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
9
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
PIN CONFIGURATION
100-PIN TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1024K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
DQPa-DQPb Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW
Synchronous Global Write Enable
Burst Sequence Mode Selection
OutputEnable
A
Synchronous Address Inputs
MODE
OE
ADSC
ADSP
ADV
SynchronousControllerAddressStatus
SynchronousProcessorAddressStatus
SynchronousBurstAddressAdvance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
VDD
3.3V/2.5V Power Supply
VDDQ
Isolated Output Buffer Supply:
3.3V/2.5V
BWa-BWb
BWE
Vss
ZZ
Ground
CE, CE2, CE2 Synchronous Chip Enable
Snooze Enable
CLK
Synchronous Clock
DQa-DQb
SynchronousDataInput/Output
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TRUTH TABLE(1-8) (3CE option)
OPERATION
ADDRESS
None
CE
H
L
CE2
X
X
H
X
H
X
L
CE2
X
L
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP ADSC ADV WRITE
OE
X
X
X
X
X
X
L
CLK
L-H
L-H
L-H
L-H
L-H
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
None
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
NOTE:
L
D
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
inputdataholdtime.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE
ADDRESS CE
ADSP ADSC
ADV
X
X
X
X
X
X
L
WRITE
X
OE
DQ
High-Z
Q
Deselected
None
External
External
External
External
External
Next
H
L
X
L
L
X
X
L
X
L
Read, Begin Burst
Read, Begin Burst
Write, Begin Burst
Read, Begin Burst
Read, Begin Burst
Read,ContinueBurst
Read,ContinueBurst
Read,ContinueBurst
Read,ContinueBurst
Write, Continue Burst
Write, Continue Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Write, Suspend Burst
X
L
L
X
H
X
L
High-Z
D
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
Write, Suspend Burst
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
inputdataholdtime.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
X
X
X
X
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
°C
W
TSTG
PD
Storage Temperature
Power Dissipation
–55 to +150
1.6
IOUT
Output Current (per I/O)
100
mA
V
VIN, VOUT Voltage Relative to Vss for I/O Pins
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
VIN
Voltage Relative to Vss for
V
for Address and Control Inputs
VDD
Voltage on VDD Supply Relative to Vss
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periodsmayaffectreliability.
2. Thisdevicecontainscircuitytoprotecttheinputsagainstdamageduetohighstaticvoltagesor
electricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigherthan
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
13
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
OPERATING RANGE (IS61LPSXXXXX)
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V + 5%
3.3V / 2.5V + 5%
Industrial
–40°Cto+85°C
3.3V + 5%
3.3V / 2.5V + 5%
OPERATING RANGE (IS61VPSXXXXX)
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
2.5V + 5%
2.5V + 5%
Industrial
–40°Cto+85°C
2.5V + 5%
2.5V + 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
2.5V
Max.
Symbol Parameter
Test Conditions
Min.
Max.
Min.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
2.0
-0.3
-5
VDD + 0.3
1.7 VDD + 0.3
V
V
0.8
5
-0.3
-5
0.7
5
(1)
Vss ≤ VIN ≤ VDD
µA
µA
ILO
Output Leakage Current Vss ≤ VOUT ≤ VDDQ,
OE = VIH
-5
5
-5
5
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250
MAX
x36
-200
MAX
x36
Symbol Parameter
Test Conditions
Temp.range x18
x72
x18
x72
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
450
500
450
500
600
650
425
475
425
475
550
600
mA
mA
mA
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
150
150
150
150
150
150
150
150
150
150
150
150
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
110
125
110
125
110
125
110
125
110
125
110
125
VIN
≤ VSS + 0.2V or ≥VDD – 0.2V
f = 0
ZZ>VIH
ISB2
Sleep Mode
Com.
Ind.
60
75
60
75
60
75
60
75
60
75
60
75
mA
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
Z
O
= 50Ω
OUTPUT
Output
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
15
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
317 Ω
2.5V
Z
O
= 50Ω
OUTPUT
Output
50Ω
351 Ω
5 pF
Including
jig and
1.25V
scope
Figure 3
Figure 4
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-250
-200
Min.
Symbol
fMAX
tKC
Parameter
Min.
Max.
250
Max.
200
—
Unit
MHz
ns
ClockFrequency
—
—
5
Cycle Time
4.0
1.7
1.7
—
—
—
—
2.6
—
—
2.6
2.8
—
2.6
—
—
—
—
—
—
—
—
—
—
2
tKH
Clock High Time
2
—
ns
tKL
Clock Low Time
2
—
ns
tKQ
Clock Access Time
—
3.1
—
ns
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Data Setup Time
0.8
0.8
—
1.5
1
ns
(2,3)
tKQLZ
tKQHZ
tOEQ
—
ns
(2,3)
—
3.0
3.1
—
ns
—
—
ns
(2,3)
tOELZ
0
0
ns
(2,3)
tOEHZ
tAS
—
—
3.0
—
ns
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
—
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
—
ns
tWS
—
ns
tCES
tAVS
tDS
—
ns
—
ns
—
ns
tAH
Address Hold Time
—
ns
tWH
Write Hold Time
—
ns
tCEH
tAVH
tDH
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
—
ns
—
ns
—
ns
tPDS
tPUS
Note:
ZZ High to Power Down
ZZ Low to Power Down
2
cyc
cyc
—
2
—
2
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
17
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
BWx
WH
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Unselected
Single Write
Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
19
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
—
—
2
Max.
60
2
Unit
mA
CurrentduringSNOOZEMODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
ZZ ≥ Vih
tPDS
cycle
cycle
cycle
ns
tPUS
—
2
tZZI
—
0
tRZZI
—
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
IEEE1149.1SERIALBOUNDARYSCAN(JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
TheIS61LPS/VPSxxxxxxproductshaveaserialboundary
scan Test Access Port (TAP) in the PBGA package only.
(The TQFP package not available.) This port operates in
accordancewithIEEEStandard1149.1-1900,butdoesnot
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
oftheSRAM.TheTAPcontrolleroperatesinamannerthat
does not conflict with the performance of other devices
using1149.1fullycompliantTAPs.TheTAPoperatesusing
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
DISABLING THE JTAG FEATURE
TheSRAMcanoperatewithoutusingtheJTAGfeature.To
disabletheTAP controller, TCK must betiedLOW (Vss)to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
beconnectedtoVDD throughapull-upresistor.TDOshould
beleftdisconnected. Onpower-up, thedevicewillstartina
resetstatewhichwillnotinterferewiththedeviceoperation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
21
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
is set LOW (VSS) when the BYPASS instruction is ex-
ecuted.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect(NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
RegistersareconnectedbetweentheTDIandTDOpinsand
allow data to be scanned into and out of the SRAM test
circuitry.Onlyoneregistercanbeselectedatatimethrough
theinstructionregisters.DataisseriallyloadedintotheTDI
pinontherisingedgeofTCKandoutputontheTDOpinon
the falling edge of TCK.
TheBoundaryScanOrdertablesshowtheorderinwhichthe
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Instruction Register
Three-bitinstructionscanbeseriallyloadedintotheinstruc-
tion register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinaresetstate
as previously described.
Register
Name
BitSize
(x18)
BitSize
(x36)
BitSize
(x72)
Instruction
Bypass
3
1
3
1
3
1
ID
32
75
32
75
32
BoundaryScan
TBD
When the TAP controller is in the CaptureIR state, the two
leastsignificantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Identification (ID) Register
Bypass Register
TheIDregisterisloadedwithavendor-specific,32-bitcode
duringtheCapture-DRstatewhentheIDCODEcommandis
loadedtotheinstructionregister.TheIDCODEishardwired
into the SRAM and can be shifted out when the TAP
controllerisintheShift-DRstate.TheIDregisterhasvendor
code and other information described in the Identification
Register Definitions table.
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
IDENTIFICATION REGISTER DEFINITIONS
InstructionField
Description
256Kx72
xxxx
512Kx36
xxxx
1Mx18
xxxx
RevisionNumber (31:28)
DeviceDepth (27:23)
DeviceWidth (22:18)
ISSIDeviceID (17:12)
ISSIJEDECID (11:1)
IDRegisterPresence (0)
Reservedforversionnumber.
DefinesdepthofSRAM.512K,1Mor256K
DefineswidthoftheSRAM.x72,x36orx18
Reservedforfutureuse.
00110
00101
xxxx
00111
01000
00100
00011
xxxxx
xxxxx
AllowsuniqueidentificationofSRAMvendor.
IndicatethepresenceofanIDregister.
0011010101
1
00011010101
1
00011010101
1
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
registerandallcombinationsarelistedintheInstructionCode
table.ThreeinstructionsarelistedasRESERVEDandshould
not be used and the other five instructions are described
below. The TAP controller used in this SRAM is not fully
compliantwiththe1149.1conventionbecausesomeman-
datory instructions are not fully implemented. The TAP
controller cannot be used to load address, data or control
signals and cannot preload the Input or Output buffers. The
SRAMdoesnotimplementthe1149.1commandsEXTESTor
INTESTorthePRELOADportionofSAMPLE/PRELOAD;instead
itperformsacaptureoftheInputsandOutputringwhenthese
instructions are executed. Instructions are loaded into the
TAPcontrollerduringtheShift-IRstatewhentheinstruction
register is placed between TDI and TDO. During this state,
instructionsareshiftedfromtheinstructionregisterthrough
the TDI and TDO pins. To execute an instruction once it is
shifted in, the TAP controller must be moved into the
Update-IRstate.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented,sotheTAPcontrollerisnotfully1149.1compliant.
When the SAMPLE/PRELOAD instruction is loaded to the
instructionregisterandtheTAPcontrollerisintheCapture-
DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clockrunsmorethananorderofmagnitudefaster.Because
oftheclockfrequencydifferences, itispossiblethatduring
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
orrepeatableresults.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lizedlongenoughtomeettheTAPcontroller’scaptureset-
up plus hold times (tCS and tCH). To insure that the SRAM
clockinputiscapturedcorrectly,designsneedawaytostop
(or slow) the clock during a SAMPLE/PRELOAD instruc-
tion. If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK captured in
the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executedwhenevertheinstructionregisterisloadedwithall
0s. Because EXTEST is not implemented in the TAP
controller,thisdeviceisnot1149.1standardcompliant.The
TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
hasbeenloaded. Thereisadifferencebetween the instruc-
tions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented,puttingtheTAPintotheUpdatetotheUpdate-DR
state while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
codetobeloadedintotheinstructionregister.Italsoplaces
the instruction register between the TDI and TDO pins and
allowstheIDCODEtobeshiftedoutofthedevicewhenthe
TAP controller enters the Shift-DR state. The IDCODE
instructionisloadedintotheinstructionregisteruponpower-
uporwhenevertheTAPcontrollerisgivenatestlogicreset
state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
TheadvantageoftheBYPASSinstructionisthatitshortens
the boundary scan path when multiple devices are con-
nected together on a board.
SAMPLE-Z
RESERVED
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
all SRAM outputs into a High-Z state.
Theseinstructionsarenotimplementedbutarereservedfor
future use. Do not use these instructions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
23
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
INSTRUCTION CODES
Code
Instruction
Description
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register between
the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
VOH1
VOH2
VOL1
VOL2
VIH
Parameter
TestConditions
Min.
1.7
2.1
—
Max.
—
Units
OutputHIGHVoltage
OutputHIGHVoltage
OutputLOWVoltage
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakageCurrent
IOH = –2.0 mA
V
V
V
V
V
V
IOH = –100
IOL = 2.0 mA
IOL = 100
µA
—
0.7
µA
—
0.2
1.7
–0.3
–10
VDD +0.3
0.7
VIL
IX
VSS ≤ V I ≤ VDDQ
10
µA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
100
—
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
tTCYC
fTF
TCK Clock cycle time
TCK Clock frequency
MHz
ns
tTH
TCK Clock HIGH
40
40
10
10
10
10
10
10
—
tTL
TCK Clock LOW
ns
tTMSS
tTDIS
tCS
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMSholdafterTCKClockRise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
ns
ns
ns
tTMSH
tTDIH
tCH
ns
ns
ns
tTDOV
ns
tTDOX
0
ns
Notes:
1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
25
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Input pulse levels
0 to 2.5V/0 to 3.0V
1ns
Input rise and fall times
Input timing reference levels
Output reference levels
1.25V/1.5V
1.25V/1.5V
50Ω
Vtrig
Test load termination supply voltage
Vtrig
1.25V/1.5V
1.25V/1.5V
TDO
20 pF
GND
Z0 = 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
t
TLTH
TCK
TMS
t
THTL
t
t
MVTH THMX
t
DVTH
t
THDX
TDI
t
TLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
209 BOUNDARY SCAN ORDER (256K X 72)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
27
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
ID
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10A
10B
9A
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
ID
1
2
MODE
A
1R
NC
CE2
BWa
BWb
BWc
BWd
CE2
CE
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
6N
1K
1L
3
A
11P
8P
4
A
1M
2J
5
A
8R
6
A
9R
2K
2L
7
A
9P
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
2M
1N
3P
3R
4R
4P
6P
6R
9
A
A
10
11
12
13
14
15
16
17
18
19
20
A
A
ZZ
A
NC
A
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
A
ADV
ADSP
ADSC
OE
A
9B
A1
8A
A0
8B
BWE
GW
7A
7B
CLK
NC
6B
11B
28
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump
Signal Bump
Signal
Name
Bump
ID
Signal Bump
Bit # Name
ID
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
DQa
DQa
DQa
DQa
DQa
NC
ID
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
A
ID
1
2
MODE
A
1R
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
NC
CE2
BWa
NC
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
6N
1K
1L
3
A
11P
8P
4
A
1M
1N
2K
2L
5
A
8R
BWb
NC
6
A
9R
7
A
9P
NC
CE2
CE
8
A
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
NC
2M
2J
9
A
NC
A
10
11
12
13
14
15
16
17
18
19
20
A
A
A
3P
3R
4R
4P
6P
6R
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
A
NC
A
A
NC
A
ADV
ADSP
ADSC
OE
NC
A
9B
NC
A1
8A
NC
A0
8B
NC
BWE
GW
CLK
NC
7A
DQb
DQb
DQb
DQb
7B
6B
11B
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
29
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
512Kx36
Frequency
OrderPartNumber
Package
250
IS61LPS51236A-250TQ
IS61LPS51236A-250B2
100 TQFP
119 PBGA
IS61LPS51236A-250B3
165 PBGA
200
250
IS61LPS51236A-200TQ
IS61LPS51236A-200B2
IS61LPS51236A-200B3
100 TQFP
119 PBGA
165 PBGA
1Mx18
IS61LPS102418A-250TQ
IS61LPS102418A-250B2
100 TQFP
119 PBGA
IS61LPS102418A-250B3
165 PBGA
200
250
IS61LPS102418A-200TQ
IS61LPS102418A-200B2
IS61LPS102418A-200B3
100 TQFP
119 PBGA
165 PBGA
256Kx72
IS61LPS25672A-250B1
209 PBGA
Industrial Range: -40°C to +85°C
Configuration
512Kx36
Frequency
OrderPartNumber
Package
250
IS61LPS51236A-250TQI
IS61LPS51236A-250B2I
100 TQFP
119 PBGA
IS61LPS51236A-250B3I
165 PBGA
200
IS61LPS51236A-200TQI
IS61LPS51236A-200TQLI
IS61LPS51236A-200B2I
100 TQFP
100TQFP,Lead-free
119 PBGA
IS61LPS51236A-200B3I
IS61LPS51236A-200B3LI
165 PBGA
165PBGA,Lead-free
1Mx18
250
200
250
IS61LPS102418A-250TQI
IS61LPS102418A-250B2I
100 TQFP
119 PBGA
IS61LPS102418A-250B3I
165 PBGA
IS61LPS102418A-200TQI
IS61LPS102418A-200B2I
100 TQFP
119 PBGA
IS61LPS102418A-200B3I
IS61LPS25672A-250B1I
165 PBGA
209 PBGA
256Kx72
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
®
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
ISSI
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
512Kx36
Frequency
OrderPartNumber
Package
250
IS61VPS51236A-250TQ
IS61VPS51236A-250B2
100 TQFP
119 PBGA
IS61VPS51236A-250B3
165 PBGA
200
IS61VPS51236A-200TQ
IS61VPS51236A-200B2
100 TQFP
119 PBGA
IS61VPS51236A-200B3
165 PBGA
1Mx18
250
200
250
IS61VPS102418A-250TQ
IS61VPS102418A-250B2
100 TQFP
119 PBGA
IS61VPS102418A-250B3
165 PBGA
IS61VPS102418A-200TQ
IS61VPS102418A-200B2
100 TQFP
119 PBGA
IS61VPS102418A-200B3
IS61VPS25672A-250B1
165 PBGA
209 PBGA
256Kx72
Industrial Range: -40°C to +85°C
Configuration
512Kx36
Frequency
OrderPartNumber
Package
250
IS61VPS51236A-250TQI
IS61VPS51236A-250B2I
100 TQFP
119 PBGA
IS61VPS51236A-250B3I
165 PBGA
200
IS61VPS51236A-200TQI
IS61VPS51236A-200B2I
100 TQFP
119 PBGA
IS61VPS51236A-200B3I
165 PBGA
1Mx18
250
200
250
IS61VPS102418A-250TQI
IS61VPS102418A-250B2I
100 TQFP
119 PBGA
IS61VPS102418A-250B3I
165 PBGA
IS61VPS102418A-200TQI
IS61VPS102418A-200B2I
100 TQFP
119 PBGA
IS61VPS102418A-200B3I
IS61VPS25672A-250B1I
165 PBGA
209 PBGA
256Kx72
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
31
02/11/05
®
PACKAGING INFORMATION
ISSI
Plastic Ball Grid Array
Package Code: B (119-pin)
φ
b (119X)
E
A
7
6
5
4
3
2
1
A
B
C
D
E
F
30ϒ
G
H
J
D
D2
D1
K
L
M
N
P
R
T
e
U
A2
E1
A1
A3
E2
SEATING PLANE
A4
MILLIMETERS
INCHES
Min.
Sym. Min.
Max.
Max.
N0.
Leads
Notes:
119
1.Controllingdimension:millimeters,unlessotherwisespecified.
2.BSC=Basicleadspacingbetweencenters.
3.DimensionsD1andEdonotincludemoldflashprotrusionand
shouldbemeasuredfromthebottomofthepackage.
4.Formedleadsshallbeplanarwithrespecttooneanotherwithin
0.004inchesattheseatingplane.
A
—
2.41
0.70
1.00
1.70
—
0.095
0.028
0.039
0.067
A1
A2
A3
A4
b
0.50
0.80
1.30
0.020
0.032
0.051
0.56 BSC
0.022 BSC
0.60
0.90
0.024
0.858
0.035
0.874
D
21.80
22.20
D1
D2
E
20.32 BSC
0.800 BSC
19.40
13.80
19.60
14.20
0.764
0.543
0.772
0.559
E1
E2
e
7.62 BSC
0.300 BSC
11.90
12.10
0.469
0.476
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
02/12/03
®
PACKAGING INFORMATION
Ball Grid Array
ISSI
Package Code: B (165-pin)
BOTTOM VIEW
A1 CORNER
TOP VIEW
A1 CORNER
φ b (165X)
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS
INCHES
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
Min. Nom. Max.
165
N0.
Leads
165
A
—
0.25
—
—
1.20
0.40
—
—
—
0.047
0.010 0.013 0.016
0.031
A1
A2
D
0.33
0.79
—
—
14.90 15.00 15.10
13.90 14.00 14.10
12.90 13.00 13.10
9.90 10.00 10.10
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
D1
E
E1
e
—
1.00
0.45
—
—
0.039
—
b
0.40
0.50
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
®
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
Inches Millimeters
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
Millimeters
Min Max
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
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