IS61LPS25636A-200TQ2LI-TR [ISSI]
IC SRAM 9M PARALLEL 100TQFP;
| 型号： | IS61LPS25636A-200TQ2LI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 9M PARALLEL 100TQFP 静态存储器 |
| 文件： | 总35页 (文件大小：2595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
256K x 36, 256K x 32, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
JUNE 2015
FEATURES
DESCRIPTION
Theꢀ ISSIꢀ IS61LPS/VPS25636A,ꢀ IS61LPS25632A,
IS64LPS25636Aꢀ andꢀ IS61LPS/VPS51218Aꢀ areꢀ high-
speed,ꢀ low-powerꢀ synchronousꢀ staticꢀ RAMs designed
to provide burstable, high-performance memory for com-
municationꢀandꢀnetworkingꢀapplications.ꢀTheꢀIS61LPS/
VPS25636Aꢀ andꢀ IS64LPS25636Aꢀ areꢀ organizedꢀ asꢀ
262,144ꢀ wordsꢀ byꢀ 36ꢀ bits.ꢀ ꢀ Theꢀ IS61LPS25632Aꢀ is
organizedꢀasꢀ262,144ꢀwordsꢀbyꢀ32ꢀbits.ꢀTheꢀIS61LPS/
VPS51218Aꢀisꢀorganizedꢀasꢀ524,288ꢀwordsꢀbyꢀ18ꢀbits.ꢀ
Fabricatedꢀ withꢀ ISSI'sꢀ advancedꢀ CMOSꢀ technology,
theꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀhigh-speedꢀ
SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ
monolithic circuit. All synchronous inputs pass through
registersꢀcontrolledꢀbyꢀaꢀpositive-edge-triggeredꢀsingleꢀ
clock input.
• Internalꢀself-timedꢀwriteꢀcycle
• IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite
• Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀand
control
• BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinput
• Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-
pansion and address pipelining
• Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
• AutoꢀPower-downꢀduringꢀdeselect
• Singleꢀcycleꢀdeselect
• SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby
• JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage
• PowerꢀSupply
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ
one to four bytes wide as controlled by the write control
inputs.
LPS:ꢀVdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPS:ꢀVdd 2.5V + 5%, Vddq 2.5V + 5%
Separatebyteenablesallowindividualbytestobewritten.
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ
write enable (BWE) input combined with one or more
individual byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀ
Writeꢀ(GW) is available for writing all bytes at one time,
regardless of the byte write controls.
• JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-
ballꢀBGAꢀpackages
• Lead-freeꢀavailable
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status
Processor)ꢀorꢀADSC (Address Status Cache Controller)
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-
ated internally and controlled by the ADV (burst address
advance) input pin.
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ
or left floating.
FAST ACCESS TIME
Symbol
Parameter
250
2.6ꢀ
4ꢀ
200
3.1ꢀ
5ꢀ
166
3.5ꢀ
6ꢀ
Units
ns
tkq
ClockꢀAccessꢀTimeꢀ
CycleꢀTimeꢀ
tkc
ns
Frequencyꢀ
250ꢀ
200ꢀ
166ꢀ
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
BLOCK DIAGRAM
MODE
A0'
Q0
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
A1'
ADV
A1
256Kx32;
256Kx36;
512Kx18
ADSC
ADSP
CLR
MEMORY ARRAY
18/19
16/17
18/19
D
Q
A
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQ(a-d)
BYTE WRITE
REGISTERS
BW(a-d)
x18: a,b
x32/x36: a-d
CLK
32, 36,
or 18
CE
CE2
CE2
2/4/8
INPUT
OUTPUT
D
Q
DQa - DQd
REGISTERS
REGISTERS
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
POWER
DOWN
REGISTER
ZZ
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165-PIN BgA
119-PIN BgA
119-Ball,ꢀ14x22ꢀmmꢀBGAꢀ
165-Ball,ꢀ13x15ꢀmmꢀBGA
BOTTOMꢀVIEW
BOTTOMꢀVIEW
Integrated Silicon Solution, Inc.
3
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION-256k x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A
A
A
ADSP
ADSC
VDD
NC
A
A
A
A
VDDQ
NC
CE2
A
NC
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
Vss
Vss
Vss
BWc
Vss
NC
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQbꢀ
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CE
OE
g
H
J
ADV
GW
VDD
CLK
NC
K
L
DQd
DQd
DQd
DQd
DQPd
A
Vss
BWd
Vss
Vss
Vss
MODE
A
M
N
P
R
T
BWE
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
OE
Pin Name
Symbol
A
Pin Name
Address Inputs
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
MODE
TCK,ꢀTDO
ꢀꢀTMS,ꢀTDI
NC
ADSP
ADSC
GWꢀ
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnable
No Connect
DQa-DQd
DQPa-Pdꢀ
Vdd
DataꢀInputs/Outputs
OutputꢀPowerꢀSupply
PowerꢀSupply
CLK
Synchronous Clock
CE,ꢀCE2
Synchronous Chip Select
BWxꢀ(x=a-d)ꢀ SynchronousꢀByteꢀWriteꢀControls
BWE ByteꢀWriteꢀEnable
Vddq
OutputꢀPowerꢀSupply
Ground
Vss
4
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION
512kx18 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A
CE2
A
A
A
ADSP
ADSC
VDD
NC
A
A
A
A
VDDQ
NC
NC
A
A
A
NC
DQb
NC
NC
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
DQb
NC
CE
DQa
VDDQ
DQa
NC
VDDQ
NC
OE
g
H
J
DQb
NC
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDD
DQb
NC
VDDQ
DQa
NC
K
L
Vss
Vss
Vss
Vss
Vss
MODE
A
DQb
VDDQ
DQb
NC
M
N
P
R
T
DQb
NC
BWE
A1*
VDDQ
NC
DQPb
A
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
OE
Pin Name
Symbol
A
Pin Name
Address Inputs
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
MODE
TCK,ꢀTDO
TMS,ꢀTDI
NC
ADSP
ADSC
GWꢀ
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnable
No Connect
DQa-DQb
DQPa-Pbꢀ
Vdd
DataꢀInputs/Outputs
OutputꢀPowerꢀSupply
PowerꢀSupply
CLK
Synchronous Clock
CE,ꢀCE2
Synchronous Chip Select
BWxꢀ(x=a,b)ꢀ SynchronousꢀByteꢀWriteꢀControls
BWE ByteꢀWriteꢀEnable
Vddq
OutputꢀPowerꢀSupply
Ground
Vss
5
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA PACKAGE PIN CONFIGURATION
256k x 36 (TOP VIEW)
1
2
3
4
5
6
7
8
ADSC
OE
9
10
A
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADV
ADSP
Vddq
Vddq
Vddq
Vddq
Vddq
Nc
NC
A
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
A
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQPc
DQc
DQc
DQc
DQc
NC
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
Nc
DQb
DQb
DQb
DQb
Nc
dqa
dqa
dqa
dqa
NC
A
DQc
DQc
DQc
DQc
Vss
DQd
DQd
DQd
DQd
NC
g
H
J
DQd
DQd
DQd
DQd
DQPd
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
Vddq
Vddq
Vddq
Vddq
Vddq
A
dqa
dqa
dqa
dqa
DQPa
A
K
L
M
N
P
R
NC
TDI
TMS
A1*
A0*
TDO
TCK
MODE
NC
A
A
A
A
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
BWE
OE
Pin Name
ByteꢀWriteꢀEnable
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
Advance
MODE
ADSP
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnable
TCK,ꢀTDO
TMS,ꢀTDI
ADSC
GW
NC
No Connect
CLK
Synchronous Clock
DQx
DQPxꢀ
Vdd
DataꢀInputs/Outputs
DataꢀInputs/Outputs
3.3V/2.5VꢀPowerꢀSupply
CE, CE2, CE2
Synchronous Chip Select
BWxꢀ(x=a,b,c,d)ꢀ SynchronousꢀByteꢀWriteꢀ
Controls
Vddq
IsolatedꢀOutputꢀPowerꢀSupplyꢀꢀꢀꢀ
3.3V/2.5V
Vssꢀ
Ground
6ꢀ
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA PACKAGE PIN CONFIGURATION
512k x 18 (TOP VIEW)
1
NC
2
3
4
5
6
7
8
ADSC
OE
9
10
A
11
A
A
B
C
D
E
F
A
CE
BWb
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADV
ADSP
Vddq
Vddq
Vddq
Vddq
Vddq
Nc
NC
A
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
DQb
DQb
DQb
DQb
Vss
NC
NC
NC
NC
NC
NC
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
Nc
NC
NC
NC
NC
Nc
dqa
dqa
dqa
dqa
NC
A
NC
NC
NC
g
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
Vddq
Vddq
Vddq
Vddq
Vddq
A
Nc
Nc
Nc
Nc
NC
A
K
L
M
N
P
R
TDI
TMS
A1*
A0*
TDO
TCK
MODE
A
A
A
A
A
A
Note: * A0 and A1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
BWE
OE
Pin Name
ByteꢀWriteꢀEnable
OutputꢀEnable
A0, A1
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ADVꢀ
SynchronousꢀBurstꢀAddressꢀ
ZZꢀ
PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
Advance
MODE
ADSP
ADSC
GW
AddressꢀStatusꢀProcessor
Address Status Controller
GlobalꢀWriteꢀEnableꢀ
TCK,ꢀTDO
TMS,ꢀTDI
NC
No Connect
CLK
Synchronous Clock
DQx
DQPxꢀ
Vdd
DataꢀInputs/Outputs
DataꢀInputs/Outputs
3.3V/2.5VꢀPowerꢀSupply
CE, CE2, CE2 Synchronous Chip Select
BWxꢀ(x=a,b)ꢀ
SynchronousꢀByteꢀWriteꢀ
Controls
Vddq
IsolatedꢀOutputꢀPowerꢀSupplyꢀꢀꢀꢀ
3.3V/2.5V
Vssꢀ
Ground
7
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
100-PIN QFP (256K ꢀ 36)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
DQPc
DQc
DQc
VDDQ
V
DDQ
VSS
DQb
DQb
DQb
DQb
VSS
VSS
DQc
DQc
DQc
DQc
VSS
V
DDQ
V
DDQ
DQb
DQb
VSS
NC
DQc
DQc
NC
VDD
NC
V
DD
NC
VDD
ZZ
V
DD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
ZZ
DQa
DQa
VSS
DQd
DQd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
VDDQ
V
V
DDQ
VSS
DQa
DQa
DQa
DQa
VSS
VSS
DQd
DQd
DQd
DQd
VSS
V
DDQ
DDQ
DQa
DQa
DQPa
DQd
DQd
DQPd
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(2 Chip-Enable option)
(3 Chip-Enable option)
PIN DESCRIPTIONS
DQa-DQdꢀ
SynchronousꢀDataꢀInput/Output
A0, A1
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
DQPa-DQPdꢀ ParityꢀDataꢀInput/Output
GWꢀ
SynchronousꢀGlobalꢀWriteꢀEnable
A
Synchronous Address Inputs
MODEꢀ
OEꢀ
BurstꢀSequenceꢀModeꢀSelection
OutputꢀEnable
ADSC
ADSP
ADV
Synchronous Controller Address Status
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
Vddꢀ
3.3V/2.5VꢀPowerꢀSupply
Vddqꢀ
IsolatedꢀOutputꢀBufferꢀSupply:
3.3V/2.5V
BWa-BWdꢀ
BWEꢀ
Vssꢀ
ZZꢀ
Ground
CE, CE2, CE2ꢀ SynchronousꢀChipꢀEnable
CLK Synchronous Clock
SnoozeꢀEnable
8ꢀ
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
100-PIN QFP (256K ꢀ 32)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable option)
PIN DESCRIPTIONS
DQa-DQdꢀ
GWꢀ
SynchronousꢀDataꢀInput/Output
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
OutputꢀEnable
A0, A1
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
MODEꢀ
OEꢀ
A
Synchronous Address Inputs
ADSC
ADSP
ADV
Synchronous Controller Address Status
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
Vddꢀ
3.3V/2.5VꢀPowerꢀSupply
Vddqꢀ
IsolatedꢀOutputꢀBufferꢀSupply:
3.3V/2.5V
BWa-BWdꢀ
BWEꢀ
Vssꢀ
ZZꢀ
Ground
SnoozeꢀEnable
CE, CE2, CE2ꢀ SynchronousꢀChipꢀEnable
CLK Synchronous Clock
9
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
100-PIN QFP (512K ꢀ 18)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
NC
NC
DDQ
VDDQ
V
VSS
NC
DQPa
DQa
DQa
VSS
VSS
NC
NC
DQb
DQb
VSS
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
V
DDQ
DQb
DQb
NC
DQa
DQa
VSS
NC
VDD
NC
V
DD
VDD
ZZ
VDD
NC
VSS
DQb
DQb
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
ZZ
DQa
DQa
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
VDDQ
V
DDQ
VSS
DQb
DQb
DQPb
NC
VSS
DQa
DQa
NC
NC
VSS
NC
VSS
VDDQ
NC
NC
NC
VSS
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable Option)
(2 Chip-Enable Option)
PIN DESCRIPTIONS
DQPa-DQPbꢀ ParityꢀDataꢀI/O;ꢀDQPaꢀisꢀparityꢀforꢀ
DQa1-8;ꢀDQPbꢀisꢀparityꢀforꢀDQb1-8
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
GWꢀ
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
OutputꢀEnable
A
Synchronous Address Inputs
MODEꢀ
OEꢀ
ADSC
ADSP
ADV
Synchronous Controller Address Status
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
Vddꢀ
3.3V/2.5VꢀPowerꢀSupply
Vddqꢀ
IsolatedꢀOutputꢀBufferꢀSupply:
3.3V/2.5V
BWa-BWbꢀ
BWEꢀ
Vssꢀ
ZZꢀ
Ground
CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable
SnoozeꢀEnable
CLK
Synchronous Clock
DQa-DQbꢀ
SynchronousꢀDataꢀInput/Output
10
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE
CLK
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Xꢀ
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
SnoozeꢀꢀMode,ꢀPower-Downꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
WriteꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
Noneꢀ
Noneꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Noneꢀ
Lꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Nextꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
Lꢀ
High-Z
D
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Nextꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
High-Z
D
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Lꢀ
D
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Hꢀ
Lꢀ
High-Z
Q
Hꢀ
Xꢀ
Xꢀ
High-Z
D
Lꢀ
D
NOTE:
1.ꢀ Xꢀmeansꢀ“Don’tꢀCare.”ꢀHꢀmeansꢀlogicꢀHIGH.ꢀLꢀmeansꢀlogicꢀLOW.
2.ꢀ ForꢀWRITE, L means one or more byte write enable signals (BWa-d) and BWEꢀareꢀLOWꢀorꢀGWꢀisꢀLOW.ꢀWRITEꢀ=ꢀHꢀforꢀall
BWx, BWE, GWꢀHIGH.
3.ꢀ BWaꢀenablesꢀWRITEsꢀtoꢀDQa’sꢀandꢀDQPa.ꢀBWbꢀenablesꢀWRITEsꢀtoꢀDQb’sꢀandꢀDQPb.ꢀBWcꢀenablesꢀWRITEsꢀtoꢀDQc’sꢀ and
DQPc.ꢀBWdꢀenablesꢀWRITEsꢀtoꢀDQd’sꢀandꢀDQPd.ꢀDQPaꢀandꢀDQPbꢀareꢀavailableꢀonꢀtheꢀx18ꢀversion.ꢀ DQPa-DQPdꢀareꢀavail-
ableꢀonꢀtheꢀx36ꢀversion.
4.ꢀ AllꢀinputsꢀexceptꢀOEꢀandꢀZZꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimesꢀaroundꢀtheꢀrisingꢀedgeꢀ(LOWꢀtoꢀHIGH)ꢀofꢀCLK.
5.ꢀ Waitꢀstatesꢀareꢀinsertedꢀbyꢀsuspendingꢀburst.
6.ꢀ ForꢀaꢀWRITEꢀoperationꢀfollowingꢀaꢀREADꢀoperation,ꢀOEꢀmustꢀbeꢀHIGHꢀbeforeꢀtheꢀinputꢀdataꢀsetupꢀtimeꢀandꢀheldꢀHIGHꢀduring
the input data hold time.
7.ꢀ ThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputsꢀwillꢀbeꢀinꢀHigh-Zꢀduringꢀpower-up.
8.ꢀ ADSPꢀLOWꢀalwaysꢀinitiatesꢀanꢀinternalꢀREADꢀatꢀtheꢀL-HꢀedgeꢀofꢀCLK.ꢀAꢀWRITEꢀisꢀperformedꢀbyꢀsettingꢀoneꢀorꢀmoreꢀbyteꢀwrite
enable signals and BWEꢀLOWꢀorꢀGWꢀLOWꢀforꢀtheꢀsubsequentꢀL-HꢀedgeꢀofꢀCLK.ꢀSeeꢀWRITEꢀtimingꢀdiagramꢀforꢀclarification.
PARTIAL TRUTH TABLE
Function
GW
BWE
H
BWa
X
BWb
X
BWc
X
BWd
X
Read
H
Read
H
L
H
H
H
H
WriteꢀByteꢀ1ꢀ
WriteꢀAllꢀBytesꢀ
WriteꢀAllꢀBytesꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
X
11
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAꢀIMUM RATINgS(1)
Symbol Parameter
Value
–55ꢀtoꢀ+150
1.6ꢀ
Unit
°C
W
TsTg
Pd
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
IOuTꢀ
OutputꢀCurrentꢀ(perꢀI/O)ꢀ
100ꢀ
mA
V
V
VIN, VOuTꢀ VoltageꢀRelativeꢀtoꢀVssꢀforꢀI/OꢀPinsꢀ
–0.5ꢀtoꢀVddq + 0.5
–0.5ꢀtoꢀVdd + 0.5
VINꢀ
VoltageꢀRelativeꢀtoꢀVssꢀforꢀꢀ
for Address and Control Inputs
Vddꢀ
VoltageꢀonꢀVddꢀSupplyꢀRelativeꢀtoꢀVssꢀ
–0.5ꢀtoꢀ4.6
V
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀperma-
nentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀ
at these or any other conditions above those indicated in the operational sections of this
specificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀ
periods may affect reliability.
2.ꢀThisꢀdeviceꢀcontainsꢀcircuityꢀtoꢀprotectꢀtheꢀinputsꢀagainstꢀdamageꢀdueꢀtoꢀhighꢀstaticꢀvoltages
orꢀelectricꢀfields;ꢀhowever,ꢀprecautionsꢀmayꢀbeꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀ
higherꢀthanꢀmaximumꢀratedꢀvoltagesꢀtoꢀthisꢀhigh-impedanceꢀcircuit.
3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHigh-Zꢀatꢀpowerꢀup.
12
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
OPERATINg RANgE (IS61LPSꢀꢀꢀꢀꢀ)
Ranꢁe
Ambient Temperature
VDD
VDDq
Commercialꢀ
Industrialꢀ
0°Cꢀtoꢀ+70°Cꢀ
3.3Vꢀ+ꢀ5%
3.3Vꢀ+ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
–40°Cꢀtoꢀ+85°C
OPERATINg RANgE (IS61VPSꢀꢀꢀꢀꢀ)
Ranꢁe
Ambient Temperature
VDD
VDDq
Commercialꢀ
Industrialꢀ
0°Cꢀtoꢀ+70°Cꢀ
2.5Vꢀ+ꢀ5%
ꢀ2.5Vꢀ+ꢀ5%
ꢀ2.5Vꢀ+ꢀ5%
ꢀ2.5Vꢀ+ꢀ5%
–40°Cꢀtoꢀ+85°C
OPERATINg RANgE (IS64LPSꢀꢀꢀꢀꢀ)
Ranꢁe
Ambient Temperature
VDD
VDDq
Automotiveꢀ
–40°Cꢀtoꢀ+125°C
3.3Vꢀ+ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
3.3V
Min.
2.5V
Min.
Symbol Parameter
Test Conditions
Max.
Max.
Unit
VOh
OutputꢀHIGHꢀVoltageꢀ
IOh = –4.0ꢀmAꢀ(3.3V)ꢀ
IOh = –1.0ꢀmAꢀ(2.5V)
2.4ꢀ
—ꢀ
2.0ꢀ
—ꢀ
Vꢀ
VOl
OutputꢀLOWꢀVoltageꢀ
IOl = 8.0ꢀmAꢀ(3.3V)ꢀ
IOl = 1.0ꢀmAꢀ(2.5V)
—ꢀ
0.4ꢀ
—ꢀ
0.4ꢀ
Vꢀ
VIh
VIl
IlI
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage
2.0ꢀ Vdd +ꢀ0.3ꢀ
1.7 Vdd + 0.3
V
V
-0.3ꢀ
-5ꢀ
0.8ꢀ
5ꢀ
-0.3ꢀ
-5ꢀ
0.7ꢀ
5ꢀ
(1)
InputꢀLeakageꢀCurrentꢀ Vssꢀ≤ VIN ≤ Vdd
µA
µA
IlO
OutputꢀLeakageꢀCurrent Vssꢀ≤ VOuT ≤ Vddq,
OE = VIh
-5ꢀ
5ꢀ
-5ꢀ
5ꢀ
Integrated Silicon Solution, Inc.ꢀ
13
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-250
MAꢀ
-200
MAꢀ
-166
MAꢀ
Symbol Parameter
Test Conditions
Temp. ranꢁe
x18
x36
x18
x36
x18 x36
Unit
Icc
ACꢀOperatingꢀ
Supply Current
DeviceꢀSelected,ꢀꢀ
OE = VIh, ZZ ≤ VIl,
All Inputs ≤ 0.2V or
≥ Vdd – 0.2V,
Com.ꢀ
Ind.
Auto.
275ꢀ 275ꢀ
300ꢀ 300ꢀ
250ꢀ 250ꢀ
275ꢀ 275ꢀ
225ꢀ 225ꢀ
250 250
300 300
mA
CycleꢀTimeꢀ≥ tkc min.
Isb
StandbyꢀCurrentꢀ
TTLꢀInputꢀ
DeviceꢀDeselected,ꢀꢀ
Vdd = Max.,ꢀ
All Inputs ≤ VIl or ≥ VIh,
ZZ ≤ VIl, fꢀ=ꢀMax.
Com.
Ind.ꢀ
AuTO.
150 150
150ꢀ 150ꢀ
150 150
150ꢀ 150ꢀ
150ꢀ 150ꢀ
150ꢀ 150
200 200
mA
IsbIꢀ
StandbyꢀCurrentꢀ
cMOs Input
DeviceꢀDeselected,ꢀ
Vdd = Max.,ꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
100 100
105ꢀ 105ꢀ
100 100
105ꢀ 105ꢀ
100 100
105ꢀ 105
130ꢀ 130
mA
VIN
≤
ꢀVss +ꢀ0.2Vꢀorꢀ
≥Vdd –ꢀ0.2Vꢀ
ꢀfꢀ=ꢀ0
Note:
1.ꢀ MODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀVddꢀorꢀVss.ꢀItꢀexhibitsꢀ±100µAꢀmaximumꢀleakageꢀcurrentꢀwhenꢀtiedꢀtoꢀ≤
Vssꢀ+ꢀ0.2Vꢀorꢀ≥ꢀVddꢀ–ꢀ0.2V.
14
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
6ꢀ
Unit
pF
cIN
Input Capacitance
Input/OutputꢀCapacitanceꢀ
cOuTꢀ
VOuT = 0V
8ꢀ
pF
Notes:
1.ꢀ Testedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTA = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ3.0V
1.5ꢀns
InputꢀandꢀOutputꢀTimingꢀ
1.5V
and Refe rence Level
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
AC TEST LOADS
317 Ω
3.3V
Z
O
= 50Ω
OUTPUT
Output
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Fiꢁure 1
Fiꢁure 2
Integrated Silicon Solution, Inc.ꢀ
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Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
2.5V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ2.5V
1.5ꢀns
InputꢀandꢀOutputꢀTimingꢀ
1.25V
and Reference Level
OutputꢀLoadꢀ
SeeꢀFiguresꢀ3ꢀandꢀ4
2.5 I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
2.5V
Z
O
= 50Ω
OUTPUT
Output
50Ω
1,538 Ω
5 pF
Including
jig and
scope
1.25V
Fiꢁure 3
Fiꢁure 4
16
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
Address Status HoldTimeꢀ
tSs
Address Status Setup
Timeꢀ
—ꢀ
—ꢀ
ns
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
READ/WRITE CYCLE SWITCHINg CHARACTERISTICS (OverꢀOperatingꢀRange)
-250
-200
Min.
-166
Min.
Symbol
fMAxꢀ
Parameter
Min.
—ꢀ
Max.
250ꢀ
—ꢀ
Max.
200ꢀ
—ꢀ
Max.
166ꢀ
—ꢀ
—ꢀ
—ꢀ
3.8ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
Unit
MHz
ns
ClockꢀFrequencyꢀ
—ꢀ
5ꢀ
—ꢀ
6ꢀ
tkcꢀ
CycleꢀTimeꢀ
4.0ꢀ
1.7ꢀ
1.7ꢀ
—ꢀ
tkhꢀ
ClockꢀHighꢀTimeꢀ
—ꢀ
2ꢀ
—ꢀ
2.4ꢀ
2.3ꢀ
—ꢀ
ns
tklꢀ
ClockꢀLowꢀTimeꢀ
—ꢀ
2ꢀ
—ꢀ
ns
tkqꢀ
ClockꢀAccessꢀTimeꢀ
2.6ꢀ
—ꢀ
—ꢀ
1.5ꢀ
1ꢀ
3.1ꢀ
—ꢀ
ns
tkqx(2)ꢀ
tkqlZ(2,3)ꢀ
tkqhZ(2,3)ꢀ
tOEqꢀ
tOElZ(2,3)ꢀ
tOEhZ(2,3)ꢀ
tAsꢀ
ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ
ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ
ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀ
OutputꢀEnableꢀtoꢀOutputꢀValidꢀ
OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ
OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀ
AddressꢀSetupꢀTimeꢀ
0.8ꢀ
0.8ꢀ
—ꢀ
1.5ꢀ
1.5ꢀ
3.5ꢀ
3.5ꢀ
0ꢀ
ns
—ꢀ
—ꢀ
ns
2.6ꢀ
2.6ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
3.0ꢀ
3.1ꢀ
—ꢀ
ns
—ꢀ
ns
0ꢀ
ns
—ꢀ
2.6ꢀ
—ꢀ
—ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
3.0ꢀ
—ꢀ
3.5ꢀ
1.7ꢀ
1.7ꢀ
1.7ꢀ
1.7ꢀ
1.7ꢀ
ns
1.2ꢀ
1.2ꢀ
1.2ꢀ
1.2ꢀ
1.2ꢀ
ns
tWsꢀ
Read/WriteꢀSetupꢀTimeꢀ
ChipꢀEnableꢀSetupꢀTimeꢀ
AddressꢀAdvanceꢀSetupꢀTimeꢀ
—ꢀ
—ꢀ
ns
tcEsꢀ
—ꢀ
—ꢀ
ns
tAVsꢀ
—ꢀ
—ꢀ
ns
tds
DataꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTime
WriteꢀHoldꢀTimeꢀ
1.2ꢀ
0.3ꢀ
0.3ꢀ
0.3ꢀ
0.3ꢀ
0.3ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
1.7ꢀ
0.7ꢀ
0.7ꢀ
0.7ꢀ
0.7ꢀ
0.7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
tAhꢀ
tWhꢀ
tcEhꢀ
tAVhꢀ
tSHꢀ
ChipꢀEnableꢀHoldꢀTimeꢀ
AddressꢀAdvanceꢀHoldꢀTimeꢀ
tdhꢀ
DataꢀHoldꢀTimeꢀ
0.3ꢀ
—ꢀ
—ꢀ
2ꢀ
0.4ꢀ
—ꢀ
—ꢀ
2ꢀ
0.7ꢀ
—ꢀ
—ꢀ
2ꢀ
ns
tPdsꢀ
tPus
ZZꢀHighꢀtoꢀPowerꢀDownꢀ
ZZꢀLowꢀtoꢀPowerꢀDownꢀ
cyc
cyc
—ꢀ
2ꢀ
—ꢀ
2ꢀ
—ꢀ
2ꢀ
Note:
1. ConfigurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.ꢀ
2. Guaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.
3.ꢀ TestedꢀwithꢀloadꢀinꢀFigureꢀ2.
17
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
READ CYCLE TIMINg
tKC
CLK
ADSP
ADSC
tKH
tKL
ADSP is blocked by CE inactive
tSS
tSH
ADSC initiate read
tSS
tSH
t
AVH
tAVS
Suspend Burst
ADV
tAS
tAH
Address
RD1
RD2
RD3
t
WS
WS
t
WH
WH
GW
BWE
BWx
t
t
tCES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
tOEHZ
tOEQ
OE
t
KQX
tOELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
tKQ
DATAIN
Pipelined Read
18
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
WRITE CYCLE TIMINg
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
SS
tSH
t
AVH
tAVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Unselected
Single Write
Write
Integrated Silicon Solution, Inc.ꢀ
19
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Temperature
Ranꢁe
Min. Max.
Unit
Isb2ꢀ
CurrentꢀduringꢀSNOOZEꢀMODEꢀ ZZꢀ≥ꢀVihꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
50ꢀ
60ꢀ
75
mAꢀ
tPdsꢀ
tPusꢀ
tZZIꢀ
ZZꢀactiveꢀtoꢀinputꢀignoredꢀ
—ꢀ
2ꢀ
2ꢀ
—ꢀ
2ꢀ
cycle
cycle
cycle
ns
ZZꢀinactiveꢀtoꢀinputꢀsampledꢀ
ZZꢀactiveꢀtoꢀSNOOZEꢀcurrentꢀ
ZZꢀinactiveꢀtoꢀexitꢀSNOOZEꢀcurrentꢀ
—ꢀ
0ꢀ
trZZIꢀ
—ꢀ
SNOOZE MODE TIMINg
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
ISB2
tRZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
20
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAg)
TEST ACCESS PORT (TAP) - TEST CLOCK
TheꢀIS61LPS/VPSxxxxxxꢀproductsꢀhaveꢀaꢀserialꢀboundaryꢀ
scanꢀTestꢀAccessꢀPortꢀ(TAP)ꢀinꢀtheꢀBGAꢀpackageꢀonly.ꢀ
(TheꢀQFPꢀpackageꢀnotꢀavailable.)ꢀThisꢀportꢀoperatesꢀinꢀ
accordancewithIEEEꢀStandardꢀ1149.1-1900,ꢀbutꢀdoesꢀnotꢀ
includeꢀallꢀfunctionsꢀrequiredꢀforꢀfullꢀ1149.1ꢀcompliance.ꢀ
TheseꢀfunctionsꢀfromꢀtheꢀIEEEꢀspecificationꢀareꢀexcludedꢀ
because they place added delay in the critical speed path
ofꢀtheꢀSRAM.ꢀTheꢀTAPꢀcontrollerꢀoperatesꢀinꢀaꢀmannerꢀthatꢀ
does not conflict with the performance of other devices us-
ingꢀ1149.1ꢀfullyꢀcompliantꢀTAPs.ꢀTheꢀTAPꢀoperatesꢀusingꢀ
JEDECꢀstandardꢀ2.5VꢀI/Oꢀlogicꢀlevels.
TheꢀtestꢀclockꢀisꢀonlyꢀusedꢀwithꢀtheTAPꢀcontroller.ꢀAllꢀinputsꢀ
areꢀcapturedꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputsꢀareꢀ
drivenꢀfromꢀtheꢀfallingꢀedgeꢀofꢀTCK.
TEST MODE SELECT (TMS)
TheꢀTMSꢀinputꢀisꢀusedꢀtoꢀsendꢀcommandsꢀtoꢀtheꢀTAPꢀ
controllerꢀandꢀisꢀsampledꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCK.ꢀThisꢀ
pinꢀmayꢀbeꢀleftꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀnotꢀused.ꢀTheꢀpinꢀ
isꢀinternallyꢀpulledꢀup,ꢀresultingꢀinꢀaꢀlogicꢀHIGHꢀlevel.
TEST DATA-IN (TDI)
TheꢀTDIꢀpinꢀisꢀusedꢀtoꢀseriallyꢀinputꢀinformationꢀtoꢀtheꢀ
registers and can be connected to the input of any regis-
ter.ꢀTheꢀregisterꢀbetweenꢀTDIꢀandꢀTDOꢀisꢀchosenꢀbyꢀtheꢀ
instructionꢀ loadedꢀ intoꢀ theꢀTAPꢀ instructionꢀ register.ꢀ Forꢀ
informationꢀonꢀinstructionꢀregisterꢀloading,ꢀseeꢀtheꢀTAPꢀ
ControllerꢀStateꢀDiagram.ꢀTDIꢀisꢀinternallyꢀpulledꢀupꢀandꢀ
canꢀbeꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀunusedꢀinꢀanꢀapplica-
tion.ꢀTDIꢀisꢀconnectedꢀtoꢀtheꢀMostꢀSignificantꢀBitꢀ(MSB)ꢀ
DISABLINg THE JTAg FEATURE
TheꢀSRAMꢀcanꢀoperateꢀwithoutꢀusingꢀtheꢀJTAGꢀfeature.ꢀ
Toꢀ disableꢀ theꢀTAPꢀ controller,ꢀTCKꢀ mustꢀ beꢀ tiedꢀ LOWꢀ
(Vss)ꢀtoꢀpreventꢀclockingꢀofꢀtheꢀdevice.ꢀTDIꢀandꢀTMSꢀareꢀ
internallyꢀpulledꢀupꢀandꢀmayꢀbeꢀdisconnected.ꢀTheyꢀmayꢀ
alternatelyꢀbeꢀconnectedꢀtoꢀVddꢀthroughꢀaꢀpull-upꢀresistor.ꢀ
TDOꢀshouldꢀbeꢀleftꢀdisconnected.ꢀOnꢀpower-up,ꢀtheꢀdeviceꢀ
will start in a reset state which will not interfere with the
device operation.
on any register.
TAP CONTROLLER BLOCK DIAgRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
21
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TEST DATA OUT (TDO)
TheꢀTDOꢀoutputꢀpinꢀisꢀusedꢀtoꢀseriallyꢀclockꢀdata-outꢀfromꢀ
theꢀregisters.ꢀTheꢀoutputꢀisꢀactiveꢀdependingꢀonꢀtheꢀcurrentꢀ
state of the TAP state machine (see TAP Controller State
Diagram).ꢀTheꢀoutputꢀchangesꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCKꢀ
andꢀTDOꢀisꢀconnectedꢀtoꢀtheꢀLeastꢀSignificantꢀBitꢀ(LSB)ꢀ
of any register.
isterꢀisꢀsetꢀLOWꢀ(Vss)ꢀwhenꢀtheꢀBYPASSꢀinstructionꢀisꢀ
executed.
Boundary Scan Reꢁister
Theꢀboundaryꢀscanꢀregisterꢀisꢀconnectedꢀtoꢀallꢀinputꢀandꢀ
output pins on the SRAM.Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
densityꢀdevices.ꢀTheꢀx36ꢀconfigurationꢀhasꢀaꢀ75-bit-longꢀ
registerꢀandꢀtheꢀx18ꢀconfigurationꢀalsoꢀhasꢀaꢀ75-bit-longꢀ
register.ꢀTheꢀboundaryꢀscanꢀregisterꢀisꢀloadedꢀwithꢀtheꢀ
contentsꢀofꢀtheꢀRAMꢀInputꢀandꢀOutputꢀringꢀwhenꢀtheꢀTAPꢀ
controllerꢀisꢀinꢀtheꢀCapture-DRꢀstateꢀandꢀthenꢀplacedꢀbe-
tween the TDI and TDO pins when the controller is moved
to the Shift-DRꢀstate.ꢀTheꢀEXTEST,ꢀSAMPLE/PRELOADꢀ
andꢀSAMPLE-Zꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀcaptureꢀtheꢀ
contentsꢀofꢀtheꢀInputꢀandꢀOutputꢀring.
PERFORMINg A TAP RESET
AꢀResetꢀisꢀperformedꢀbyꢀforcingꢀTMSꢀHIGHꢀ(Vdd) for five
risingꢀedgesꢀofꢀTCK.ꢀRESETꢀmayꢀbeꢀperformedꢀwhileꢀtheꢀ
SRAMꢀisꢀoperatingꢀandꢀdoesꢀnotꢀaffectꢀitsꢀoperation.ꢀAtꢀ
power-up,ꢀtheꢀTAPꢀisꢀinternallyꢀresetꢀtoꢀensureꢀthatꢀTDOꢀ
comesꢀupꢀinꢀaꢀhigh-Zꢀstate.
TAP REgISTERS
RegistersꢀareꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
andꢀallowꢀdataꢀtoꢀbeꢀscannedꢀintoꢀandꢀoutꢀofꢀtheꢀSRAMꢀ
test circuitry. Onlyꢀoneꢀregisterꢀcanꢀbeꢀselectedꢀatꢀaꢀtimeꢀ
throughꢀtheꢀinstructionꢀregisters.ꢀDataꢀisꢀseriallyꢀloadedꢀ
intoꢀtheꢀTDIꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputꢀonꢀ
theꢀTDOꢀpinꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCK.
TheꢀBoundaryꢀScanꢀOrderꢀtablesꢀshowꢀtheꢀorderꢀinꢀwhichꢀ
theꢀbitsꢀareꢀconnected.ꢀEachꢀbitꢀcorrespondsꢀtoꢀoneꢀofꢀtheꢀ
bumpsꢀonꢀtheꢀSRAMꢀpackage.ꢀTheꢀMSBꢀofꢀtheꢀregisterꢀisꢀ
connectedꢀtoꢀTDI,ꢀandꢀtheꢀLSBꢀisꢀconnectedꢀtoꢀTDO.
Scan Reꢁister Sizes
Instruction Reꢁister
Reꢁister
Bit Size
(x18)
3ꢀ
Bit Size
(x36)
3ꢀ
Three-bitꢀinstructionsꢀcanꢀbeꢀseriallyꢀloadedꢀintoꢀtheꢀin-
structionꢀregister.ꢀThisꢀregisterꢀisꢀloadedꢀwhenꢀitꢀisꢀplacedꢀ
between the TDI and TDO pins. (See TAPꢀControllerꢀBlockꢀ
Diagram)ꢀ Atꢀpower-up,ꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀ
withꢀtheꢀIDCODEꢀinstruction.ꢀItꢀisꢀalsoꢀloadedꢀwithꢀtheꢀ
IDCODEꢀinstructionꢀifꢀtheꢀcontrollerꢀisꢀplacedꢀinꢀaꢀresetꢀ
state as previously described.
Name
Instructionꢀ
Bypassꢀ
1ꢀ
1ꢀ
IDꢀ
32ꢀ
32ꢀ
BoundaryꢀScanꢀ
75ꢀ
75ꢀ
WhenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCaptureIRꢀstate,ꢀtheꢀtwoꢀ
leastꢀsignificantꢀbitsꢀareꢀloadedꢀwithꢀaꢀbinaryꢀ“01”ꢀpatternꢀtoꢀ
allow for fault isolation of the board level serial test path.
Identification (ID) Reꢁister
Bypass Reꢁister
TheꢀIDꢀregisterꢀisꢀloadedꢀwithꢀaꢀvendor-specific,ꢀ32-bitꢀ
codeꢀduringꢀtheꢀCapture-DRꢀstateꢀwhenꢀtheꢀIDCODEꢀcom-
mandꢀisꢀloadedꢀtoꢀtheꢀinstructionꢀregister.ꢀTheꢀIDCODEꢀ
isꢀhardwiredꢀintoꢀtheꢀSRAMꢀandꢀcanꢀbeꢀshiftedꢀoutꢀwhenꢀ
theꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀShift-DRꢀstate.ꢀTheꢀIDꢀregisterꢀ
has vendor code and other information described in the
IdentificationꢀRegisterꢀDefinitionsꢀtable.
Toꢀsaveꢀtimeꢀwhenꢀseriallyꢀshiftingꢀdataꢀthroughꢀregisters,ꢀ
itꢀisꢀsometimesꢀadvantageousꢀtoꢀskipꢀcertainꢀstates.ꢀTheꢀ
bypassꢀregisterꢀisꢀaꢀsingle-bitꢀregisterꢀthatꢀcanꢀbeꢀplacedꢀ
betweenꢀTDIꢀandꢀTDOꢀpins.ꢀThisꢀallowsꢀdataꢀtoꢀbeꢀshiftedꢀ
through the SRAMꢀwithꢀminimalꢀdelay.ꢀTheꢀbypassꢀreg-
IDENTIFICATION REgISTER DEFINITIONS
Instruction Field
Description
256K x 36
xxxxꢀ
512K x 18
xxxxꢀ
RevisionꢀNumberꢀ (31:28)ꢀ
DeviceꢀDepthꢀ (27:23)ꢀ
DeviceꢀWidthꢀ (22:18)ꢀ
ISSIꢀDeviceꢀIDꢀ (17:12)ꢀ
ISSIꢀJEDECꢀIDꢀ (11:1)ꢀ
IDꢀRegisterꢀPresenceꢀ (0)ꢀ
Reservedꢀforꢀversionꢀnumber.ꢀ
DefinesꢀdepthꢀofꢀSRAM.ꢀ256Kꢀorꢀ512Kꢀ
DefinesꢀwidthꢀofꢀtheꢀSRAM.ꢀx36ꢀorꢀx18ꢀ
Reservedꢀforꢀfutureꢀuse.ꢀ
00111ꢀ
01000ꢀ
00011ꢀ
xxxxxꢀ
00100ꢀ
xxxxxꢀ
AllowsꢀuniqueꢀidentificationꢀofꢀSRAMꢀvendor.ꢀ
IndicateꢀtheꢀpresenceꢀofꢀanꢀIDꢀregister.ꢀ
00011010101ꢀ
1ꢀ
00011010101
1ꢀ
22
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
The
TAPꢀcontrollerꢀrecognizesꢀanꢀall-0ꢀinstruction.Whenꢀanꢀ
Eightꢀinstructionsꢀareꢀpossibleꢀwithꢀtheꢀthree-bitꢀinstructionꢀ
register and all combinations are listed in the Instruction
Codeꢀtable.ꢀThreeꢀinstructionsꢀareꢀlistedꢀasꢀRESERVED
and should not be used and the other five instructions are
describedꢀbelow.ꢀTheꢀTAPꢀcontrollerꢀusedꢀinꢀthisꢀSRAMꢀ
isꢀnotꢀfullyꢀcompliantꢀwithꢀtheꢀ1149.1ꢀconventionꢀbecauseꢀ
some mandatory instructions are not fully implemented.
TheꢀTAPꢀcontrollerꢀcannotꢀbeꢀusedꢀtoꢀloadꢀaddress,ꢀdataꢀorꢀ
control signals and cannot preload the Input or Output buf-
fers.ꢀTheꢀSRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD;ꢀinsteadꢀitꢀperformsꢀaꢀcaptureꢀofꢀtheꢀInputs and
Outputꢀringꢀwhenꢀtheseꢀinstructionsꢀareꢀexecuted.ꢀInstruc-
tionsꢀareꢀloadedꢀintoꢀtheꢀTAPꢀcontrollerꢀduringꢀtheꢀShift-IRꢀ
stateꢀwhenꢀtheꢀinstructionꢀregisterꢀisꢀplacedꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀDuringꢀthisꢀstate,ꢀinstructionsꢀareꢀshiftedꢀfromꢀ
theꢀinstructionꢀregisterꢀthroughꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀToꢀ
executeꢀanꢀinstructionꢀonceꢀitꢀisꢀshiftedꢀin,ꢀtheꢀTAPꢀcontrol-
lerꢀmustꢀbeꢀmovedꢀintoꢀtheꢀUpdate-IRꢀstate.
SAMPLE/PRELOADꢀisꢀaꢀ1149.1ꢀmandatoryꢀinstruction.Theꢀ
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP INSTRUCTION SET
SAMPLE/PRELOAD
PRELOADꢀportionꢀofꢀthisꢀinstructionꢀisꢀnotꢀimplemented,ꢀsoꢀ
theꢀTAPꢀcontrollerꢀisꢀnotꢀfullyꢀ1149.1ꢀcompliant.ꢀWhenꢀtheꢀ
SAMPLE/PRELOADꢀinstructionꢀisꢀloadedꢀtoꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-DRꢀ
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
ItꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀtheꢀTAPꢀcontrollerꢀclockꢀoper-
atesꢀatꢀaꢀfrequencyꢀupꢀtoꢀ10ꢀMHz,ꢀwhileꢀtheꢀSRAMꢀclockꢀ
runsꢀmoreꢀthanꢀanꢀorderꢀofꢀmagnitudeꢀfaster.ꢀBecauseꢀofꢀ
theꢀclockꢀfrequencyꢀdifferences,ꢀitꢀisꢀpossibleꢀthatꢀduringꢀ
theꢀCapture-DRꢀstate,ꢀanꢀinputꢀorꢀoutputꢀwillꢀunder-goꢀaꢀ
transition.ꢀTheꢀTAPꢀmayꢀattemptꢀaꢀsignalꢀcaptureꢀwhileꢀinꢀ
transitionꢀ(metastableꢀstate).Theꢀdeviceꢀwillꢀnotꢀbeꢀharmed,ꢀ
but there is no guarantee of the value that will be captured
or repeatable results.
Toꢀguaranteeꢀthatꢀtheꢀboundaryꢀscanꢀregisterꢀwillꢀcaptureꢀ
theꢀcorrectꢀsignalꢀvalue,ꢀtheꢀSRAMꢀsignalꢀmustꢀbeꢀstabilizedꢀ
longꢀenoughꢀtoꢀmeetꢀtheꢀTAPꢀcontroller’sꢀcaptureꢀset-upꢀ
plusholdtimes(tcs andtch).ꢀToꢀinsureꢀthatꢀtheꢀSRAMꢀclockꢀ
input is captured correctly, designs need a way to stop (or
slow)ꢀtheꢀclockꢀduringꢀaꢀSAMPLE/PRELOADꢀinstruction.ꢀ
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK captured
in the boundary scan register.
EꢀTEST
EXTESTꢀisꢀaꢀmandatoryꢀ1149.1ꢀinstructionꢀwhichꢀisꢀtoꢀbeꢀ
executedꢀwheneverꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀwithꢀ
allꢀ0s.ꢀBecauseꢀEXTESTꢀisꢀnotꢀimplementedꢀinꢀtheꢀTAPꢀ
controller,ꢀthisꢀdeviceꢀisꢀnotꢀ1149.1ꢀstandardꢀcompliant.ꢀ
Onceꢀtheꢀdataꢀisꢀcaptured,ꢀitꢀisꢀpossibleꢀtoꢀshiftꢀoutꢀtheꢀdataꢀ
byꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀShift-DRꢀstate.ꢀThisꢀplacesꢀtheꢀ
boundaryꢀscanꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpins.
EXTESTꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregister,ꢀ
theꢀSRAMꢀrespondsꢀasꢀifꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ
hasꢀbeenꢀloaded.ꢀThereꢀisꢀaꢀdifferenceꢀbetweenꢀtheꢀinstruc-
tions, unlike the SAMPLE/PRELOADꢀinstruction,ꢀEXTESTꢀ
placesꢀtheꢀSRAMꢀoutputsꢀinꢀaꢀHigh-Zꢀstate.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
willꢀhaveꢀtheꢀsameꢀeffectꢀasꢀtheꢀPause-DRꢀcommand.
IDCODE
Theꢀ IDCODEꢀ instructionꢀ causesꢀ aꢀ vendor-specific,ꢀ 32-
bit code to be loaded into the instruction register. It also
placesꢀtheꢀinstructionꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pinsꢀandꢀallowsꢀtheꢀIDCODEꢀtoꢀbeꢀshiftedꢀoutꢀofꢀtheꢀdeviceꢀ
whenꢀtheꢀTAPꢀcontrollerꢀentersꢀtheꢀShift-DRꢀstate.ꢀTheꢀ
IDCODEꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregisterꢀ
uponꢀpower-upꢀorꢀwheneverꢀtheꢀTAPꢀcontrollerꢀisꢀgivenꢀaꢀ
test logic reset state.
BYPASS
WhenꢀtheꢀBYPASSꢀinstructionꢀisꢀloadedꢀinꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀisꢀplacedꢀinꢀaꢀShift-DRꢀstate,ꢀ
theꢀbypassꢀregisterꢀisꢀplacedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pins.ꢀTheꢀadvantageꢀofꢀtheꢀBYPASSꢀinstructionꢀisꢀthatꢀitꢀ
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
RESERVED
Theꢀ SAMPLE-Zꢀ instructionꢀ causesꢀ theꢀ boundaryꢀ scanꢀ
registerꢀtoꢀbeꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
whenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀaꢀShift-DRꢀstate.ꢀItꢀalsoꢀplacesꢀ
allꢀSRAMꢀoutputsꢀintoꢀaꢀHigh-Zꢀstate.
Theseꢀinstructionsꢀareꢀnotꢀimplementedꢀbutꢀareꢀreservedꢀ
forꢀfutureꢀuse.ꢀDoꢀnotꢀuseꢀtheseꢀinstructions.
Integrated Silicon Solution, Inc.ꢀ
23
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
INSTRUCTION CODES
Code
Instruction
Description
000ꢀ
EXTESTꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbe-
tweenꢀtheꢀTDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputsꢀtoꢀHigh-Zꢀstate.ꢀThisꢀ
instructionꢀisꢀnotꢀ1149.1ꢀcompliant.
001ꢀ
010ꢀ
IDCODEꢀ
LoadsꢀtheꢀIDꢀregisterꢀwithꢀtheꢀvendorꢀIDꢀcodeꢀandꢀplacesꢀtheꢀregisterꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀaffectꢀSRAMꢀoperation.
SAMPLE-Zꢀ
CapturesꢀtheꢀInput/Outputꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbetweenꢀ
TDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputꢀdriversꢀtoꢀaꢀHigh-Zꢀstate.
011ꢀ
RESERVEDꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
100
SAMPLE/PRELOAD
ꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀ
between TDIꢀandꢀTDO.ꢀDoesꢀnotꢀaffectꢀtheꢀSRAMꢀoperation.ꢀThisꢀinstructionꢀdoesꢀnotꢀ
implementꢀ1149.1ꢀpreloadꢀfunctionꢀandꢀisꢀthereforeꢀnotꢀ1149.1ꢀcompliant.
101ꢀ
110ꢀ
111ꢀ
RESERVEDꢀ
RESERVEDꢀ
BYPASSꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.ꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
PlacesꢀtheꢀbypassꢀregisterꢀbetweenꢀTDIꢀandꢀTDO.ꢀThisꢀoperationꢀdoesꢀnot
affectꢀSRAMꢀoperation.
TAP CONTROLLER STATE DIAgRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
24
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP Electrical Characteristics OverꢀtheꢀOperatingꢀRange(1,2)
Symbol
VOh1
VOh2
VOl1
VOl2
VIh
Parameter
Test Conditions
Min.
1.7ꢀ
2.1ꢀ
—ꢀ
Max.
—ꢀ
Units
OutputꢀHIGHꢀVoltage
OutputꢀHIGHꢀVoltage
OutputꢀLOWꢀVoltage
OutputꢀLOWꢀVoltage
InputꢀHIGHꢀVoltage
InputꢀLOWꢀVoltage
Input Leakage Current
IOhꢀ=ꢀ–2.0ꢀmAꢀ
V
V
V
V
V
V
IOhꢀ=ꢀ–100ꢀ
IOlꢀ=ꢀ2.0ꢀmAꢀ
IOlꢀ=ꢀ100ꢀ Aꢀ
µ
A
—ꢀ
0.7
µ
—ꢀ
0.2
1.7
Vddꢀ+0.3ꢀ
0.7
VIl
–0.3
–10
Ix
Vss ≤ꢀVꢀIꢀ≤ꢀVddq
10ꢀ
µA
Notes:
1.ꢀ AllꢀVoltageꢀreferencedꢀtoꢀGround.
2.ꢀ Overshoot:ꢀVIh (AC) ≤ꢀꢀVddꢀ+1.5Vꢀforꢀtꢀ≤ tTcyc/2,
Undershoot:ꢀVIl (AC) ≥ -1.5Vꢀforꢀtꢀ≤ tTcyc/2,
Power-up:ꢀVIhꢀ<ꢀ2.6VꢀandꢀVddꢀ<ꢀ2.4VꢀandꢀVddqꢀ<ꢀ1.4Vꢀforꢀtꢀ<ꢀ200ꢀms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATINg RANgE)
Symbol Parameter
Min.
100ꢀ
—ꢀ
40
Max.
—ꢀ
10ꢀ
—
Unit
ns
tTcyc
fTf
TCKꢀClockꢀcycleꢀtime
TCKꢀClockꢀfrequencyꢀ
MHz
ns
tTh
TCKꢀClockꢀHIGH
tTl
TCKꢀClockꢀLOWꢀ
40ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
—ꢀ
0ꢀ
—
ns
tTMss
tTdIs
tcs
TMSꢀsetupꢀtoꢀTCKꢀClockꢀRise
TDIꢀsetupꢀtoꢀTCKꢀClockꢀRise
CaptureꢀsetupꢀtoꢀTCKꢀRise
TMSꢀholdꢀafterꢀTCKꢀClockꢀRise
TDIꢀHoldꢀafterꢀClockꢀRise
Capture hold after Clock Rise
TCKꢀLOWꢀtoꢀTDOꢀvalidꢀ
TCKꢀLOWꢀtoꢀTDOꢀinvalid
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20
ns
ns
ns
tTMsh
tTdIh
tch
ns
ns
ns
tTdOV
ns
tTdOx
—ꢀ
ns
Notes:
1.ꢀBothꢀtcs and tch referꢀtoꢀtheꢀset-upꢀandꢀholdꢀtimeꢀrequirementsꢀofꢀlatchingꢀdataꢀfromꢀtheꢀboundaryꢀscanꢀregister.
2.ꢀTestꢀconditionsꢀareꢀspecifiedꢀusingꢀtheꢀloadꢀinꢀTAPꢀACꢀtestꢀconditions.ꢀtr/tfꢀ=ꢀ1ꢀns.
Integrated Silicon Solution, Inc.ꢀ
25
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Inputꢀpulseꢀlevelsꢀ
0ꢀtoꢀ2.5V/0ꢀtoꢀ3.0V
Input rise and fall times
Inputꢀtimingꢀreferenceꢀlevelsꢀ
Outputꢀreferenceꢀlevelsꢀ
1ns
1.25V/1.5V
1.25V/1.5V
50Ω
Testꢀloadꢀterminationꢀsupplyꢀvoltageꢀ
Vtrigꢀ
1.25V/1.5V
1.25V/1.5V
Vtrig
TDO
20 pF
GND
Z0
= 50Ω
TAP TIMINg
1
2
3
4
5
6
tTHTH
tTLTH
TCK
TMS
tTHTL
t
t
MVTH THMX
t
DVTH
tTHDX
TDI
tTLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BgA BOUNDARY SCAN ORDER (256K ꢀ 36)
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal Bump
Bit # Name
ID
Bit # Name
ID
Bit # Name
ID
Bit # Name
ID
2K
1L
1ꢀ
2ꢀ
Aꢀ
Aꢀ
2Rꢀ
3Tꢀ
4Tꢀ
5Tꢀ
6Rꢀ
3Bꢀ
5Bꢀ
6Pꢀ
7Nꢀ
6Mꢀ
7Lꢀ
6Kꢀ
7Pꢀ
6Nꢀ
6Lꢀ
7Kꢀ
7Tꢀ
6Hꢀ
19ꢀ
20ꢀ
21ꢀ
22ꢀ
23ꢀ
24ꢀ
25ꢀ
26ꢀ
27ꢀ
28ꢀ
29ꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
Aꢀ
7Gꢀ
6Fꢀ
7Eꢀ
7Dꢀ
7Hꢀ
6Gꢀ
6Eꢀ
6Dꢀ
6Aꢀ
5Aꢀ
4Gꢀ
37ꢀ
38ꢀ
39ꢀ
40ꢀ
41ꢀ
42ꢀ
43ꢀ
44ꢀ
45ꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
52ꢀ
53ꢀ
54ꢀ
BWaꢀ
BWbꢀ
BWcꢀ
BWdꢀ
CE2ꢀ
CEꢀ
5Lꢀ
5Gꢀ
3Gꢀ
3Lꢀ
2Bꢀ
4Eꢀ
3Aꢀ
2Aꢀ
2Dꢀ
1Eꢀ
2Fꢀ
1Gꢀ
2Hꢀ
1Dꢀ
2Eꢀ
2Gꢀ
1H
55ꢀ
56ꢀ
57ꢀ
58ꢀ
59ꢀ
60ꢀ
61ꢀ
62ꢀ
63ꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
3ꢀ
Aꢀ
2M
1N
1P
1K
2L
4ꢀ
Aꢀ
5ꢀ
Aꢀ
6ꢀ
Aꢀ
7ꢀ
Aꢀ
Aꢀ
8ꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
ZZꢀ
Aꢀ
2N
2P
9ꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
NCꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
ꢀ14ꢀ
ꢀ15ꢀ
ꢀ16ꢀ
ꢀ17ꢀ
ꢀ18ꢀ
Aꢀ
64ꢀ MODEꢀ 3R
ADVꢀ
65ꢀ
66ꢀ
67ꢀ
68ꢀ
69ꢀ
70ꢀ
Aꢀ
Aꢀ
2C
3C
5C
6C
4N
4P
30ꢀ ADSPꢀ 4Aꢀ
31ꢀ ADSCꢀ 4Bꢀ
Aꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
OEꢀ
4Fꢀ
Aꢀ
BWEꢀ 4Mꢀ
A1ꢀ
A0ꢀ
GWꢀ
CLKꢀ
Aꢀ
4Hꢀ
4Kꢀ
6Bꢀ
DQbꢀ
5R
119 BgA BOUNDARY SCAN ORDER (512K ꢀ 18)
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal Bump
Bit # Name
ID
Bit # Name
ID
Bit # Name
ID
Bit # Name
ID
2K
1L
1ꢀ
2ꢀ
Aꢀ
Aꢀ
2Rꢀ
2Tꢀ
3Tꢀ
5Tꢀ
6Rꢀ
3Bꢀ
5Bꢀ
7Pꢀ
6Nꢀ
6Lꢀ
7Kꢀ
7Tꢀ
6Hꢀ
14ꢀ
15ꢀ
16ꢀ
17ꢀ
18ꢀ
19ꢀ
20ꢀ
21ꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
Aꢀ
7Gꢀ
6Fꢀ
7Eꢀ
6Dꢀ
6Tꢀ
6Aꢀ
5Aꢀ
4Gꢀ
27ꢀ
28ꢀ
29ꢀ
30ꢀ
31ꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
37ꢀ
38ꢀ
39ꢀ
CLKꢀ
Aꢀ
4Kꢀ
6Bꢀ
5Lꢀ
3Gꢀ
2Bꢀ
4Eꢀ
3Aꢀ
2Aꢀ
1Dꢀ
2Eꢀ
2Gꢀ
1Hꢀ
5R
40ꢀ
41ꢀ
42ꢀ
43ꢀ
44ꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
3ꢀ
Aꢀ
BWaꢀ
BWbꢀ
CE2ꢀ
CEꢀ
2M
1N
2P
4ꢀ
Aꢀ
5ꢀ
Aꢀ
6ꢀ
Aꢀ
Aꢀ
45ꢀ MODEꢀ 3R
7ꢀ
Aꢀ
Aꢀ
Aꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
Aꢀ
Aꢀ
2C
3C
5C
6C
4N
4P
8ꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
ZZꢀ
DQaꢀ
ADVꢀ
Aꢀ
9ꢀ
22ꢀ ADSPꢀ 4Aꢀ
23ꢀ ADSCꢀ 4Bꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NCꢀ
Aꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
Aꢀ
24ꢀ
25ꢀ
26ꢀ
OEꢀ
BWEꢀ 4Mꢀ
GWꢀ 4Hꢀ
4Fꢀ
A1ꢀ
A0ꢀ
27
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BgA BOUNDARY SCAN ORDER (x 36)
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal
Name
Bump
ID
Siꢁnal Bump
Bit # Name
ID
Bit # Name
ID
Bit #
41ꢀ
42ꢀ
43ꢀ
44ꢀ
45ꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
52ꢀ
53ꢀ
54ꢀ
55ꢀ
56ꢀ
57ꢀ
58ꢀ
59ꢀ
60ꢀ
Bit #
61ꢀ
62ꢀ
63ꢀ
64ꢀ
65ꢀ
66ꢀ
67ꢀ
68ꢀ
69ꢀ
70ꢀ
71ꢀ
72ꢀ
73ꢀ
74ꢀ
75ꢀ
Name
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
DQdꢀ
Aꢀ
ID
1ꢀ
2ꢀ
MODEꢀ 1Rꢀ
21ꢀ
22ꢀ
23ꢀ
24ꢀ
25ꢀ
26ꢀ
27ꢀ
28ꢀ
29ꢀ
30ꢀ
31ꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
37ꢀ
38ꢀ
39ꢀ
40ꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NCꢀ
11Gꢀ
11Fꢀ
11Eꢀ
11Dꢀ
10Gꢀ
10Fꢀ
10Eꢀ
10Dꢀ
11Cꢀ
11Aꢀ
10Aꢀ
10Bꢀ
9Aꢀ
NCꢀ
CE2ꢀ
BWaꢀ
BWbꢀ
BWcꢀ
BWdꢀ
CE2ꢀ
CEꢀ
1Aꢀ
6Aꢀ
5Bꢀ
5Aꢀ
4Aꢀ
4Bꢀ
3Bꢀ
3Aꢀ
2Aꢀ
2Bꢀ
1Bꢀ
1Cꢀ
1Dꢀ
1Eꢀ
1Fꢀ
1Gꢀ
2D
1J
NCꢀ
Aꢀ
6Nꢀ
11Pꢀ
8Pꢀ
1K
1L
1M
2J
3ꢀ
4ꢀ
Aꢀ
5ꢀ
Aꢀ
8Rꢀ
6ꢀ
Aꢀ
9Rꢀ
2K
2L
2M
1N
3P
3R
4R
4P
6P
6R
7ꢀ
Aꢀ
9Pꢀ
8ꢀ
Aꢀ
10Pꢀ
10Rꢀ
11Rꢀ
11Hꢀ
9ꢀ
Aꢀ
Aꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
ꢀ14ꢀ
ꢀ15ꢀ
ꢀ16ꢀ
ꢀ17ꢀ
ꢀ18ꢀ
ꢀ19ꢀ
ꢀ20ꢀ
Aꢀ
Aꢀ
ZZꢀ
Aꢀ
NCꢀ
Aꢀ
DQaꢀ 11Nꢀ
DQaꢀ 11Mꢀ
DQaꢀ 11Lꢀ
DQaꢀ 11Kꢀ
DQaꢀ 11Jꢀ
DQaꢀ 10Mꢀ
DQaꢀ 10Lꢀ
DQaꢀ 10Kꢀ
DQaꢀ 10Jꢀ
Aꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
DQcꢀ
Aꢀ
ADVꢀ
ADSPꢀ
ADSCꢀ
OEꢀ
Aꢀ
9Bꢀ
A1ꢀ
8Aꢀ
A0ꢀ
8Bꢀ
BWEꢀ
GWꢀ
CLKꢀ
NCꢀ
7Aꢀ
7Bꢀ
2E
6Bꢀ
2F
11Bꢀ
2G
28
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BgA BOUNDARY SCAN ORDER (x 18)
Siꢁnal Bump
Siꢁnal Bump
Siꢁnal
Name
Bump
ID
Siꢁnal Bump
Bit # Name
ID
Bit # Name
ID
Bit #
41ꢀ
42ꢀ
43ꢀ
44ꢀ
45ꢀ
46ꢀ
47ꢀ
48ꢀ
49ꢀ
50ꢀ
51ꢀ
52ꢀ
53ꢀ
54ꢀ
55ꢀ
56ꢀ
57ꢀ
58ꢀ
59ꢀ
60ꢀ
Bit #
61ꢀ
62ꢀ
63ꢀ
64ꢀ
65ꢀ
66ꢀ
67ꢀ
68ꢀ
69ꢀ
70ꢀ
71ꢀ
72ꢀ
73ꢀ
74ꢀ
75ꢀ
Name
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
Aꢀ
ID
1ꢀ
2ꢀ
MODEꢀ 1Rꢀ
21ꢀ
22ꢀ
23ꢀ
24ꢀ
25ꢀ
26ꢀ
27ꢀ
28ꢀ
29ꢀ
30ꢀ
31ꢀ
32ꢀ
33ꢀ
34ꢀ
35ꢀ
36ꢀ
37ꢀ
38ꢀ
39ꢀ
40ꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
DQaꢀ
NCꢀ
11Gꢀ
11Fꢀ
11Eꢀ
11Dꢀ
11Cꢀ
10Fꢀ
10Eꢀ
10Dꢀ
10Gꢀ
11Aꢀ
10Aꢀ
10Bꢀ
9Aꢀ
NCꢀ
CE2ꢀ
BWaꢀ
NCꢀ
1Aꢀ
6Aꢀ
5Bꢀ
5Aꢀ
4Aꢀ
4Bꢀ
3Bꢀ
3Aꢀ
2Aꢀ
2Bꢀ
1Bꢀ
1Cꢀ
1Dꢀ
1Eꢀ
1Fꢀ
1Gꢀ
2D
1J
NCꢀ
Aꢀ
6Nꢀ
11Pꢀ
8Pꢀ
1K
1L
1M
1N
2K
2L
2M
2J
3ꢀ
4ꢀ
Aꢀ
5ꢀ
Aꢀ
8Rꢀ
BWbꢀ
NCꢀ
6ꢀ
Aꢀ
9Rꢀ
7ꢀ
Aꢀ
9Pꢀ
NCꢀ
CE2ꢀ
CEꢀ
8ꢀ
Aꢀ
10Pꢀ
10Rꢀ
11Rꢀ
11Hꢀ
11Nꢀ
11Mꢀ
11Lꢀ
11Kꢀ
11Jꢀ
NCꢀ
9ꢀ
Aꢀ
NCꢀ
Aꢀ
ꢀ10ꢀ
ꢀ11ꢀ
ꢀ12ꢀ
ꢀ13ꢀ
ꢀ14ꢀ
ꢀ15ꢀ
ꢀ16ꢀ
ꢀ17ꢀ
ꢀ18ꢀ
ꢀ19ꢀ
ꢀ20ꢀ
Aꢀ
Aꢀ
Aꢀ
3P
3R
4R
4P
6P
6R
ZZꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
NCꢀ
Aꢀ
NCꢀ
Aꢀ
Aꢀ
NCꢀ
Aꢀ
ADVꢀ
ADSPꢀ
ADSCꢀ
OEꢀ
NCꢀ
Aꢀ
9Bꢀ
NCꢀ
A1ꢀ
8Aꢀ
NCꢀ
A0ꢀ
8Bꢀ
NCꢀ
DQaꢀ 10Mꢀ
DQaꢀ 10Lꢀ
DQaꢀ 10Kꢀ
DQaꢀ 10Jꢀ
BWEꢀ
GWꢀ
CLKꢀ
NCꢀ
7Aꢀ
DQbꢀ
DQbꢀ
DQbꢀ
DQbꢀ
7Bꢀ
2E
6Bꢀ
2F
11Bꢀ
2G
Integrated Silicon Solution, Inc.ꢀ
29
Rev. N
05/25/25
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
ORDERINg INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Ranꢁe: 0°C to +70°C
Confiꢁuration
256Kx36
Frequency
Order Part Number
Packaꢁe(1)
250
IS61LPS25636A-250TQ
IS61LPS25636A-250B2
IS61LPS25636A-250B3
IS61LPS25636A-200TQ
IS61LPS25636A-200B2
IS61LPS25636A-200B3
IS61LPS25636A-166TQ
IS61LPS25636A-166TQL
100ꢀQFP,ꢀ3CE
119ꢀBGA
165ꢀBGA
200
166
250
200
100ꢀQFP,ꢀ3CE
119ꢀBGA
165ꢀBGA
100ꢀQFP,ꢀ3CE
100ꢀQFP,ꢀ3CE,ꢀLead-free
512Kx18
IS61LPS51218A-250TQ
IS61LPS51218A-250B2
IS61LPS51218A-250B3
IS61LPS51218A-200TQ
IS61LPS51218A-200B2
IS61LPS51218A-200B3
100ꢀQFP,ꢀ3CE
119ꢀBGA
165ꢀBGA
100ꢀQFP,ꢀ3CE
119ꢀBGA
165ꢀBGA
30
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Industrial Ranꢁe: -40°C to +85°C
Confiꢁuration
256Kx32
Frequency
OrderPartNumber
Packaꢁe(1)
200
IS61LPS25632A-200TQLI
100ꢀQFP,3CE,Lead-free
256Kx36
250
IS61LPS25636A-250TQI
IS61LPS25636A-250TQLI
IS61LPS25636A-250B2I
IS61LPS25636A-250B3I
IS61LPS25636A-200TQI
IS61LPS25636A-200TQ2LI
IS61LPS25636A-200TQ2I
IS61LPS25636A-200TQLI
IS61LPS25636A-200B2I
IS61LPS25636A-200B2LI
IS61LPS25636A-200B3I
IS61LPS25636A-200B3LI
100ꢀQFP,3CE
100ꢀQFP,3CE,Lead-free
119ꢀBGA
165ꢀBGA
200
100ꢀQFP,3CE
100ꢀQFP,2CE,Lead-free
100ꢀQFP,2CE
100ꢀQFP,3CE,Lead-free
119ꢀBGA
119ꢀBGA,Lead-free
165ꢀBGA
166
250
165ꢀBGA,Lead-free
512Kx18
IS61LPS51218A-250TQI
IS61LPS51218A-250B2I
IS61LPS51218A-250B3I
IS61LPS51218A-200TQI
IS61LPS51218A-200TQ2LI
IS61LPS51218A-200TQ2I
IS61LPS51218A-200TQLI
IS61LPS51218A-200B2I
IS61LPS51218A-200B3I
100ꢀQFP,3CE
119ꢀBGA
165ꢀBGA
200
100ꢀQFP,3CE
100ꢀQFP,2CE,Lead-free
100ꢀQFP,2CE
100ꢀQFP,3CE,Lead-free
119ꢀBGA
165ꢀBGA
Note:
1. Forꢀ100ꢀQFP,ꢀ2CEꢀoptionꢀcontactꢀSRAMꢀMarketingꢀatꢀsram@issi.com
Automotive Ranꢁe: -40°C to +125°C
Confiꢁuration
Frequency
Order Part Number
Packaꢁe
256Kx36
166ꢀ
IS64LPS25636A-166TQLA3ꢀ
100ꢀQFP,ꢀ3CEꢀ
Integrated Silicon Solution, Inc.ꢀ
31
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
ORDERINg INFORMATION (2.5V core/2.5V I/O)
Commercial Ranꢁe: 0°C to +70°C
Confiꢁuration
Frequency
Order Part Number
Packaꢁe(1)
256Kx36
250ꢀ
IS61VPS25636A-250TQꢀ
IS61VPS25636A-250B2ꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS25636A-250B3ꢀ
165ꢀBGA
200ꢀ
IS61VPS25636A-200TQꢀ
IS61VPS25636A-200B2ꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS25636A-200B3ꢀ
165ꢀBGA
512Kx18
250ꢀ
200ꢀ
IS61VPS51218A-250TQꢀ
IS61VPS51218A-250B2ꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS51218A-250B3ꢀ
165ꢀBGA
IS61VPS51218A-200TQꢀ
IS61VPS51218A-200B2ꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS51218A-200B3ꢀ
165ꢀBGA
Industrial Ranꢁe: -40°C to +85°C
Confiꢁuration
Frequency
Order Part Number
Packaꢁe(1)
256Kx36
250ꢀ
IS61VPS25636A-250TQIꢀ
IS61VPS25636A-250B2Iꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS25636A-250B3Iꢀ
165ꢀBGA
200ꢀ
IS61VPS25636A-200TQIꢀ
IS61VPS25636A-200TQ2Iꢀ
IS61VPS25636A-200TQLIꢀ
IS61VPS25636A-200B2Iꢀ
100ꢀQFP,ꢀ3CEꢀ
100ꢀQFP,ꢀ2CEꢀ
100ꢀQFP,ꢀ3CE,ꢀLead-free
119ꢀBGA
ꢀ
ꢀ
IS61VPS25636A-200B3Iꢀ
165ꢀBGA
512Kx18
250ꢀ
200ꢀ
IS61VPS51218A-250TQIꢀ
IS61VPS51218A-250B2Iꢀ
100ꢀQFP,ꢀ3CE
119ꢀBGA
IS61VPS51218A-250B3Iꢀ
165ꢀBGA
IS61VPS51218A-200TQIꢀ
IS61VPS51218A-200TQ2Iꢀ
IS61VPS51218A-200B2Iꢀ
100ꢀQFP,ꢀ3CEꢀ
100ꢀQFP,ꢀ2CE
119ꢀBGA
IS61VPS51218A-200B3Iꢀ
165ꢀBGA
Note:
1. Forꢀ100ꢀQFP,ꢀ2CEꢀoptionꢀcontactꢀSRAMꢀMarketingꢀatꢀsram@issi.com
32
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Integrated Silicon Solution, Inc.ꢀ
33
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
34
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Integrated Silicon Solution, Inc.ꢀ
35
Rev. N
05/25/2015
相关型号：
IS61LPS25636A-200TQI
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-200TQLI
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250B2
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250B2I
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250B3
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250B3I
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250TQ
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636A-250TQI
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
ISSI
IS61LPS25636B-200TQLI
Cache SRAM, 256KX36, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LQFP-100
ISSI
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