IS61LPS25636D-166TQI [ISSI]
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | IS61LPS25636D-166TQI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LPS25632T/D
IS61LPS25636T/D
IS61LPS51218T/D
®
ISSI
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINED,
DECEMBER 2003
SINGLE-CYCLE DESELECT STATIC RAM
DESCRIPTION
FEATURES
The ISSI IS61LPS25632T/D, IS61LPS25636T/D, and
IS61LPS51218T/Darehigh-speed,low-powersynchronous
staticRAMsdesignedtoprovideburstable,high-performance
memory for communication and networking applications.
The IS61LPS25632T/D is organized as 262,144 words by
32bitsandtheIS61LPS25636T/Disorganizedas262,144
words by 36 bits. The IS61LPS51218T/D is organized as
524,288wordsby18bits.FabricatedwithISSI'sadvanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputspassthroughregisterscontrolledbyapositive-edge-
triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE
input
•
Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power Supply
Writecyclesareinternallyself-timedandareinitiatedbythe
risingedgeoftheclockinput.Writecyclescanbeonetofour
bytes wide as controlled by the write control inputs.
+3.3V VDD
+3.3V or 2.5 VDDQ (I/O)
Separate byte enables allow individual bytes to be written.
Bytewriteoperationisperformedbyusingbytewriteenable
(BWE). Input combined with one or more individual byte
write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T Version (three chips selects)
• D Version (two chips selects)
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-200
3.1
5
-166
3.5
6
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
200
166
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
BLOCK DIAGRAM
MODE
A0'
Q0
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
A1'
ADV
A1
256Kx32; 256Kx36;
512Kx18
ADSC
ADSP
CLR
MEMORY ARRAY
18/19
16/17
18/19
D
Q
A
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQd
BYTE WRITE
REGISTERS
BWd
(x32/x36)
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BWc
(x32/x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BWb
(x32/x36/x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
CE (T,D)
CE2 (T,D)
CE2 (T)
4
32, 36,
or 18
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa - DQd
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
PIN CONFIGURATION
100-Pin TQFP (D Version)
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
V
DDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
V
DDQ
GND
DQc
DQc
DQc
DQc
GND
GND
DQb
DQb
DQb
DQb
GND
GND
DQb
DQb
DQb
DQb
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
DDQ
DQc
DQc
NC
VDDQ
V
DDQ
DQc
DQc
NC
DQb
DQb
GND
NC
DQb
DQb
GND
NC
V
DD
V
DD
V
DD
NC
GND
DQd
DQd
VDD
NC
GND
DQd
DQd
ZZ
DQa
DQa
ZZ
DQa
DQa
V
DDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
V
DDQ
GND
DQd
DQd
DQd
DQd
GND
GND
DQa
DQa
DQa
DQa
GND
GND
DQa
DQa
DQa
DQa
GND
V
DDQ
V
DDQ
DQd
DQd
NC
VDDQ
V
DDQ
DQd
DQd
NC
DQa
DQa
NC
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
PIN CONFIGURATION
100-Pin TQFP (T Version)
100-Pin TQFP (D Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
DQPb
DQb
DQb
DQPc
DQc
DQc
DQPc
DQc
DQc
V
DDQ
VDDQ
V
DDQ
VDDQ
GND
DQb
DQb
DQb
DQb
GND
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
GND
DQc
DQc
DQc
DQc
GND
GND
DQc
DQc
DQc
DQc
GND
V
DDQ
V
DDQ
VDDQ
DQb
DQb
GND
NC
DQc
DQc
NC
DQc
DQc
NC
V
DD
NC
VDD
V
DD
NC
ZZ
DQa
DQa
GND
DQd
DQd
GND
DQd
DQd
V
DDQ
VDDQ
V
DDQ
VDDQ
GND
DQa
DQa
DQa
DQa
GND
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
DQd
DQd
DQd
DQd
GND
GND
DQd
DQd
DQd
DQd
GND
V
DDQ
V
DDQ
VDDQ
DQa
DQa
DQPa
DQd
DQd
DQPd
DQd
DQd
DQPd
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
PIN CONFIGURATION
100-Pin TQFP (D Version)
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
GND
NC
DQPa
DQa
DQa
GND
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
NC
NC
DDQ
DDQ
V
VDDQ
V
GND
NC
NC
DQb
DQb
GND
GND
NC
DQPa
DQa
DQa
GND
GND
NC
NC
DQb
DQb
GND
V
DDQ
V
DDQ
VDDQ
VDDQ
DQa
DQa
GND
NC
V
ZZ
DQa
DQa
V
GND
DQa
DQa
NC
NC
GND
VDDQ
NC
NC
NC
DQb
DQb
DQa
DQa
GND
NC
DQb
DQb
V
V
DD
VDD
DD
V
DD
DD
NC
GND
DQb
DQb
VDD
NC
GND
DQb
DQb
ZZ
DQa
DQa
DDQ
VDDQ
VDDQ
VDDQ
GND
DQa
DQa
NC
NC
GND
GND
DQb
DQb
DQPb
NC
GND
DQb
DQb
DQPb
NC
GND
GND
VDDQ
V
DDQ
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BWa-BWd
BWE
DQPa-DQPd
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
High-Z
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.
WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc
and DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte
write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for
clarification.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
OPERATING RANGE
Range
AmbientTemperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
Industrial
-40°Cto+85°C
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
ExternalAddress
A1 A0
1stBurstAddress
A1 A0
2ndBurstAddress
A1 A0
3rdBurstAddress
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
7
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–55 to +150
1.6
Unit
°C
W
TSTG
PD
StorageTemperature
PowerDissipation
IOUT
OutputCurrent(perI/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
VIN
Voltage Relative to GND for
for Address and Control Inputs
V
VDD
Voltage on VDD Supply Relative to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
DCELECTRICALCHARACTERISTICS(OverOperatingRange)
2.5V (I/O)
3.3V (I/O)
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
1.7
–0.3
–5
VDD + 0.3
2.0
–0.3
–5
VDD + 0.3
V
V
0.7
5
0.8
5
(1)
Input Leakage Current
Output Leakage Current
GND ≤ VIN ≤ VDD
µA
µA
ILO
GND ≤ VOUT ≤ VDDQ, OE = VI
–5
5
–5
5
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200
-166
Max
x18
Max
x36
Max
x18 x36/x32
Max
Symbol
Parameter
Test Conditions
Unit
ICC
AC Operating
Supply Current
Device Selected,
Com.
Ind.
125 130
135 140
120
130
125
135
mA
mA
mA
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ VIL or ≥ VIH,
Cycle Time ≥ tKC min.
ISB
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
55
60
55
60
50
55
50
55
ISBI
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
30
40
30
40
30
40
30
40
VIN
≤ GND + 0.2V or ≥ VDD – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to VDD or GND. It exhibits ±30 µA maximum leakage current when tied to
≤ GND + 0.2V or ≥ VDD – 0.2V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
1,538 Ω
1.25V
Figure 4
Figure 3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
Read/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Min.
-200
Min.
Symbol Parameter
Max.
166
—
Max.
200
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMAX
tKC
tKH
tKL
Clock Frequency
—
6
—
5
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
2.3
2.3
—
—
2
—
—
2
—
tKQ
3.5
—
—
3.1
—
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
1.5
0
1.0
0
(1,2)
(1,2)
tKQLZ
—
—
tKQHZ
tOEQ
—
3.5
3.5
—
—
3.0
3.1
—
—
—
(1,2)
tOELZ
tOEHZ
tAS
0
0
(1,2)
—
3.5
—
—
3.0
—
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
tSS
Address Status Setup Time
Write Setup Time
—
—
tWS
—
—
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
—
—
—
—
—
—
tSH
Address Status Hold Time
Write Hold Time
—
—
tWH
tCEH
tAVH
—
—
Chip Enable Hold Time
Address Advance Hold Time
—
—
—
—
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 1,2,3,4.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
BWx
WH
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
Pipelined Read
DATAIN
Burst Read
Single Read
Unselected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
13
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-200
Symbol
tKC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle Time
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tKH
Clock High Pulse Width
Clock Low Pulse Width
Address Setup Time
Address Status Setup Time
Write Setup Time
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
tKL
2
tAS
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
tSS
tWS
tDS
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
tCES
tAVS
tAH
tSH
Address Status Hold Time
Data In Hold Time
tDH
tWH
tCEH
tAVH
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
15
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
ISB2
CurrentduringSNOOZEMODE
ZZ ≥ Vih, Com.
ZZ ≥ Vih, Ind.
—
—
30
40
mA
tPUS
tZZI
ZZ inactive to input sampled
2
—
0
—
2
cycle
cycle
ns
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
tRZZI
—
SNOOZE MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
IS61LPS25632T/D,IS61LPS25636T/D,IS61LPS51218T/D
ISSI
ORDERING INFORMATION: IS61LPS25632
(T Version)
Industrial Range: -40°C to +85°C
(T Version)
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166Mhz
IS61LPS25632T-166TQI
TQFP
166Mhz
IS61LPS25632T-166TQ
TQFP
(D Version)
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
166Mhz
IS61LPS25632D-166TQ
TQFP
ORDERING INFORMATION: IS61LPS25636
(T Version)
(T Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
Package
Speed
166Mhz
200Mhz
OrderPartNumber
Package
TQFP
166Mhz
IS61LPS25636T-166TQ
TQFP
IS61LPS25636T-166TQI
IS61LPS25636T-200TQI
TQFP
(D Version)
(D Version)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166Mhz
IS61LPS25636D-166TQ
TQFP
166Mhz
IS61LPS25636D-166TQI
TQFP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
17
12/04/03
®
IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D
ISSI
ORDERING INFORMATION: IS61LPS51218
(T Version)
Industrial Range: -40°C to +85°C
(T Version)
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
Speed
OrderPartNumber
Package
166Mhz
IS61LPS51218T-166TQI
TQFP
166Mhz
IS61LPS51218T-166TQ
TQFP
(D Version)
Commercial Range: 0°C to +70°C
Speed
OrderPartNumber
Package
166Mhz
IS61LPS51218D-166TQ
TQFP
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
12/04/03
®
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
Inches Millimeters
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
Millimeters
Min Max
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
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