IS61LV256-15T-TR [ISSI]
Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, TSOP1-28;
| 型号： | IS61LV256-15T-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, TSOP1-28 |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV256
32K x 8 LOW VOLTAGE CMOS STATIC RAM
ISSI
FEBRUARY 1996
FEATURES
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 12 ns maximum.
• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 345 mW (max.) operating
— 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using an active LOW
ChipEnable(CE).TheactiveLOWWriteEnable(WE)controls
both writing and reading of the memory.
• Three-state outputs
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil DIP and SOJ, plus the 450-mil TSOP package.
FUNCTIONAL BLOCK DIAGRAM
256 X 1024
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
2-1
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
PIN CONFIGURATION
28-Pin DIP and SOJ
PIN CONFIGURATION
28-Pin TSOP
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A5
5
A9
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A4
6
A11
OE
A3
7
A2
8
A10
CE
2
A1
9
3
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
4
I/O0
I/O1
I/O2
GND
5
6
A1
A2
7
8
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE
X
CE
H
OE I/O Operation Vcc Current
A0-A14
CE
Address Inputs
Not Selected
(Power-down)
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
I/O0-I/O7
Vcc
Write
X
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2-2
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.3V +10%, –5%
3.3V ± 5%
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
0.4
V
2.2
VCC + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
–2
–5
2
5
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
50
—
—
—
50
60
—
—
50
60
—
—
50
60
mA
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
100
—
—
—
90
100
—
—
80
90
—
—
70
80
mA
mA
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
10
—
—
—
10
20
—
—
10
20
—
—
10
20
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
2
—
—
—
2
5
—
—
2
5
—
—
2
5
mA
CE ≤ VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
6
5
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
2-3
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-12 ns
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Symbol Parameter
Max.
—
12
—
12
6
Max.
—
15
—
15
7
Max.
—
20
—
20
8
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
12
—
2
15
—
2
20
—
2
25
—
2
—
tAA
Address Access Time
Output Hold Time
CE Access Time
25
—
tOHA
tACE
tDOE
tLZOE
—
—
0
—
—
0
—
—
0
—
—
0
25
9
OE Access Time
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
—
7
—
8
—
9
—
tHZOE
—
3
—
3
—
3
—
3
10
—
(2)
tLZCE
tHZCE
—
5
—
6
—
9
(2)
—
0
—
0
—
0
—
0
10
—
(3)
tPU
—
13
—
15
—
18
(3)
tPD
CE to Power-Down
—
—
—
—
20
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
635 Ω
635 Ω
3.3V
3.3V
OUTPUT
OUTPUT
702 Ω
702 Ω
30 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1a.
Figure 1b.
2-4
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE
t
ACE
t
LZCE
t
HZCE
HIGH-Z
DOUT
DATA VALID
t
PU
t
PD
ICC
ISB
50%
50%
SUPPLY
CURRENT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc.
2-5
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-12 ns
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
7
Max.
—
—
—
—
—
—
—
—
8
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCE
tAW
tHA
Write Cycle Time
12
8
15
10
10
0
20
13
15
0
25
15
20
0
—
CE to Write End
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
8
—
0
—
tSA
0
0
0
0
—
(4)
tPWE
tSD
WE Pulse Width
8
10
8
13
10
0
15
12
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6
—
tHD
0
0
—
(2)
tHZWE
—
0
—
0
—
0
—
0
10
—
(2)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE
t
HA
t
SCE
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
DIN
2-6
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
WRITE CYCLE NO. 2 (CE Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE
CE
t
AW
t
PWE
WE
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
SD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
12
12
12
IS61LV256-12N
IS61LV256-12T
IS61LV256-12J
300-mil Plastic DIP
TSOP - 450 mil
300-mil Plastic SOJ
12
12
12
IS61LV256-12NI
IS61LV256-12TI
IS61LV256-12JI
300-mil Plastic DIP
TSOP - 450 mil
300-mil Plastic SOJ
15
15
15
IS61LV256-15N
IS61LV256-15T
IS61LV256-15J
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
15
15
15
IS61LV256-15NI
IS61LV256-15TI
IS61LV256-15JI
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
20
20
20
IS61LV256-20N
IS61LV256-20T
IS61LV256-20J
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
20
20
20
IS61LV256-20NI
IS61LV256-20TI
IS61LV256-20JI
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
25
25
25
IS61LV256-25N
IS61LV256-25T
IS61LV256-25J
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
25
25
25
IS61LV256-25NI
IS61LV256-25TI
IS61LV256-25JI
300-mil Plastic DIP
450-mil TSOP
300-mil Plastic SOJ
Integrated Silicon Solution, Inc.
2-7
Rev. F 0296
SR81995LV61
®
IS61LV256
ISSI
®
ISSI
Integrated Silicon Solution, Inc.
680 Almanor Avenue
Sunnyvale, CA 94086
Fax: (408) 245-4774
Toll Free: 1-800-379-4774
http://www.issiusa.com
2-8
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
相关型号：
IS61LV256-15TL
Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.450 INCH, LEAD FREE, PLASTIC, TSOP1-28
ISSI
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