IS61LV25616L [ISSI]
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY; 256K ×16高速异步静态CMOS与3.3V供电的RAM
| 型号： | IS61LV25616L |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总11页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV25616L
ISSI
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
JUNE 2002
DESCRIPTION
FEATURES
The ISSI IS61LV25616L is a high-speed, 4,194,304-bit
static RAM organized as 262,144 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative
circuitdesigntechniques,yieldshigh-performanceandlow
power consumption devices.
• High-speed access time:
— 10, 12, and 15 ns
• Low Active Power
— Less than 90mA (typ.) Active Current
• Low standby power:
— Less than 1 mA (typ.) CMOS standby
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory.A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
The IS61LV25616L is packaged in the JEDEC standard
44-pin400-milSOJ,44-pinTSOPTypeII,44-pinLQFPand
48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
06/28/02
®
IS61LV25616L
ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
44-Pin LQFP
A0
A1
A2
A3
A4
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
2
3
4
5
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
CE
6
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
2
8
3
9
4
10
11
12
13
14
15
16
17
18
19
20
21
22
5
TOP VIEW
6
7
8
9
10
11
I/O8
NC
12 13 14 15 16 17 18 19 20 21 22
A6
A7
A8
A9
48-Pin mini BGA
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
1
2
3
4
5
6
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
A0
A3
A1
A4
A2
LB
OE
UB
N/C
A
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
I/O
CE
I/O
0
B
C
D
E
F
8
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
UB
GND
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
Vcc
11
3
4
5
NC
GND
Vcc
A16
A15
A13
A10
12
Vcc
Power
I/O
14
I/O
I/O
6
13
GND
Ground
I/O
15
NC
A8
WE
I/O
7
G
H
NC
A9
A11
NC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
®
IS61LV25616L
ISSI
TRUTHTABLE
I/O PIN
I/O0-I/O7
1
Mode
I/O8-I/O15
Vcc Current
ISB1, ISB2
ICC
Not Selected
Output Disabled
X
H
X
X
X
High-Z
High-Z
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
2
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
3
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
4
5
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
6
VTERM
TBIAS
VCC
Terminal Voltage with Respect to GND –0.5 to Vcc+0.5
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
–45 to +90
–0.3 to +4.0
–65 to +150
1.0
°C
V
7
TSTG
PT
°C
W
Note:
8
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
10
11
12
OPERATING RANGE
10 ns
VCC
12 ns, 15 ns
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial
3.3V +10%, -5%
3.3V +10%, -5%
3.3V ± 10%
3.3V ± 10%
–40°C to +85°C
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
06/28/02
®
IS61LV25616L
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.0
VCC + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, 4
Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10
Min. Max.
-12
Min. Max.
-15
Symbol Parameter
TestConditions
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
125
135
—
—
115
125
—
—
105
115
mA
ISB
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
65
70
—
—
55
60
—
—
45
50
mA
mA
mA
ISB1
ISB2
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
15
20
—
—
15
20
—
—
15
20
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
5
10
—
—
5
10
—
—
5
10
CE ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shadedareaproductindevelopment
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
®
IS61LV25616L
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
10
—
3
—
10
—
10
4
12
—
3
—
12
—
12
5
15
—
3
—
15
—
15
7
AA
OHA
ACE
DOE
HZOE
2
—
—
—
0
—
—
—
0
—
—
0
OE Access Time
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
Power Up Time
4
5
6
3
(2)
LZOE
—
4
—
6
0
—
8
(2
HZCE
0
0
0
(2)
LZCE
BA
3
—
4
3
—
5
3
—
7
4
—
0
—
0
—
0
(2)
HZB
3
4
5
(2)
LZB
PU
0
—
—
10
0
—
—
12
0
—
—
15
5
0
0
0
PD
Power Down Time
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
6
Shadedareaproductindevelopment
7
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
8
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
9
AC TEST LOADS
10
11
12
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
5 pF
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
06/28/02
®
IS61LV25616L
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
tOHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
RC
t
LZB
HIGH-Z
DOUT
DATA VALID
I
CC
SB
V
CC
Supply
Current
50%
50%
t
PD
t
PU
I
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
®
IS61LV25616L
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
1
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Symbol
Parameter
Unit
tWC
tSCE
t
AW
Write Cycle Time
CE to Write End
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
ns
ns
ns
2
Address Setup Time
to Write End
8
8
3
t
t
t
t
t
t
t
t
t
HA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
5
0
0
—
—
—
—
—
—
—
6
0
0
—
—
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
SA
PWB
PWE
PWE
SD
LB, UB Valid to End of Write
WE Pulse Width
8
8
10
10
12
7
4
1
2
8
8
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
6
12
6
5
HD
0
0
0
(2)
HZWE
—
2
—
2
—
2
(2)
LZWE
—
—
—
6
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
7
Shadedareaproductindevelopment
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
7
06/28/02
®
IS61LV25616L
ISSI
AC WAVEFORMS
(1 )
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
®
IS61LV25616L
ISSI
AC WAVEFORMS
(1,2)
WRITE CYCLE NO. 2(WE Controlled. OE is HIGH During Write Cycle)
1
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
2
LOW
CE
3
t
AW
t
PWE1
WE
t
SA
4
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
5
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
UB_CEWR2.eps
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
7
t
WC
ADDRESS
VALID ADDRESS
8
t
HA
LOW
LOW
OE
CE
9
t
t
AW
t
PWE2
10
11
12
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
06/28/02
®
IS61LV25616L
ISSI
AC WAVEFORMS
(1,3)
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/28/02
®
IS61LV25616L
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
1
Speed
(ns)
Order Part No.
Package
Speed
(ns)
Order Part No.
Package
2
10
12
15
IS61LV25616L-10T
IS61LV25616L-10K 400-mil SOJ
IS61LV25616L-10LQ LQFP
TSOP (Type II)
10
12
15
IS61LV25616L-10TI TSOP (Type II)
IS61LV25616L-10KI 400-mil SOJ
IS61LV25616L-10LQI LQFP
IS61LV25616L-10B Mini BGA (8mm x 10mm)
IS61LV25616L-10BI Mini BGA (8mm x 10mm)
3
IS61LV25616L-12T
IS61LV25616L-12K 400-mil SOJ
IS61LV25616L-12LQ LQFP
TSOP (Type II)
IS61LV25616L-12TI TSOP (Type II)
IS61LV25616L-12KI 400-mil SOJ
IS61LV25616L-12LQI LQFP
IS61LV25616L-12B Mini BGA (8mm x 10mm)
IS61LV25616L-12BI Mini BGA (8mm x 10mm)
4
IS61LV25616L-15T
IS61LV25616L-15K 400-mil SOJ
TSOP (Type II)
IS61LV25616L-15TI TSOP (Type II)
IS61LV25616L-15KI 400-mil SOJ
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11
06/28/02
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