IS61LV2568-15T [ISSI]
256K x 8 HIGH-SPEED CMOS STATIC RAM; 256K ×8高速CMOS静态RAM
| 型号： | IS61LV2568-15T |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISSI®
DECEMBER 2000
IS61LV2568
256K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS61LV2568 is a very high-speed, low power,
262,144-wordby8-bitCMOSstaticRAM.TheIS61LV2568
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
• High-speed access times:
8, 10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
• CE power-down
The IS61LV2568 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
• Low power: 540 mW @ 10 ns
36 mW standby mode
The IS61LV2568 is available in 36-pin 400-mil SOJ, and
44-pin TSOP (Type II) packages.
• TTL compatible inputs and outputs
• Single 3.3V 10ꢀ power supply
• Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
FUNCTIONAL BLOCK DIAGRAM
256K X 8
MEMORY ARRAY
A0-A17
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
1
ISSI®
IS61LV2568
PIN CONFIGURATION
36-Pin SOJ
44-Pin TSOP (Type II)
A4
A3
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A5
A6
A7
2
A5
A2
3
A6
A1
4
A7
A0
5
A8
A8
CE
6
OE
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
7
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
11
12
13
14
15
16
17
18
A10
A11
A12
NC
NC
NC
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE
CE OE I/O Operation Vcc Current
A0-A17
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
OE
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
Read
Write
H
L
I/O0-I/O7
Vcc
X
GND
NC
Ground
No Connection
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +4.6
Unit
V
VCC
Supply voltage with Respect to GND
Terminal Voltage with Respect to GND
VTERM
TBIAS
–0.5 to Vcc + 0.5
V
Temperature Under Bias
Com.
Ind.
–10 to +85
–45 to +90
°C
TSTG
PD
Storage Temperature
Power Dissipation
–65 to +150
1.0
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
IS61LV2568
ISSI®
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.3V 10ꢀ
3.3V 10ꢀ
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test
Conditions
Min.Max.Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
—
—
V
V
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
Input Leakage
0.4
VCC + 0.3
0.8
2.0
–0.3
V
V
GND - VIN - VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Note:
1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
VIH(max) = VCC + 0.3V (DC); VIH(max) = Vcc + 2.0V (pulse width - 2.0 ns).
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
Min.Max.
-12 ns
-15 ns
Symbol
Parameter
Test Conditions
Min.Max.
Min.Max.
Min.Max. Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
150
160
—
—
125
—
—
110
120
—
—
90
mA
135
100
ISB1
ISB2
TTL Standby
Current
VCC
=
=
Max.,Com.
60
—
50
50
—
—
40
45
—
35
40
—
—
30
10
VIN = VIH or VIL
CE • VIH, f = max
Ind.
—
—
—
(TTL Inputs)
CMOS Standby
Current
VCC
Max.,Com.
0.2V,Ind.
—
10
—
—
10
—
10
CE - VCC
–
—
20
20
—
20
—
20
(CMOS Inputs)
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.Unit
Input Capacitance
Input/Output Capacitance
6
8
pF
pF
CI/O
VOUT = 0V
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
3
ISSI®
IS61LV2568
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
- 8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
MinM. ax
MinM.ax.Min.Max. Min.Max.
Unit
—
12
—
12
5
tRC
Read Cycle Time
8
—
3
—
8
10
—
3
—
10
—
10
4
12
—
3
15
—
15
—
15
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
CE Access Time
—
3
tOHA
tACE
tDOE
tLZOE
—
8
—
—
0
—
—
0
—
—
0
—
—
0
OE Access Time
3
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
—
3
—
4
—
5
—
6
tHZOE
0
0
0
0
(2)
tLZCE
tHZCE
3
—
3
3
—
4
3
—
5
3
—
6
(2)
0
0
0
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100ꢀ tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
IS61LV2568
ISSI®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
5
ISSI®
IS61LV2568
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
- 8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
MinM. ax
MinM.ax.Min.Max. Min.Max.
Unit
—
tWC
tSCE
tAW
Write Cycle Time
8
—
—
—
10
8
—
—
—
12
9
15
—
—
—
ns
ns
ns
CE to Write End
6.5
6.5
—
10
10
Address Setup Time to
Write End
8
9
—
tHA
Address Hold from
Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
5
—
—
—
—
—
3
0
7
—
—
—
—
—
4
0
8
—
—
—
—
—
5
0
10
11
7
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6.5
4
8
10
6
5
tHD
0
0
0
0
(3)
tHZWE
—
0
—
0
—
0
—
0
(3)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
IS61LV2568
ISSI®
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
7
ISSI®
IS61LV2568
ORDERING INFORMATION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed
(ns) Order
Part
No.Package
Speed
(ns) Order
Part
No.Package
8
IS61LV2568-8K
IS61LV2568-8T
400-mil Plastic SOJ
TSOP (Type II)
8
IS61LV2568-8KI
IS61LV2568-8TI
400-mil Plastic SOJ
TSOP (Type II)
10
12
15
IS61LV2568-10K
IS61LV2568-10T
400-mil Plastic SOJ
TSOP (Type II)
10
12
15
IS61LV2568-10KI 400-mil Plastic SOJ
IS61LV2568-10TI TSOP (Type II)
IS61LV2568-12K
IS61LV2568-12T
400-mil Plastic SOJ
TSOP (Type II)
IS61LV2568-12KI 400-mil Plastic SOJ
IS61LV2568-12TI TSOP (Type II)
IS61LV2568-15K
IS61LV2568-15T
400-mil Plastic SOJ
TSOP (Type II)
IS61LV2568-15KI 400-mil Plastic SOJ
IS61LV2568-15TI TSOP (Type II)
ISSI®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.A
12/19/00
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