IS61LV2568L_08 [ISSI]
256K x 8 HIGH-SPEED CMOS STATIC RAM; 256K ×8高速CMOS静态RAM
| 型号： | IS61LV2568L_08 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总14页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV2568L
APRIL2008
256K x 8 HIGH-SPEED CMOS STATIC RAM
DESCRIPTION
FEATURES
The ISSI IS61LV2568L is a very high-speed, low power,
262,144-wordby8-bitCMOSstaticRAM.TheIS61LV2568L
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
• High-speed access time: 8, 10 ns
• Operating Current: 50mA (typ.)
• Standby Current: 700µA (typ.)
• Multiple center power and ground pins for
greater noise immunity
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
• Easy memory expansion with CE and OE
options
• CE power-down
The IS61LV2568L operates from a single 3.3V power
supply and all inputs are TTL-compatible.
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
The IS61LV2568L is available in 36-pin 400-mil SOJ and
44-pin TSOP (Type II) packages.
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
256K X 8
MEMORY ARRAY
A0-A17
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. D
04/28/08
IS61LV2568L
PIN CONFIGURATION
36-Pin SOJ
44-Pin TSOP (Type II)
A4
A3
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A5
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A5
A6
A7
2
A2
3
A6
A1
4
A7
A0
5
A8
CE
I/O0
I/O1
6
OE
I/O7
I/O6
GND
A8
OE
I/O7
I/O6
GND
7
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
9
V
DD
GND
I/O2
I/O3
WE
10
11
12
13
14
15
16
17
18
VDD
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
VDD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
I/O5
I/O4
A9
A17
A16
A15
A14
A13
A10
A11
A12
NC
NC
NC
PIN DESCRIPTIONS
A0-A17
CE
Address Inputs
Chip Enable Input
OE
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
WE
I/O0-I/O7
VDD
GND
NC
Ground
NoConnection
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08
IS61LV2568L
TRUTH TABLE
Mode
WE
CE
OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD
Parameter
Value
Unit
V
V
°C
W
Supply voltage with Respect to GND
Terminal Voltage with Respect to GND
StorageTemperature
–0.5 to +4.0
–0.5 to VDD + 0.5
–65 to +150
1.0
VTERM
TSTG
PD
PowerDissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD (8ns)
3.3V +10%,-5%
VDD (10 ns)
3.3V + 10%
3.3V + 10%
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
InputLeakage
0.4
V
2.0
–0.3
–1
VDD + 0.3
V
0.8
1
V
GND ≤ VIN
GND
≤
VDD
µA
µA
ILO
OutputLeakage
≤
VOUT
≤
VDD, Outputs Disabled
–1
1
Note:
1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
VIH(max) = VDD + 0.3V (DC); VIH(max) = VDD + 2.0V (pulse width - 2.0 ns).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. D
04/28/08
IS61LV2568L
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
65
—
—
—
60
65
50
mA
typ.(2)
—
—
50
30
ISB1
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = max
Com.
Ind.
—
—
25
30
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
3
—
—
—
3
4
700
mA
mA
μA
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
typ.(2)
700
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08
IS61LV2568L
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Levels
OutputLoad
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. D
04/28/08
IS61LV2568L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
- 8 ns
-10 ns
Min.
Symbol Parameter
Min.
Max
—
Max.
—
10
—
10
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
—
2.5
—
—
0
10
—
2.5
—
—
0
tAA
Address Access Time
Output Hold Time
CE Access Time
8
tOHA
tACE
tDOE
tLZOE
—
8
OE Access Time
3.5
—
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
—
4
tHZOE
0
3.5
—
0
(2)
tLZCE
tHZCE
3.5
0
3
—
4
(2)
3.5
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08
IS61LV2568L
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
CE
t
HZOE
t
DOE
t
t
LZOE
ACE
t
HZCE
t
LZCE
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. D
04/28/08
IS61LV2568L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
- 8 ns
-10 ns
Symbol
tWC
Parameter
Min. Max
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
8
7
—
—
—
—
—
—
—
—
—
3
10
8
—
—
—
—
—
—
—
—
—
4
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
7
8
tHA
0
0
tSA
0
0
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6
7
6.5
4
8
5
tHD
0
0
(3)
tHZWE
—
0
—
0
(3)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08
IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a
Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or
falling edge of the signal that terminates the Write.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. D
04/28/08
IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08
IS61LV2568L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
8
IS61LV2568L-8K
IS61LV2568L-8T
IS61LV2568L-8TL
400-mil SOJ
TSOP (Type II)
TSOP (Type II), Lead-free
10
IS61LV2568L-10T
IS61LV2568L-10TL
TSOP (Type II)
TSOP (Type II), Lead-free
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
10
IS61LV2568L-10KI
IS61LV2568L-10KLI
400-mil SOJ
400-milSOJ,Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. D
04/28/08
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
N
N/2+1
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
E1
E
1
N/2
SEATING PLANE
D
A
b
C
A2
e
B
A1
E2
Millimeters
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
No. Leads (N)
28
32
36
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
18.29 18.54
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.720 0.730
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Millimeters
Symbol Min Max
No. Leads (N)
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Min Max
Inches
Min Max
Min
Max
40
42
44
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
25.91 26.16
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.020 1.030
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
PlasticTSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
相关型号：
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