IS61LV6416-10TLI-TR [ISSI]
IC SRAM 1M PARALLEL 44TSOP II;
| 型号： | IS61LV6416-10TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 1M PARALLEL 44TSOP II 静态存储器 |
| 文件： | 总16页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV6416
IS61LV6416L
ISSI
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
NOVEMBER2005
FEATURES
DESCRIPTION
The ISSI IS61LV6416/IS61LV6416L is a high-speed,
1,048,576-bitstaticRAMorganizedas65,536wordsby16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
• High-speed access time: 8, 10, 12 ns
• CMOS low power operation
— 61LV6416:
75 mW (typical) operating current
0.5 mW (typical) standby current
— 61LV6416L:
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
65 mW (typical) operating current
50 µW (typical) standby current
• TTL compatible interface levels
• Single 3.3V power supply
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.
• Fully static operation: no clock or refresh
required
• Three state outputs
TheIS61LV6416/IS61LV6416LispackagedintheJEDEC
standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin
mini BGA (6mm x 8mm).
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
64K x 16
MEMORY ARRAY
A0-A15
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc.
1
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
PIN CONFIGURATIONS
44-Pin SOJ (K)
44-Pin TSOP-II (T)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
A15
A14
A13
A12
A11
CE
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
2
A1
3
A2
4
OE
5
UB
6
LB
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
A3
A4
A8
A5
A8
A7
NC
A7
A6
NC
NC
NC
PIN DESCRIPTIONS
48-Pin mini BGA (6mm x 8mm) (B)
A0-A15
I/O0-I/O15
CE
Address Inputs
1
2
3
4
5
6
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
A0
A3
A1
A4
A2
LB
OE
UB
NC
I/O
A
B
C
D
E
F
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NoConnection
I/O
CE
8
0
UB
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
NC
GND
NC
NC
A14
A12
A7
I/O
I/O
I/O
I/O
I/O
VDD
11
3
4
5
GND
VDD
Power
VDD
NC
A15
A13
A10
12
I/O
I/O
I/O
I/O
6
14
GND
Ground
13
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
2
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
1
Not Selected
OutputDisabled
X
H
X
H
L
L
X
H
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ICC
2
Read
Write
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
L
H
L
L
H
L
H
L
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
DIN
High-Z
DIN
High-Z
DIN
DIN
3
4
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
TSTG
PT
Terminal Voltage with Respect to GND
StorageTemperature
PowerDissipation
–0.5 to VDD+0.5
–65 to +150
V
°C
W
5
1.5
20
IOUT
DCOutputCurrent(LOW)
mA
Note:
6
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7
OPERATING RANGE
8
Range
Commercial
Industrial
AmbientTemperature
0°C to +70°C
VDD (8,10ns)
3.3V+10%,-5%
3.3V+10%,-5%
VDD (12ns)
3.3V 10%
3.3V 10%
–40°Cto+85°C
9
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
10
11
12
Symbol Parameter
TestConditions
Min.
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
2.4
—
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–2
0.8
2
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–2
2
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc.
3
Rev. I
11/22/05
®
IS61LV6416
IS61LV6416L
ISSI
IS61LV6416
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
VDD Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
—
140
150
105
—
—
—
120
130
95
—
—
—
100
110
75
mA
Supply Current
IOUT = 0 mA, f = fMAX
typ.(2)
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
—
—
15
20
—
—
15
20
—
—
15
20
mA
mA
ISB2
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VDD = Max.,
Com.
Ind.
—
—
—
5
10
0.5
—
—
—
5
10
0.5
—
—
—
5
10
0.5
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
typ.(2)
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
IS61LV6416L
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
—
100
110
75
—
—
—
95
105
70
mA
Supply Current
IOUT = 0 mA, f = fMAX
typ.(2)
ISB1
ISB2
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
—
—
15
20
—
—
15
20
mA
mA
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VDD = Max.,
Com.
Ind.
—
—
—
1
1.5
0.05
—
—
—
1
1.5
0.05
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
typ.(2)
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
1
Input and Output Timing
and Reference Level
1.5V
2
Output Load
See Figures 1a and 1b
AC TEST LOADS
3
319 Ω
319 Ω
3.3V
3.3V
4
OUTPUT
OUTPUT
353 Ω
353 Ω
5 pF
30 pF
Including
jig and
5
Including
jig and
scope
scope
6
Figure 1a.
Figure 1b.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
7
-8 ns
-10 ns
-12 ns
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
Read Cycle Time
8
—
3
—
8
10
—
3
—
10
—
10
5
12
—
3
—
12
—
12
6
tAA
Address Access Time
Output Hold Time
tOHA
—
8
9
tACE
CE Access Time
—
—
—
0
—
—
—
0
—
—
—
0
tDOE
OE Access Time
5
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
5
5
6
10
11
12
(2)
tLZOE
—
4
—
5
—
6
(2
tHZCE
0
0
0
(2)
tLZCE
3
—
6
3
—
6
3
—
6
tBA
—
0
—
0
—
0
tHZB
4
5
6
tLZB
0
—
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not100%tested.
Integrated Silicon Solution, Inc.
5
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
tAA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
D
OUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
1
Write Cycle Time
CE to Write End
8
6
8
—
—
—
10
8
—
—
—
12
9
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
8
9
ns
2
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
4
0
0
—
—
—
—
—
—
5
0
0
—
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
tSA
3
tPBW
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH/LOW)
Data Setup to Write End
7
8
9
tPWE1/tPWE2
6
8
9
tSD
tHD
6
6
6
4
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
0
0
(2)
tHZWE
—
3
—
3
—
3
(2)
tLZWE
—
—
—
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc.
7
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
8
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
1
t
HA
OE
2
LOW
CE
t
AW
3
t
PWE1
WE
t
SA
t
PBW
4
UB, LB
t
HZWE
t
LZWE
HIGH-Z
5
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
6
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
7
t
WC
ADDRESS
VALID ADDRESS
8
t
HA
LOW
LOW
OE
CE
9
t
t
AW
t
PWE2
10
11
12
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
Integrated Silicon Solution, Inc.
9
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write)(1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
IS61LV6416
ISSI
IS61LV6416L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
3.6
1
IDR
IS61LV6416
—
—
0.5
10
mA
IS61LV6416L
0.05
1.5
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
0
—
—
—
—
ns
ns
2
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.0V, T
A
= 25 C and not 100% tested.
3
4
DATA RETENTION WAVEFORM (CE Controlled)
5
tSDR
Data Retention Mode
tRDR
6
VDD
VDR
7
CE ≥ VDD - 0.2V
CE
GND
8
9
10
11
12
Integrated Silicon Solution, Inc.
11
Rev. I
11/22/05
®
IS61LV6416
IS61LV6416L
ISSI
IS61LV6416
ORDERING INFORMATION
Speed(ns)
Order Part No.
Package
TemperatureRange
8
8
8
8
8
IS61LV6416-8T
IS61LV6416-8TL
IS61LV6416-8BI
IS61LV6416-8TI
IS61LV6416-8KL
Plastic TSOP
Plastic TSOP
Commercial (0°C to +70°C )
Commercial(0°Cto+70°C), Lead-free
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C )
Commercial (0°C to +70°C ), Lead-free
mini BGA (6mm x 8mm)
Plastic TSOP
400-mil Plastic SOJ
10
10
10
10
10
10
10
10
10
IS61LV6416-10T
IS61LV6416-10TL
IS61LV6416-10K
IS61LV6416-10BI
IS61LV6416-10BLI
IS61LV6416-10TI
IS61LV6416-10TLI
IS61LV6416-10KI
IS61LV6416-10KLI
Plastic TSOP
Plastic TSOP
Commercial (0°C to +70°C )
Commercial(0°Cto+70°C), Lead-free
Commercial (0°C to +70°C )
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C ), Lead-free
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C ), Lead-free
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C ), Lead-free
400-mil Plastic SOJ
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm)
Plastic TSOP
Plastic TSOP
400-mil Plastic SOJ
400-mil Plastic SOJ
12
12
12
12
IS61LV6416-12T
IS61LV6416-12K
IS61LV6416-12KL
IS61LV6416-12BI
Plastic TSOP
Commercial (0°C to +70°C )
Commercial (0°C to +70°C )
Commercial (0°C to +70°C ), Lead-free
Industrial (-40°C to +85°C )
400-mil Plastic SOJ
400-mil Plastic SOJ
mini BGA (6mm x 8mm)
IS61LV6416L
ORDERING INFORMATION
Speed(ns)
Order Part No.
Package
TemperatureRange
8
8
8
8
IS61LV6416L-8T
IS61LV6416L-8BI
IS61LV6416L-8TI
IS61LV6416L-8KI
Plastic TSOP
mini BGA (6mm x 8mm)
Plastic TSOP
Commercial (0°C to +70°C )
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C )
400-mil Plastic SOJ
10
10
10
10
IS61LV6416L-10T
IS61LV6416L-10BI
IS61LV6416L-10TI
IS61LV6416L-10KI
Plastic TSOP
mini BGA (6mm x 8mm)
Plastic TSOP
Commercial (0°C to +70°C )
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C )
Industrial (-40°C to +85°C )
400-mil Plastic SOJ
12
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
®
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
ISSI
Notes:
1. Controlling dimension:
millimeters.
N
N/2+1
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
E1
E
1
N/2
SEATING PLANE
D
A
b
C
A2
e
B
A1
E2
Millimeters
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
No. Leads (N)
28
32
36
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
18.29 18.54
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.720 0.730
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGING INFORMATION
ISSI
Millimeters
Symbol Min Max
No. Leads (N)
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Min Max
Inches
Min Max
Min
Max
40
42
44
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
25.91 26.16
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.020 1.030
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
7.90
0.009
0.024
0.311
A1
A2
D
0.24
0.60
9.90
0.009
0.024
0.390
8.10
0.319
10.10
0.398
D1
E
5.25 BSC
—
0.207 BSC
D1
E
5.25 BSC
—
0.207 BSC
5.90
6.10
0.232
—
0.240
7.90
8.10
0.311
—
0.319
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
0.030 BSC
0.030 BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
相关型号：
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