IS61NF12832-10TQI [ISSI]
128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM; 128K ×32 ， 128K ×36和256K ×18的流通无等待状态SRAM总线
| 型号： | IS61NF12832-10TQI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM |
| 文件： | 总20页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61NF12832 IS61NF12836 IS61NF25618
IS61NLF12832 IS61NLF12836 IS61NLF25618 ISSI
128K x 32, 128K x 36 and 256K x 18
FLOW-THROUGH 'NO WAIT' STATE BUS
NOVEMBER 2002
SRAM
FEATURES
DESCRIPTION
The 4 Meg 'NF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining for TQFP
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119 PBGA package
• Single +3.3V power supply (± 5%)
• NF Version: 3.3V I/O Supply Voltage
• NLF Version: 2.5V I/O Supply Voltage
• Industrialtemperatureavailable
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-8.5
8.5
10
-9
9
-10
10
12
83
Units
ns
Clock Access Time
Cycle Time
tKC
12
83
ns
Frequency
100
MHz
ISSIreservestherighttomakechangesthisspecificationhereinanditproductsatanytimewithoutnotice. ISSIassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,
productorservicesdescribedherein.Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
©Copyright2000,IntegratedSiliconSolution,Inc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
1
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
BLOCK DIAGRAM
A2-A16 or A2-A17
A [0:16] or
ADDRESS
128Kx32; 125Kx36;
256Kx18
MEMORY ARRAY
A [0:17]
REGISTER
MODE
BURST
ADDRESS
COUNTER
A0-A1
A'0-A'1
K
DATA-IN
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CONTROL
LOGIC
K
CKE
CE
CE2
CE2
CONTROL
REGISTER
ADV
WE
CONTROL
LOGIC
}
BW
Ÿ
(X=a,b,c,d or a,b)
BUFFER
OE
ZZ
32, 36 or 18
DQa0-DQd7 or DQa0-DQb8
DQPa-DQPd
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
A
B
C
D
E
F
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND
VCC
VCC
VCCQ
NC
A6
CE2
A7
A4
A3
NC
ADV
VCC
NC
A8
A16
CE2
VCCQ
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
GND
VCC
A9
NC
A2
A12
GND
GND
GND
BWb
GND
NC
A15
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
GND
GND
GND
BWc
GND
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
CE
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
NC
WE
VCC
CLK
NC
ZZ
GND
K
L
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
GND
BWd
GND
GND
GND
MODE
A10
GND
BWa
GND
GND
GND
NC
M
N
P
R
T
CKE
A1
A0
A5
VCC
A11
NC
A13
NC
NC
A14
NC
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VCCQ
NC
NC
NC
VCCQ
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
A2
-
A16
Synchronous Address Inputs
Synchronous Clock
CLK
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
GND
VCCQ
ZZ
Ground
BWa-BWd
WE
IsolatedOutputBufferSupply:+3.3V/2.5V
Snooze Enable
CKE
Clock Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
3
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
A6
A4
A3
NC
ADV
VCC
NC
A8
A16
CE2
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
GND
VCC
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND
VCC
VCC
CE2
A9
NC
A7
A2
A12
GND
GND
GND
BWb
GND
NC
A15
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
GND
GND
GND
BWc
GND
NC
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
CE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
NC
WE
VCC
CLK
NC
ZZ
GND
K
L
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
GND
BWd
GND
GND
GND
MODE
A10
GND
BWa
GND
GND
GND
NC
M
N
P
R
T
CKE
A1
A0
VCC
A11
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A14
NC
NC
ZZ
U
VCCQ
NC
NC
NC
VCCQ
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
A2-A16
Synchronous Address Inputs
Synchronous Clock
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
CLK
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
BWa-BWd
WE
GND
VCCQ
ZZ
Ground
solatedOutputBufferSupply:+3.3V/2.5V
Snooze Enable
DQPa-DQPd Parity Data I/O
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
A6
CE2
A7
A4
A3
NC
ADV
VCC
NC
A8
A16
CE2
A15
DQP1
NC
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VCCQ
GND
NC
A10
NC
NC
VCCQ
GND
NC
A9
NC
A2
A12
GND
GND
GND
NC
NC
DQ9
NC
NC
GND
GND
GND
BWb
GND
NC
NC
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
GND
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
GND
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
DQ10
NC
CE
DQ8
VCCQ
DQ6
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCCQ
NC
OE
DQ7
NC
G
H
J
DQ11
NC
NC
DQ12
VCCQ
NC
WE
VCC
CLK
NC
GND
NC
DQ5
VCC
NC
VCC
DQ13
NC
VCCQ
DQ4
NC
K
L
GND
NC
GND
BWa
GND
GND
GND
NC
DQ14
VCCQ
DQ16
NC
DQ3
NC
M
N
P
R
T
DQ15
NC
GND
GND
GND
MODE
A11
CKE
A1
VCCQ
NC
DQ2
NC
NC
GND
VCCQ
NC
NC
NC
GND
VCCQ
NC
NC
NC
DQP2
A5
A0
DQ1
NC
NC
VCC
NC
A13
A17
NC
NC
A10
NC
A14
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VCCQ
NC
NC
VCCQ
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
A2
-
A17
Synchronous Address Inputs
Synchronous Clock
CLK
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
GND
VCCQ
ZZ
Ground
BWa-BWb
WE
IsolatedOutputBufferSupply:+3.3V/2.5V
Snooze Enable
CKE
Clock Enable
DQP1-DQP2 Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
5
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
STATE DIAGRAM
READ
WRITE
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
WRITE
BURST
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
BURST
BURST
WRITE
READ
SYNCHRONOUSTRUTHTABLE(1)
Address
Operation
Used
CS1 CS2 CS2 ADV
WE
BWx
OE
CKE CLK
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
N/A
X
L
X
H
X
H
X
H
X
H
X
X
X
L
H
L
X
H
X
H
X
L
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
H
X
Next Address
Current Address
X
X
X
X
H
X
X
X
Ignore Clock
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
ASYNCHRONOUS TRUTH TABLE(1)
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
L
L
L
H
DQ
High-Z
Read
Write
L
L
X
X
Din, High-Z
High-Z
Deselected
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
L
L
L
L
X
L
X
H
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
H
L
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x32/x36)
Operation
WE
BWa
BWb
BWc
BWd
READ
H
L
L
L
L
L
L
X
L
X
H
L
X
H
H
L
X
H
H
H
L
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
H
H
H
L
H
H
L
H
L
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
7
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–65 to +150
1.6
Unit
°C
W
TSTG
PD
StorageTemperature
PowerDissipation
IOUT
OutputCurrent(perI/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.3
–0.3 to 4.6
VIN
Voltage Relative to GND for
for Address and Control Inputs
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for extended periods
mayaffectreliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
OPERATING RANGE
Range
AmbientTemperature
VCC
VCCQ
Commercial
0°C to +70°C
3.3V ± 5%
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
Industrial
-40°Cto+85°C
3.3V ± 5%
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V
3.3V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
1.7
–0.3
–5
VCC + 0.3
2.0
–0.3
–5
VCC + 0.3
V
V
0.7
5
0.8
5
(1)
Input Leakage Current
Output Leakage Current
GND ≤ VIN ≤ VCC
µA
µA
ILO
GND ≤ VOUT ≤ VCCQ, OE = VI
–5
5
–5
5
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8.5
-9
-10
MAX
MAX
MAX
Symbol Parameter
Test Conditions
x18
x32/36
x18
x32/36
x18
x32/36
Unit
ICC
ISB
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
Cycle Time ≥ tKC min.
Com.
IND.
305
—
305
—
290
305
290
305
275
290
275
290
mA
mA
mA
Standby Current
TTL Input
Device Deselected,
VCC = Max.,
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
ZZ ≤ VIL, f = Max.
COM.
Ind.
90
—
90
—
80
90
80
90
70
80
70
80
ISBI
Standby Current
CMOS Input
Device Deselected,
VCC = Max.,
Com.
Ind.
10
—
10
—
10
15
10
15
10
15
10
15
VIN
≤ GND + 0.2V or ≥ VCC – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits ±30 µA maximum leakage current when
tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
9
11/11/02
IS61NF12832
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IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
IS61NF12832
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IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11
11/11/02
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ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8.5
-9
-10
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fmax
tKC
ClockFrequency
—
10
3
100
—
—
—
8.5
—
—
5
—
12
3
83
—
—
—
9
—
12
3
83
—
—
—
10
—
—
6
Cycle Time
tKH
Clock High Time
tKL
Clock Low Time
3
3
3
tKQ
Clock Access Time
—
3
—
3
—
3
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
5
(2,3)
(2,3)
tKQLZ
2.5
—
—
0
2.5
—
—
0
2.5
—
—
0
tKQHZ
tOEQ
3.5
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
3.5
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
3.5
—
4
(2,3)
tOELZ
tOEHZ
tAS
(2,3)
—
2
—
2
—
2
—
—
—
—
—
—
—
—
—
—
—
—
tWS
Read/WriteSetupTime
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
2
2
2
tCES
tSE
2
2
2
2
2
2
tAVS
tDS
2
2
2
2
2
2
tAH
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
tHE
ClockEnableHoldTime
Write Hold Time
tWH
tCEH
tADVH
tDH
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
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ISSI
SLEEPMODEELECTRICALCHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
Max.
Unit
mA
Current during SLEEP MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
ZZ ≥ Vih
10
tPDS
2
2
2
0
cycle
cycle
cycle
ns
tPUS
tZZI
tRZZI
SLEEP MODE TIMING
K
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
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ISSI
READ CYCLE TIMING
t
KH
tKL
Clock
ADV
tKC
tADVS tADVH
tAS tAH
A16 - A0 or
A17 - A0
A1
A3
A2
tWS
tWH
WE
tSE tHE
CKE
CE
tCES
tCEH
OE
t
DS
KQ
tOEQ
tOEHZ
t
tKQHZ
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
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ISSI
WRITE CYCLE TIMING
tKH
tKL
Clock
ADV
tKC
A16 - A0 or
A17 - A0
A1
A2
A3
WE
tSE
tHE
CKE
CE
OE
tDS
tDH
Data In
Data Out
D1-1
OEHZ
D2-1
D2-2
D2-3
D2-4
D3-1
D3-2
D3-3
D3-4
t
Q0-4
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
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ISSI
SINGLE READ/WRITE CYCLE TIMING
t
KH
tKL
Clock
t
SE tHE
t
KC
CKE
Address
WRITE
CS
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
t
OEQ
t
OELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS = L, CS = H and CS
CS = H means CS = H, or CS = L and CS
Don't Care
Undefined
1
2
2
= L
= H, or CS
1
1
2
1
= L and CS
2
= L
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
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ISSI
CKE OPERATION TIMING
t
KH
tKL
Clock
t
SE tHE
t
KC
CKE
Address
WRITE
CS
A1
A2
A3
A4
A5
A6
ADV
OE
t
KQ
t
KQHZ
t
KQLZ
Data Out
Data In
Q1
Q3
Q4
t
DS
t
DH
D2
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS = L, CS = H and CS
CS = H means CS = H, or CS
Don't Care
Undefined
1
2
2
= L
1
1
= L and CS
2
= H, or CS
1
= L and CS2 = L
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
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ISSI
CS OPERATION TIMING
t
KH
tKL
Clock
t
SE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CS
ADV
OE
t
OEQ
t
KQHZ
tKQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS = L, CS = H and CS
CS = H means CS = H, or CS = L and CS
Don't Care
Undefined
1
2
2
= L
= H, or CS
1
1
2
1
= L and CS
2
= L
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/11/02
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®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
ORDERING INFORMATION (6INFxxxxx)
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Frequency
128Kx32
8.5
OrderPartNumber
Package
Frequency Order Part Number
128Kx32
Package
IS61NF12832-8.5TQ
IS61NF12832-8.5B
TQFP
PBGA
10
IS61NF12832-10TQI
IS61NF12832-10BI
TQFP
PBGA
10
IS61NF12832-10TQ
IS61NF12832-10B
TQFP
PBGA
128Kx36
10
IS61NF12836-10TQI
IS61NF12836-10BI
TQFP
PBGA
128Kx36
8.5
IS61NF12836-8.5TQ
IS61NF12836-8.5B
TQFP
PBGA
256Kx18
10
IS61NF25618-10TQI
IS61NF25618-10BI
TQFP
PBGA
10
256Kx18
8.5
IS61NF12836-10TQ
TQFP
IS61NF25618-8.5TQ
IS61NF25618-8.5B
TQFP
PBGA
10
IS61NF25618-10TQ
TQFP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
19
11/11/02
IS61NF12832
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®
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
ORDERING INFORMATION
(IS61NLFxxxxx)
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Frequency Order Part Number
128Kx32
Package
Frequency
128Kx32
8.5
OrderPartNumber
Package
10
128Kx36
10
IS61NLF12832-10TQI
TQFP
IS61NLF12832-8.5TQ
IS61NLF12832-8.5B
TQFP
PBGA
IS61NLF12836-10TQI
IS61NLF12836-10BI
TQFP
PBGA
128Kx36
8.5
IS61NLF12836-8.5TQ
IS61NLF12836-8.5B
TQFP
PBGA
256Kx18
10
IS61NLF25618-10TQI
IS61NLF25618-10BI
TQFP
PBGA
10
256Kx18
8.5
IS61NLF12836-10TQ
TQFP
IS61NLF25618-8.5TQ
IS61NLF25618-8.5B
TQFP
PBGA
10
IS61NLF25618-10TQ
IS61NLF25618-10B
TQFP
PBGA
®
ISSI
IntegratedSiliconSolution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
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Rev. A
11/11/02
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