IS61NLP102436A-166TQ [ISSI]
1Mb x 36 and 2Mb x 18 STATE BUS SRAM; 1MB ×36和2MB ×18态总线SRAM
| 型号： | IS61NLP102436A-166TQ |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 1Mb x 36 and 2Mb x 18 STATE BUS SRAM |
| 文件： | 总22页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
1Mb x 36 and 2Mb x 18
36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER2007
FEATURES
DESCRIPTION
The 36 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organizedas1Mwordsby36bitsand2M wordsby18bits,
fabricated with ISSI's advanced CMOS technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
• JEDEC 100-pin TQFP and 165-ball PBGA
packages
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
• Power supply:
NVP: VDD 2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)
NLP: VDD 3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol
tKQ
Parameter
-200
3.1
5
-166
3.5
6
Units
ns
Clock Access Time
CycleTime
tKC
ns
Frequency
200
166
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc.
1
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
BLOCK DIAGRAM
A2-A19 or A2-A20
1Mx36;
2Mx18
MEMORY ARRAY
x 36: A [0:19] or
x 18: A [0:20]
ADDRESS
REGISTER
MODE
BURST
ADDRESS
COUNTER
K
K
DATA-IN
REGISTER
A0-A1
A'0-A'1
DATA-IN
REGISTER
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CONTROL
LOGIC
K
CKE
CE
CE2
CE2
CONTROL
REGISTER
ADV
WE
K
CONTROL
LOGIC
OUTPUT
REGISTER
}
BW
X
(X=a,b,c,d or a,b)
BUFFER
OE
ZZ
36 or 18
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
PIN CONFIGURATION — 1M X 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
A
A
10
A
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
VSS
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
OE
NC
A
CE2
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
VSS
V
DDQ
DDQ
DDQ
DDQ
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQc
DQc
DQc
DQc
NC
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
DQb
DQb
DQb
DQb
NC
V
V
V
V
V
V
V
V
G
H
J
V
V
V
VDDQ
NC
V
V
NC
DQd
DQd
DQd
DQd
DQPd
NC
DQd
DQd
DQd
DQd
NC
V
DDQ
DDQ
DDQ
DDQ
V
V
V
DDQ
DDQ
DDQ
DDQ
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DQPa
NC
K
L
V
V
V
V
V
V
V
V
M
N
P
R
V
V
V
V
VDDQ
VSS
A
VSS
A
VDDQ
NC
A
NC
A1*
A0*
NC
A
A
MODE
A
A
A
NC
NC
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
(Under Evaluation)
PIN DESCRIPTIONS
MODE
VDD
Burst Sequence Selection
3.3V/2.5V Power Supply
NoConnect
Symbol
A
Pin Name
Address Inputs
NC
A0, A1
ADV
Synchronous Burst Address Inputs
DQx
DataInputs/Outputs
Parity Data I/O
Synchronous Burst Address Advance/
Load
DQPx
VDDQ
WE
Synchronous Read/Write Control
Input
Isolated output Power Supply
3.3V/2.5V
CLK
SynchronousClock
Clock Enable
VSS
Ground
CKE
CE, CE2, CE2 SynchronousChipEnable
BWx(x=a-d)
Synchronous Byte Write Inputs
Output Enable
OE
ZZ
PowerSleepMode
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
165-PIN PBGA PACKAGE CONFIGURATION
2M x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
A
B
C
D
CKE
NC
ADV
A
A
A
A
BWb
NC
A
CE2
CLK
Vss
Vss
CE
NC
CE2
A
OE
WE
NC
Vss
NC
BWa
V
DDQ
NC
Vss
DQPa
NC
V
DDQ
DDQ
DDQ
Vss
Vss
NC
NC
NC
VDD
Vss
V
V
V
DD
DQa
DQa
DQa
DQa
ZZ
NC
Vss
Vss
Vss
Vss
V
DDQ
DDQ
DQb
DQb
VDD
V
V
DD
DD
E
F
NC
Vss
Vss
Vss
Vss
V
DDQ
DDQ
V
DDQ
V
DD
DD
NC
DQb
NC
NC
V
V
Vss
Vss
Vss
Vss
V
G
NC
V
DDQ
DQb
NC
NC
NC
NC
V
DD
V
DD
DD
DD
DD
DD
V
DD
NC
H
J
NC
NC
Vss
Vss
NC
V
DDQ
V
Vss
Vss
Vss
V
DDQ
DDQ
V
DD
DD
DQb
DQb
DQb
DQb
DQPb
NC
DQa
NC
NC
NC
K
L
V
V
DDQ
DDQ
V
V
Vss
Vss
Vss
Vss
DQa
DQa
DQa
NC
A
V
V
Vss
Vss
V
DD
V
DDQ
V
NC
NC
V
DDQ
V
DD
M
N
P
NC
NC
NC
A
Vss
Vss
NC
V
DDQ
Vss
A
NC
V
DDQ
Vss
A
NC
NC
NC
V
DDQ
A
A
NC
A
A1
*
*
NC
NC
A
A
0
A
A
A
A
R
MODE
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
(Under Evaluation)
PIN DESCRIPTIONS
MODE
VDD
Burst Sequence Selection
3.3V/2.5V Power Supply
NoConnect
Symbol
A
Pin Name
Address Inputs
NC
A0, A1
ADV
Synchronous Burst Address Inputs
DQx
DataInputs/Outputs
Parity Data I/O
Synchronous Burst Address Advance/
Load
DQPx
VDDQ
WE
Synchronous Read/Write Control
Input
Isolated output Power Supply
3.3V/2.5V
CLK
SynchronousClock
Clock Enable
VSS
Ground
CKE
CE, CE2, CE2 SynchronousChipEnable
BWx (x=a,b)
Synchronous Byte Write Inputs
Output Enable
OE
ZZ
PowerSleepMode
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
DQPc
DQc
DQc
VDDQ
Vss
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
Vss
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
V
DDQ
VDDQ
Vss
Vss
DQc
DQc
DQb
DQb
NC
NC
NC
DQPa
DQc
DQc
Vss
DQb
DQb
Vss
DQb
DQb
Vss
DQa
DQa
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQc
VDDQ
DQb
V
DDQ
VDDQ
DQb
DQa
DQc
VDD
VDD
DQb
Vss
NC
DQb
VDD
DQa
Vss
NC
V
DD
NC
Vss
VDD
ZZ
NC
Vss
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQd
DQd
VDDQ
DQb
DQb
DQa
DQa
V
DDQ
VDDQ
Vss
DQd
Vss
DQb
Vss
DQa
DQa
DQa
DQa
DQb
DQd
DQPb
NC
DQd
DQd
Vss
DQa
DQa
Vss
NC
NC
Vss
Vss
VDDQ
VDDQ
V
DDQ
VDDQ
NC
NC
NC
NC
NC
NC
DQd
DQd
DQPd
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2M x 18
1M x 36
PIN DESCRIPTIONS
CE, CE2, CE2 SynchronousChipEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
OE
OutputEnable
DQa-DQd
DQPa-DQPd
MODE
VDD
SynchronousDataInput/Output
Parity Data I/O
A
Synchronous Address Inputs
SynchronousClock
CLK
ADV
BWa-BWd
WE
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Synchronous Burst Address Advance
Synchronous Byte Write Enable
WriteEnable
VSS
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
SnoozeEnable
CKE
Vss
Clock Enable
ZZ
GroundforCore
NC
NotConnected
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
STATE DIAGRAM
READ
WRITE
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
BURST
WRITE
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
WRITE
BURST
BURST
READ
SYNCHRONOUSTRUTHTABLE(1)
Address
Operation
Used
CE
CE2
CE2 ADV
WE
BWx
OE
CKE CLK
Not Selected
N/A
N/A
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Not Selected
Not Selected
N/A
X
X
H
X
H
X
H
X
H
X
X
L
NotSelectedContinue
Begin Burst Read
ContinueBurstRead
NOP/DummyRead
DummyRead
N/A
H
L
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write
ContinueBurstWrite
NOP/WriteAbort
WriteAbort
X
L
X
L
H
L
X
L
L
H
H
X
Next Address
CurrentAddress
X
X
X
X
H
X
X
X
IgnoreClock
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
ASYNCHRONOUSTRUTHTABLE(1)
Operation
ZZ
OE
I/O STATUS
SleepMode
H
X
High-Z
L
L
L
H
DQ
High-Z
Read
Write
Deselected
L
L
X
X
Din,High-Z
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
L
L
L
L
X
L
H
L
X
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITEABORT/NOP
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x36)
Operation
WE
BWa
BWb
BWc
BWd
READ
H
L
L
L
L
L
L
X
L
H
H
H
L
X
H
L
H
H
L
X
H
H
L
H
L
X
H
H
H
L
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITEABORT/NOP
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
Parameter
Value
–65 to +150
1.6
Unit
°C
W
StorageTemperature
PowerDissipation
OutputCurrent(perI/O)
PD
IOUT
100
mA
V
VIN, VOUT
VIN
Voltage Relative to VSS for I/O Pins
–0.5 to VDDQ + 0.3
–0.3 to 4.6
Voltage Relative to VSS for
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLPx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
3.3V 5ꢀ
3.3V 5ꢀ
3.3V / 2.5V 5ꢀ
3.3V / 2.5V 5ꢀ
-40°Cto+85°C
OPERATING RANGE (IS61NVPx)
Range
AmbientTemperature
0°C to +70°C
VDD
VDDQ
Commercial
Industrial
2.5V 5ꢀ
2.5V 5ꢀ
2.5V 5ꢀ
2.5V 5ꢀ
-40°Cto+85°C
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
2.4
—
2.0
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
Input HIGH Voltage
Input LOW Voltage
2.0
–0.3
–5
VDD + 0.3
1.7
–0.3
–5
VDD + 0.3
V
V
0.8
5
0.7
5
(1)
Input Leakage Current
Output Leakage Current
VSS ≤ VIN ≤ VDD
ꢁA
ꢁA
ILO
VSS ≤ VOUT ≤ VDDQ, OE = VIH
–5
5
–5
5
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200
-166
MAX
MAX
Symbol Parameter
Test Conditions
Temp.range
x18
x36
x18
x36
Unit
ICC
ISB
ISBI
AC Operating
Supply Current
Device Selected,
OE = VIH, ZZ ≤ VIL,
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
Com.
Ind.
450
475
450
475
400 400
450 450
340
mA
mA
mA
typ.(2)
390
Standby Current
TTL Input
Device Deselected,
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com.
Ind.
260
270
260
270
250 250
260 260
Standby Current
CMOS Input
Device Deselected,
VDD = Max.,
Com.
Ind.
105
110
105
110
105 105
110 110
30
VIN
≤
VSS + 0.2V or ≥VDD – 0.2V
typ.(2)
30
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100ꢁA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100ꢀ tested.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
InputCapacitance
Input/OutputCapacitance
6
8
COUT
Notes:
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
1.5 ns
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 2.5V
1.5 ns
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-200
Min.
-166
Min. Max.
Symbol
fmax
tKC
Parameter
Max.
200
—
—
—
3.1
—
—
3.0
3.1
—
3.0
—
—
—
—
—
—
—
—
—
—
—
—
2
Unit
MHz
ns
ClockFrequency
—
5
—
6
166
—
—
—
3.5
—
—
3.4
3.5
—
3.4
—
—
—
—
—
—
—
—
—
—
—
—
2
Cycle Time
tKH
Clock High Time
2
2.5
2.5
—
ns
tKL
Clock Low Time
2
ns
tKQ
Clock Access Time
—
1.5
1
ns
(2)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/WriteSetupTime
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
1.5
1
ns
(2,3)
tKQLZ
ns
(2,3)
tKQHZ
—
—
0
—
ns
tOEQ
—
ns
(2,3)
tOELZ
0
ns
(2,3)
tOEHZ
—
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
—
—
—
ns
tAS
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
—
ns
tWS
ns
tCES
tSE
ns
ns
tADVS
tDS
ns
ns
tAH
Address Hold Time
ns
tHE
Clock Enable Hold Time
Write Hold Time
ns
tWH
tCEH
tADVH
tDH
ns
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
ns
ns
ns
tPDS
tPUS
ZZ High to Power Down
ZZ Low to Power Down
cyc
cyc
2
—
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100ꢀ tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
SLEEPMODEELECTRICALCHARACTERISTICS
Symbol
ISB2
Parameter
Conditions
Min.
Max.
Unit
mA
CurrentduringSLEEPMODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
ZZ ≥ VIH
75
tPDS
2
2
2
0
cycle
cycle
cycle
ns
tPUS
tZZI
tRZZI
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
ISB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
READ CYCLE TIMING
t
KH
tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
tSE tHE
tCES
t
CEH
CE
OE
KQX tKQ
tOEQ
tOEHZ
t
tKQHZ
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
WRITE CYCLE TIMING
t
KH
t
KL
CLK
tKC
ADV
Address
WRITE
CKE
A1
A2
A3
tSE
tHE
CE
OE
t
DS
t
DH
Data In
Data Out
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
D3-2
D3-3
D3-4
tOEHZ
Q0-3
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
SINGLE READ/WRITE CYCLE TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
tOEQ
tOELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
CKE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
tKQ
tKQHZ
tKQLZ
Data Out
Data In
Q1
Q3
Q4
t
DS
t
DH
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
CE OPERATION TIMING
t
KH
tKL
CLK
tSE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
tOEQ
tKQHZ
t
KQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
1Mx36
AccessTime
OrderPartNumber
Package
166
IS61NLP102436A-166TQ
IS61NLP102436A-166TQL
100 TQFP
100TQFP,Lead-free
IS61NLP102436A-166B3
165 PBGA
2Mx18
166
IS61NLP204818A-166TQ
IS61NLP204818A-166TQL
100 TQFP
100TQFP,Lead-free
IS61NLP204818A-166B3
165 PBGA
Industrial Range: -40°C to +85°C
Configuration
1Mx36
AccessTime
OrderPartNumber
Package
166
IS61NLP102436A-166TQI
IS61NLP102436A-166TQLI
100 TQFP
100TQFP,Lead-free
IS61NLP102436A-166B3I
165 PBGA
2Mx18
166
IS61NLP204818A-166TQI
IS61NLP204818A-166TQLI
100 TQFP
100TQFP,Lead-free
IS61NLP204818A-166B3I
165 PBGA
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. A
09/13/07
IS61NLP102436A/IS61NVP102436A
IS61NLP204818A/IS61NVP204818A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
1Mx36
AccessTime
OrderPartNumber
Package
166
IS61NVP102436A-166TQ
IS61NVP102436A-166TQL
100 TQFP
100TQFP,Lead-free
IS61NVP102436A-166B3
165 PBGA
2Mx18
166
IS61NVP204818A-166TQ
IS61NVP204818A-166TQL
100 TQFP
100TQFP,Lead-free
IS61NVP204818A-166B3
165 PBGA
Industrial Range: -40°C to +85°C
Configuration
1Mx36
AccessTime
OrderPartNumber
Package
166
IS61NVP102436A-166TQI
IS61NVP102436A-166TQLI
100 TQFP
100TQFP,Lead-free
IS61NVP102436A-166B3I
165 PBGA
2Mx18
166
IS61NVP204818A-166TQI
IS61NVP204818A-166B3I
100 TQFP
165 PBGA
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/13/07
PACKAGING INFORMATION
Ball Grid Array
Package Code: B (165-pin)
BOTTOM VIEW
A1 CORNER
TOP VIEW
A1 CORNER
φ b (165X)
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D
D1
K
L
K
L
M
N
P
R
M
N
P
R
e
E1
E
A2
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS
INCHES
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
Min. Nom. Max.
165
N0.
Leads
165
A
—
0.25
—
—
1.20
0.40
—
—
—
0.047
0.010 0.013 0.016
0.031
A1
A2
D
0.33
0.79
—
—
14.90 15.00 15.10
13.90 14.00 14.10
12.90 13.00 13.10
9.90 10.00 10.10
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
D1
E
E1
e
—
1.00
0.45
—
—
0.039
—
b
0.40
0.50
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Notes:
Thin Quad Flat Pack (TQ)
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
Millimeters
Min Max
Inches
Millimeters
Inches
Min Max
Symbol
Ref. Std.
Min
Max
Min
Max
No. Leads (N)
100
128
A
A1
A2
b
D
D1
E
—
1.60
0.15
1.45
0.38
—
0.063
—
1.60
0.15
1.45
0.27
—
0.063
0.05
1.35
0.22
0.002 0.006
0.053 0.057
0.009 0.015
0.862 0.870
0.783 0.791
0.626 0.634
0.547 0.555
0.026 BSC
0.05
1.35
0.17
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
3. Controlling dimension:
millimeters.
21.90 22.10
19.90 20.10
15.90 16.10
13.90 14.10
0.65 BSC
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
E1
e
L
0.45
1.00 REF.
0o 7o
0.75
0.018 0.030
0.45
0.75
0.018 0.030
L1
C
0.039 REF.
1.00 REF.
0o
0.039 REF.
0o
7o
7o
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev.D 05/08/03
相关型号：
IS61NLP102436B-200B3LI
ZBT SRAM, 1MX36, 3.1ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, LEAD FREE, PLASTIC, TFBGA-165
ISSI
IS61NLP102436B-200TQLI
ZBT SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
ISSI
©2020 ICPDF网 联系我们和版权申明