IS61NVF409618B [ISSI]
100 percent bus utilization;
| 型号： | IS61NVF409618B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 100 percent bus utilization |
| 文件： | 总38页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
2M x 36 and 4M x 18
72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
ADVANCED INFORMATION
FEBRUARY 2013
FEATURES
DESCRIPTION
The72Megproductfamilyfeatureshigh-speed,low-power
synchronousstaticRAMsdesignedtoprovideaburstable,
high-performance, 'no wait' state, device for networking
and communications applications. They are organized as
2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with ISSI's advanced CMOS technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
AllRead,WriteandDeselectcyclesareinitiatedbytheADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
• Power supply:
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol
Parameter
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
tkq
Clock Access Time
Cycle Time
tkc
ns
Frequency
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
BLOCK DIAGRAM
A0-20 ( A0-21)
A0-20 ( A0-21)
A2-20(A2-A21)
Burst Logic
A0-20(A0-21)
Address
MODE
2Mx36;
4Mx18
Memory Array
Registers
ADV
A0-A1
A'0-A'1
K
K
Address
Registers
Address
Registers
CLK
/CKE
Data-In
Register
K
K
/CE
CE2
/CE2
Data-In
Register
Control Logic
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
/OE
ZZ
Output
Buffers
K
36(18)
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN BGA
165-PIN BGA
119-Ball, 14x22 mm BGA
165-Ball, 13x15 mm BGA
1.27mm Ball Pitch, 7x17 Ball Array
165-Ball, 15x17 mm BGA
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION — 2M x 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
ADV
OE
A
NC
A
CE2
A
A
NC
DQPc
DQc
DQc
DQc
DQc
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
DQPb
DQb
DQb
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQPd
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
DQa
DQa
DQa
DQa
DQPa
NC
K
L
M
N
P
R
TDI
A1*
TDO
TCK
MODE
A
A
A
TMS
A0*
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
Synchronous Burst Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQd
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWd
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN PBGA PACKAGE CONFIGURATION
2M x 36 (TOP VIEW)
1
2
A
3
A
4
5
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
A
VDDQ
NC
CE2
A
A
ADV
VDD
NC
CE
A
CE2
A
NC
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
VSS
VSS
BWb
VSS
NC
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
OE
A
G
H
J
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
K
L
VSS
BWd
VSS
VSS
VSS
MODE
A
VSS
BWa
VSS
VSS
VSS
NC
M
N
P
R
T
NC
A
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
Synchronous Burst Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQd
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWd
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
165-PIN PBGA PACKAGE CONFIGURATION
4M x 18 (TOP VIEW)
1
NC
2
A
3
4
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
CE
BWb
NC
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CKE
WE
ADV
OE
A
NC
A
CE2
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
K
L
NC
NC
M
N
P
R
NC
NC
TDI
A1*
TDO
TCK
NC
MODE
A
A
A
TMS
A0*
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
Synchronous Burst Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQb
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWb
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN PBGA PACKAGE CONFIGURATION
4M x 18 (TOP VIEW)
1
2
A
3
A
4
5
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
A
VDDQ
NC
CE2
A
A
ADV
VDD
NC
CE
A
CE2
A
NC
A
A
NC
DQb
NC
NC
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
NC
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
DQb
NC
DQa
VDDQ
DQa
NC
VDDQ
NC
OE
A
G
H
J
DQb
NC
DQb
VDDQ
NC
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
VSS
NC
VDD
DQb
NC
VDDQ
DQa
NC
K
L
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
DQb
VDDQ
DQb
NC
M
N
P
R
T
DQb
NC
VSS
VSS
VSS
MODE
A
VDDQ
NC
DQPb
A
DQa
NC
NC
A
A
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
Synchronous Burst Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQb
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWb
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
DQPc
DQc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQc
DQb
V
DDQ
Vss
V
DDQ
Vss
DQc
DQc
DQb
DQb
DQc
DQc
Vss
DQb
DQb
Vss
V
DDQ
V
DDQ
DQc
DQb
DQc
NC
DQb
Vss
NC
VDD
NC
Vss
VDD
ZZ
DQa
DQa
DQd
DQd
V
DDQ
VDDQ
Vss
DQd
Vss
DQa
DQa
DQd
DQd
DQd
Vss
DQa
DQa
Vss
V
DDQ
V
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2M x 36
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
Synchronous Burst Address Inputs
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQd
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWd
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
Vss
VDDQ
Vss
NC
NC
NC
DQPa
DQb
DQa
DQa
Vss
DQb
Vss
V
DDQ
VDDQ
DQb
DQa
DQb
NC
DQa
Vss
NC
VDD
NC
Vss
VDD
ZZ
DQb
DQb
DQa
DQa
V
DDQ
VDDQ
Vss
DQb
Vss
DQa
DQa
DQb
DQPb
NC
NC
NC
Vss
Vss
V
DDQ
VDDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4M x 18
PIN DESCRIPTIONS
Symbol
Pin Name
MODE
Burst Sequence Selection
JTAG Pins
A
Synchronous Address Inputs
TCK, TDI
TDO, TMS
A0, A1
ADV
Synchronous Burst Address Inputs
VDD
Power Supply
Synchronous Burst Address Advance/
Load
NC
No Connect
WE
Synchronous Read/Write Control Input
Synchronous Clock
DQa-DQb
Synchronous Data Inputs/Outputs
CLK
CKE
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Synchronous Clock Enable
VDDQ
I/O Power Supply
CE, CE2, CE2 Synchronous Chip Enable
Vss
Ground
BWa-BWb
OE
Synchronous Byte Write Inputs
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
STATE DIAGRAM
READ
WRITE
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
WRITE
BURST
BURST
DS
DS
DS
WRITE
BURST
READ
BURST
WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation
Used
CE
H
X
X
X
L
CE2 CE2 ADV
WE
X
X
X
X
H
X
H
X
L
BWx
X
OE
CKE CLK
Not Selected
N/A
X
L
X
X
H
X
L
L
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Not Selected
N/A
X
Not Selected
N/A
X
X
H
X
H
X
H
X
H
X
X
L
X
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
N/A
H
L
X
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
X
L
X
L
H
L
X
L
X
H
H
X
X
X
X
X
X
L
X
L
H
L
X
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
L
X
L
X
L
H
L
X
L
L
H
H
X
Next Address
Current Address
X
X
X
X
H
X
X
X
Ignore Clock
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
ASYNCHRONOUS TRUTH TABLE(1)
Operation
Sleep Mode
Read
ZZ
OE
I/O STATUS
H
X
High-Z
L
L
L
H
DQ
High-Z
Write
L
L
X
X
Din, High-Z
High-Z
Deselected
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
H
L
BWa
X
BWb
READ
X
H
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
L
H
L
L
L
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
WRITE TRUTH TABLE (x36)
Operation
WE
H
L
BWa
X
BWb
X
BWc
X
BWd
X
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
POWER UP SEQUENCE
1
Vddq → Vdd → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POWER-UP INITIALIZATION TIMING
VDD
power > 1ms
Device ready for
normal operation
VDD
Device Initialization
VDDQ
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
12
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TsTG
Parameter
NLF Value
–65 to +150
1.6
NVF/NVVF Value
–65 to +150
1.6
Unit
°C
W
Storage Temperature
Power Dissipation
Output Current (per I/O)
Pd
iouT
100
100
mA
V
Vin, VouT
Vin
Voltage Relative to Vss for I/O Pins –0.5 to Vddq + 0.3
–0.5 to Vddq + 0.3
–0.3 to Vdd + 0.3
Voltage Relative to Vss for
–0.3 to Vdd + 0.5
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precau-
tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLFx)
Range
Ambient Temperature
0°C to +70°C
VDD
VDDq
Commercial
Industrial
3.3V ± 5%
3.3V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
-40°C to +85°C
OPERATING RANGE (IS61NVFx)
Range
Ambient Temperature
0°C to +70°C
VDD
VDDq
Commercial
Industrial
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
-40°C to +85°C
OPERATING RANGE (IS61NVVFx)
Range
Ambient Temperature
0°C to +70°C
VDD
VDDq
Commercial
Industrial
1.8V ± 5%
1.8V ± 5%
1.8V ± 5%
1.8V ± 5%
-40°C to +85°C
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3
3.3V
2.5V
Max.
1.8V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Min.
Max.
Unit
Voh
Output HIGH Voltage
ioh = –4.0 mA (3.3V)
2.4
—
2.0
—
Vddq - 0.4
—
V
ioh = –1.0 mA (2.5V, 1.8V)
Vol
Output LOW Voltage
iol = 8.0 mA (3.3V)
—
0.4
—
0.4
—
0.4
V
iol = 1.0 mA (2.5V, 1.8V)
Vih
Vil
ili
Input HIGH Voltage
Input LOW Voltage
2.0 Vdd + 0.3
1.7 Vdd + 0.3
0.6Vdd Vdd + 0.3
V
V
–0.3
0.8
–0.3
0.7
–0.3 0.3Vdd
(1,4)
Input Leakage Current
Input Current of MODE
Input Current of ZZ
Vss ≤ Vin ≤ Vdd
Vss ≤ Vin ≤ Vdd
Vss ≤ Vin ≤ Vdd
–5
–30
–5
5
5
30
–5
–30
–5
5
5
30
–5
–30
–5
5
5
30
µA
(5)
(6)
ilo
Output Leakage Current
Vss ≤ VouT ≤ Vddq, OE = Vih
–5
5
–5
5
–5
5
µA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. Except MODE and ZZ.
5. MODE is connected to pull-up resister internally.
6. ZZ is connected to pull-down resister internally
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5
MAX
7.5
MAX
Symbol Parameter
Test Conditions
Temp. range
x18
x36
x18
x36
Unit
icc
isb
Isbi
AC Operating
Supply Current
Device Selected,
OE = Vih, ZZ ≤ Vil,
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Com.
Ind.
260
270
260
270
240
250
240
250
mA
Standby Current
TTL Input
Device Deselected,
Vdd = Max.,
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Com.
Ind.
130
135
130
135
130
135
130
135
mA
Standby Current
Device Deselected,
Com.
115
115
115
115
mA
cMos Input
Vdd = Max.,
Ind.
120
120
120
120
Vin
≤ Vss + 0.2V or ≥Vdd – 0.2V
f = 0
14
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
Vin = 0V
Max.
Unit
pF
cin
Input Capacitance
Input/Output Capacitance
6
8
couT
VouT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°c, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
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15
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
1.8V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 1.8V
1.5 ns
Input Rise and Fall Times
Input and Output Timing
and Reference Level
0.9V
Output Load
See Figures 5 and 6
1.8V I/O OUTPUT LOAD EQUIVALENT
1K Ω
+1.8V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1K Ω
0.9V
Figure 5
Figure 6
16
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Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5
Min.
7.5
Min. Max.
Symbol
fmax
tkc
Parameter
Max.
133
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Clock Frequency
—
7.5
2.2
2.2
—
—
8.5
2.5
2.5
—
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycle Time
tkh
Clock High Time
—
tkl
Clock Low Time
—
tkq
Clock Access Time
6.5
—
(2)
tkqx
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
2.5
2.5
—
2.5
2.5
—
(2,3)
tkqlZ
—
(2,3)
tkqhZ
3.8
3.2
—
toeq
—
—
(2,3)
toelZ
0
0
(2,3)
toehZ
—
3.5
—
—
tAs
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
tws
tces
tse
Read/Write Setup Time
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
—
—
—
tAdVs
tds
—
—
tAh
Address Hold Time
—
the
Clock Enable Hold Time
Write Hold Time
—
twh
tceh
tAdVh
tdh
—
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
—
—
—
(4)
tPower
Vdd (typical) to First Access
—
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. tPower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions Temperature
Min. Max.
Unit
Range
Isb2
Current during SNOOZE MODE ZZ ≥ Vdd - 0.2V
Com.
Ind.
Auto.
—
—
—
80
90
100
mA
tpds
tpus
tzzi
ZZ active to input ignored
—
2
2
—
2
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
—
0
trzzi
—
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
All Inputs
I
SB2
t
RZZI
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
18
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
READ CYCLE TIMING
t
KH
tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
t
SE tHE
t
CES
t
CEH
CE
OE
t
DS
KQ
t
OEQ
t
OEHZ
t
t
KQHZ
Q3-4
tOEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
WRITE CYCLE TIMING
t
KH
tKL
CLK
t
KC
ADV
Address
WRITE
CKE
A1
A2
A3
tSE
tHE
CE
OE
tDS
t
DH
Data In
Data Out
D1-1
D2-1
D2-2
D2-4
D3-1
D3-2
D3-3
D3-4
D2-3
tOEHZ
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
20
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
SINGLE READ/WRITE CYCLE TIMING
t
KH
tKL
CLK
t
SE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
t
OEQ
tOELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
t
DS
tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CKE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
t
KC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
tKQ
tKQHZ
tKQLZ
Q4
Data Out
Data In
Q1
Q3
t
DS
t
DH
D5
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
22
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
tOEQ
t
KQHZ
t
KQ
t
OELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
The serial boundary scan Test Access Port (TAP) is only
available in the PBGA package. (Not available in TQFP
package.) This port operates in accordance with IEEE
Standard 1149.1-1900, but does not include all functions
required for full 1149.1 compliance. These functions from
the IEEE specification are excluded because they place
added delay in the critical speed path of the SRAM. The
TAP controller operates in a manner that does not conflict
with the performance of other devices using 1149.1 fully
compliant TAPs.
ThetestclockisonlyusedwiththeTAPcontroller.Allinputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
DISABLING THE JTAG FEATURE
The TDI pin is used to serially input information to the
registers and can be connected to the input of any regis-
ter. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an applica-
tion. TDI is connected to the Most Significant Bit (MSB)
on any register.
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDOshouldbeleftdisconnected.Onpower-up,thedevice
will start in a reset state which will not interfere with the
device operation.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
24
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the cur-
rent state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge
of TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed be-
tween the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Instruction Register
Register
Name
Bit Size
Bit Size
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
(x18)
3
(x36)
3
Instruction
Bypass
1
1
ID
32
75
32
75
Boundary Scan
When theTAPcontroller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Identification (ID) Register
Bypass Register
The ID register is loaded with a vendor-specific, 32-bit
codeduringtheCapture-DRstatewhentheIDCODEcom-
mand is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Description
2M x 36
xxxx
4M x 18
xxxx
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Reserved for version number.
Defines depth of SRAM. 2M or 4M
Defines Width of the SRAM. x36 or x18
Reserved for future use.
01010
01011
00100
00011
xxxxx
xxxxx
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
00001010101
1
00001010101
1
Integrated Silicon Solution, Inc. — www.issi.com
25
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
TheTAPcontrollercannotbeusedtoloadaddress, dataor
control signals and cannot preload the Input or Output buf-
fers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instruc-
tions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, theTAPcontrol-
ler must be moved into the Update-IR state.
SAMPLE/PRELOADisa1149.1mandatoryinstruction.The
PRELOADportionofthisinstructionisnotimplemented,so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruc-
tion register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock oper-
ates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition(metastablestate).Thedevicewillnotbeharmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
thecorrectsignalvalue,theSRAMsignalmustbestabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM
clock input is captured correctly, designs need a way to
stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is not an issue, it is possible to capture
all other signals and simply ignore the value of the CLK
captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
TheTAPcontrollerrecognizesanall-0instruction.Whenan
EXTEST instruction is loaded into the instruction register,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
hasbeenloaded. Thereisadifferencebetweenthe instruc-
tions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-
DR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-
bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tion register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
RESERVED
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
all SRAM outputs into a High-Z state.
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
INSTRUCTION CODES
Code
Instruction
Description
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011
RESERVED
Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
Integrated Silicon Solution, Inc. — www.issi.com
27
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP Electrical Characteristics(Vddq = 3.3V Operating Range)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Parameter
Test Conditions
Min.
2.4
2.9
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Ioh = -4 mA
Ioh = -100 µA
Iol = 8 mA
—
V
0.4
V
Iol = 100 µA
—
0.2
V
2.0
-0.3
-30
Vdd+0.3
0.8
V
Vil
V
Ix
Vss ≤ Vin ≤ Vddq
30
µA
TAP Electrical Characteristics(Vddq = 2.5V Operating Range)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Parameter
Test Conditions
Min.
2.0
2.1
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Ioh = -1 mA
Ioh = -100 µA
Iol = 1 mA
—
V
0.4
V
Iol = 100 µA
—
0.2
V
1.7
-0.3
-30
Vdd+0.3
0.7
V
Vil
V
Ix
Vss ≤ Vin ≤ Vddq
30
µA
TAP Electrical Characteristics(Vddq = 1.8V Operating Range)
Symbol
Voh1
Vol1
Vih
Parameter
Test Conditions
Min.
Vdd-0.4
—
Max.
—
Units
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Ioh = -1 mA
Iol = 1 mA
0.5
V
1.3
Vdd+0.3
0.7
V
Vil
-0.3
V
Ix
Vss ≤ Vin ≤ Vddq
-30
30
µA
28
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP AC ELECTRICAL CHARACTERISTICS(OVER OPERATING RANGE)
Parameter
Symbol
tTHTH
tTHTL
Min
100
40
40
10
10
10
10
–
Max
Units
TCK cycle time
TCK high pulse width
TCK low pulse width
TMS Setup
–
ns
–
ns
tTLTH
–
ns
tMVTH
tTHMX
tDVTH
tTHDX
tTLOV
–
ns
TMS Hold
–
ns
TDI Setup
–
ns
TDI Hold
–
ns
TCK Low to Valid Data
20
ns
TAP AC TEST CONDITIONS
(1.8V/2.5V/3.3V)Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Test load termination supply voltage
Vtrig
0 to 1.8V/0 to 2.5V/0 to 3.0V
1.5ns
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
TAP Output Load Equivalent
50Ω
Vtrig
TDO
20 pF
GND
Z0 = 50Ω
TAP TIMING
1
2
3
4
5
6
t
THTH
tTLTH
TCK
tTHTL
t
t
MVTH THMX
t
TMS
DVTH
tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. — www.issi.com
29
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
BOUNDARY SCAN ORDER
165 BGA
119 BGA
X36
Bump ID
N6
N7
X18
Bump ID
X36
Bump ID
X18
Bump ID
Bit #
1
2
Signal
NC
NC
Signal
NC
NC
Bit #
1
2
Signal
NC
NC
Signal
NC
NC
N6
N7
3
4
5
6
7
8
9
N10
P11
P8
R8
R9
NC
NC
A18
A17
A16
A15
A14
A13
N10
P11
P8
R8
R9
NC
NC
3
4
5
6
7
8
9
NC
NC
A18
A17
A16
A15
A14
A13
NC
NC
A18
A17
A16
A15
A14
A13
A12
ZZ
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
ZZ
NC
NC
NC
NC
P9
P9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A12
ZZ
A12
ZZ
T7
P6
N7
M6
L7
K6
P7
N6
L6
T7
P6
N7
M6
L7
K6
P7
N6
L6
DQa0
DQa1
DQa2
DQa6
DQa7
DQa3
DQa4
DQa5
DQa8
NC
DQa0
DQa1
DQa2
DQa6
DQa7
DQa3
DQa4
DQa5
DQa8
NC
NC
NC
DQa8
DQa7
DQa6
DQa5
NC
DQa8
DQa7
DQa6
DQa5
NC
K7
K7
NC
NC
NC
NC
DQb8
DQb7
DQb5
DQb4
DQb6
DQb3
DQb2
DQb1
DQb0
NC
NC
A11
A10
A9
A8
NC
DQa4
DQa3
DQa2
DQa1
NC
NC
NC
NC
DQa0
A21
NC
A11
A10
A9
H6
G7
F6
E7
H7
G6
E6
D7
D6
T1
DQb8
DQb7
DQb5
DQb4
DQb6
DQb3
DQb2
DQb1
DQb0
NC
NC
A11
A10
A9
A8
NC
H6
G7
F6
E7
H7
G6
E6
D7
D6
T1
DQa4
DQa3
DQa2
DQa1
NC
NC
NC
NC
DQa0
A21
NC
A11
A10
A9
G4
A4
G4
A4
B9
C10
A8
B8
A7
B9
C10
A8
B8
A7
A8
NC
A8
NC
ADV
/OE
/CKE
/WE
CLK
ADV
/OE
/CKE
/WE
CLK
B4
F4
M4
H4
K4
ADV
/OE
/CKE
/WE
CLK
B4
F4
M4
H4
K4
ADV
/OE
/CKE
/WE
CLK
B7
B6
B7
B6
Continued on next page
30
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
165 BGA
119 BGA
X36
Bump ID
X18
Bump ID
X36
Bump ID
X18
Bump ID
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Signal
/CE2
/Bwa
/Bwb
/Bwc
/Bwd
CE2
/CE1
A7
A6
NC
NC
NC
DQc0
DQc1
DQc2
DQc6
DQc7
DQc3
DQc4
DQc5
DQc8
NC
Signal
/CE2
/Bwa
NC
/Bwb
NC
CE2
/CE1
A7
A6
NC
NC
NC
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Signal
/CE2
/Bwa
/Bwb
/Bwc
/Bwd
CE2
/CE1
A7
A6
NC
NC
NC
DQc0
DQc1
DQc2
DQc6
DQc7
DQc3
DQc4
DQc5
DQc8
NC
Signal
/CE2
/Bwa
NC
/Bwb
NC
CE2
/CE1
A7
A6
NC
NC
NC
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H2
H3
J1
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H2
H3
J1
B6
L5
G5
G3
L3
B6
L5
G5
G3
L3
B2
E4
B2
E4
NC
NC
NC
NC
D2
E1
F2
G1
H2
D1
E2
G2
H1
D2
E1
F2
G1
H2
D1
E2
G2
H1
NC
NC
NC
NC
NC
NC
DQb8
DQb7
DQb6
DQb5
NC
DQb8
DQb7
DQb6
DQb5
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQd8
DQd7
DQd5
DQd4
DQd6
DQd3
DQd2
DQd1
DQd0
NC
NC
MODE
A4
A3
A2
A5
A19
A20
NC
A1
A0
Int
DQb4
DQb3
DQb2
DQb1
NC
NC
NC
NC
DQb0
NC
NC
MODE
A4
A3
A2
K2
L1
M2
N1
K1
L2
N2
P1
P2
DQd8
DQd7
DQd5
DQd4
DQd6
DQd3
DQd2
DQd1
DQd0
NC
NC
MODE
A4
A3
A2
A5
A19
A20
NC
A1
A0
Int
K2
L1
M2
N1
K1
L2
N2
P1
P2
DQb4
DQb3
DQb2
DQb1
NC
NC
NC
NC
DQb0
NC
NC
MODE
A4
A3
A2
K1
L1
M1
J2
K1
L1
M1
J2
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
*
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
*
R3
R3
A5
A5
A19
A20
NC
A1
A0
A19
A20
NC
A1
A0
T2
T2
N4
P4
*
N4
P4
*
Int
Int
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Commercial Range: 0°C to 70°C(VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time x36
IS61NLF204836B-6.5TQ
x18
Package
IS61NLF409618B-6.5TQ
IS61NLF409618B-6.5B3
IS61NLF409618B-6.5M3
IS61NLF409618B-6.5B2
IS61NLF409618B-6.5TQL
IS61NLF409618B-6.5B3L
IS61NLF409618B-6.5M3L
IS61NLF409618B-6.5B2L
IS61NLF409618B-7.5TQ
IS61NLF409618B-7.5B3
IS61NLF409618B-7.5M3
IS61NLF409618B-7.5B2
IS61NLF409618B-7.5TQL
IS61NLF409618B-7.5B3L
IS61NLF409618B-7.5M3L
IS61NLF409618B-7.5B2L
100 TQFP
IS61NLF204836B-6.5B3
IS61NLF204836B-6.5M3
IS61NLF204836B-6.5B2
IS61NLF204836B-6.5TQL
IS61NLF204836B-6.5B3L
IS61NLF204836B-6.5M3L
IS61NLF204836B-6.5B2L
IS61NLF204836B-7.5TQ
IS61NLF204836B-7.5B3
IS61NLF204836B-7.5M3
IS61NLF204836B-7.5B2
IS61NLF204836B-7.5TQL
IS61NLF204836B-7.5B3L
IS61NLF204836B-7.5M3L
IS61NLF204836B-7.5B2L
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
6.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
100 TQFP
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
Commercial Range: 0°C to 70°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36
IS61NVF204836B-6.5TQ
x18
Package
IS61NVF409618B-6.5TQ
IS61NVF409618B-6.5B3
IS61NVF409618B-6.5M3
IS61NVF409618B-6.5B2
IS61NVF409618B-6.5TQL
IS61NVF409618B-6.5B3L
IS61NVF409618B-6.5M3L
IS61NVF409618B-6.5B2L
IS61NVF409618B-7.5TQ
IS61NVF409618B-7.5B3
IS61NVF409618B-7.5M3
IS61NVF409618B-7.5B2
IS61NVF409618B-7.5TQL
IS61NVF409618B-7.5B3L
IS61NVF409618B-7.5M3L
IS61NVF409618B-7.5B2L
100 TQFP
IS61NVF204836B-6.5B3
IS61NVF204836B-6.5M3
IS61NVF204836B-6.5B2
IS61NVF204836B-6.5TQL
IS61NVF204836B-6.5B3L
IS61NVF204836B-6.5M3L
IS61NVF204836B-6.5B2L
IS61NVF204836B-7.5TQ
IS61NVF204836B-7.5B3
IS61NVF204836B-7.5M3
IS61NVF204836B-7.5B2
IS61NVF204836B-7.5TQL
IS61NVF204836B-7.5B3L
IS61NVF204836B-7.5M3L
IS61NVF204836B-7.5B2L
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
6.5MHz
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
100 TQFP
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
32
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Commercial Range: 0°C to 70°C(VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
IS61NVVF204836B-7.5TQ
x18
Package
IS61NVVF409618B-7.5TQ
IS61NVVF409618B-7.5B3
IS61NVVF409618B-7.5M3
IS61NVVF409618B-7.5B2
IS61NVVF409618B-7.5TQL
IS61NVVF409618B-7.5B3L
IS61NVVF409618B-7.5M3L
IS61NVVF409618B-7.5B2L
100 TQFP
IS61NVVF204836B-7.5B3
IS61NVVF204836B-7.5M3
IS61NVVF204836B-7.5B2
IS61NVVF204836B-7.5TQL
IS61NVVF204836B-7.5B3L
IS61NVVF204836B-7.5M3L
IS61NVVF204836B-7.5B2L
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, 3CE, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time x36
IS61NLF204836B-6.5TQI
x18
Package
IS61NLF409618B-6.5TQI
IS61NLF409618B-6.5B3I
IS61NLF409618B-6.5M3I
IS61NLF409618B-6.5B2I
IS61NLF409618B-6.5TQLI
IS61NLF409618B-6.5B3LI
IS61NLF409618B-6.5M3LI
IS61NLF409618B-6.5B2LI
IS61NLF409618B-7.5TQI
IS61NLF409618B-7.5B3I
IS61NLF409618B-7.5M3I
IS61NLF409618B-7.5B2I
IS61NLF409618B-7.5TQLI
IS61NLF409618B-7.5B3LI
IS61NLF409618B-7.5M3LI
IS61NLF409618B-7.5B2LI
100 TQFP
IS61NLF204836B-6.5B3I
IS61NLF204836B-6.5M3I
IS61NLF204836B-6.5B2I
IS61NLF204836B-6.5TQLI
IS61NLF204836B-6.5B3LI
IS61NLF204836B-6.5M3LI
IS61NLF204836B-6.5B2LI
IS61NLF204836B-7.5TQI
IS61NLF204836B-7.5B3I
IS61NLF204836B-7.5M3I
IS61NLF204836B-7.5B2I
IS61NLF204836B-7.5TQLI
IS61NLF204836B-7.5B3LI
IS61NLF204836B-7.5M3LI
IS61NLF204836B-7.5B2LI
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
6.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
100 TQFP
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
33
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Industrial Range: -40°C to +85°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time
x36
x18
Package
IS61NVF204836B-6.5TQI
IS61NVF204836B-6.5B3I
IS61NVF204836B-6.5M3I
IS61NVF204836B-6.5B2I
IS61NVF204836B-6.5TQLI
IS61NVF204836B-6.5B3LI
IS61NVF204836B-6.5M3LI
IS61NVF204836B-6.5B2LI
IS61NVF204836B-7.5TQI
IS61NVF204836B-7.5B3I
IS61NVF204836B-7.5M3I
IS61NVF204836B-7.5B2I
IS61NVF204836B-7.5TQLI
IS61NVF204836B-7.5B3LI
IS61NVF204836B-7.5M3LI
IS61NVF204836B-7.5B2LI
IS61NVF409618B-6.5TQI
IS61NVF409618B-6.5B3I
IS61NVF409618B-6.5M3I
IS61NVF409618B-6.5B2I
IS61NVF409618B-6.5TQLI
IS61NVF409618B-6.5B3LI
IS61NVF409618B-6.5M3LI
IS61NVF409618B-6.5B2LI
IS61NVF409618B-7.5TQI
IS61NVF409618B-7.5B3I
IS61NVF409618B-7.5M3I
IS61NVF409618B-7.5B2I
IS61NVF409618B-7.5TQLI
IS61NVF409618B-7.5B3LI
IS61NVF409618B-7.5M3LI
IS61NVF409618B-7.5B2LI
100 TQFP
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
6.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
100 TQFP
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
IS61NVVF204836B-7.5TQI
x18
Package
IS61NVVF409618B-7.5TQI
IS61NVVF409618B-7.5B3I
IS61NVVF409618B-7.5M3I
IS61NVVF409618B-7.5B2I
IS61NVVF409618B-7.5TQLI
IS61NVVF409618B-7.5B3LI
IS61NVVF409618B-7.5M3LI
IS61NVVF409618B-7.5B2LI
100 TQFP
IS61NVVF204836B-7.5B3I
IS61NVVF204836B-7.5M3I
IS61NVVF204836B-7.5B2I
IS61NVVF204836B-7.5TQLI
IS61NVVF204836B-7.5B3LI
IS61NVVF204836B-7.5M3LI
IS61NVVF204836B-7.5B2LI
165 PBGA,13x15mm
165 PBGA,15x17mm
119 PBGA
7.5ns
100 TQFP, Lead-free
165 PBGA,13x15mm, Lead-free
165 PBGA,15x17mm, Lead-free
119 PBGA, Lead-free
Automotive(A3) Range: -40°C to +125°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time x36 x18
Please contact ISSI (SRAM@issi.com)
Package
Automotive(A3) Range: -40°C to +125°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36 x18
Please contact ISSI (SRAM@issi.com)
Package
Package
Automotive(A3) Range: -40°C to +125°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time x36 x18
Please contact ISSI (SRAM@issi.com)
34
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Integrated Silicon Solution, Inc. — www.issi.com
35
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
36
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Integrated Silicon Solution, Inc. — www.issi.com
37
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
相关型号：
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