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IS61SF12836-12B [ISSI]

x36 Fast Synchronous SRAM ; X36高速同步SRAM
IS61SF12836-12B
型号： IS61SF12836-12B
厂家： INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述：

x36 Fast Synchronous SRAM
X36高速同步SRAM

静态存储器
文件： 总16页 (文件大小：114K)
中文：  中文翻译
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®
IS61SF12832  
IS61SF12836  
128K x 32, 128K x 36 SYNCHRONOUS  
FLOW-THROUGH STATIC RAM  
ISSI  
APRIL 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61SF12832 and IS61SF12836 are high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 131,072  
words by 32 bits or 36 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
a single monolithic circuit. All synchronous inputs pass  
through registers controlled by a positive-edge-triggered  
single clock input.  
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,  
and 12 ns  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data  
inputs and control signals  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,  
BW4 controls DQd, conditioned by BWE being LOW. A LOW  
on GW input would cause all bytes to be written.  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V +10%, –5% power supply  
• Power-down snooze mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins.Subsequentburstaddressescanbegeneratedinternally  
and controlled by the ADV (burst address advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle Time  
7.5  
7.5  
8.5  
117  
8
8
10  
100  
8.5  
8.5  
11  
10  
10  
15  
66  
12  
12  
15  
66  
Units  
ns  
ns  
tKC  
Frequency  
90  
MHz  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
BLOCK DIAGRAM  
MODE  
A0  
A0'  
A1'  
Q0  
CLK  
CLK  
BINARY  
COUNTER  
Q1  
CE  
ADV  
A1  
ADSC  
ADSP  
128K x 32, 128K x 36  
MEMORY ARRAY  
CLR  
17  
15  
17  
D
Q
A16-A0  
ADDRESS  
REGISTER  
CE  
CLK  
32  
or  
32  
or  
36  
36  
D
Q
GW  
BWE  
DQd  
BYTE WRITE  
REGISTERS  
BW4  
CLK  
D
Q
DQc  
BYTE WRITE  
REGISTERS  
BW3  
CLK  
D
Q
DQb  
BYTE WRITE  
REGISTERS  
BW2  
BW1  
CLK  
D
Q
DQa  
BYTE WRITE  
REGISTERS  
CLK  
CE  
CE2  
CE2  
4
32 or 36  
INPUT  
D
Q
REGISTERS  
ENABLE  
DQ[31:0] or  
DQ[35:0]  
OE  
REGISTER  
CLK  
CE  
CLK  
D
Q
ENABLE  
DELAY  
REGISTER  
CLK  
OE  
2
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
PIN CONFIGURATION  
119-pin PBGA (Top View)  
100-Pin TQFP  
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
100  
VCCQ  
NC  
A6  
CE2  
A7  
A4  
A3  
ADSP  
ADSC  
VCC  
NC  
A8  
A16  
CE2  
VCCQ  
NC  
1
2
3
4
5
6
7
8
9
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
DQc1  
DQc2  
VCCQ  
GND  
DQc3  
DQc4  
DQc5  
DQc6  
GND  
VCCQ  
DQc7  
DQc8  
NC  
VCC  
NC  
DQb8  
DQb7  
VCCQ  
GND  
DQb6  
DQb5  
DQb4  
DQb3  
GND  
VCCQ  
DQb2  
DQb1  
GND  
NC  
A9  
NC  
A2  
A12  
A15  
NC  
DQc1  
DQc2  
VCCQ  
DQc5  
DQc7  
VCCQ  
DQd1  
DQd4  
VCCQ  
DQd6  
DQd8  
NC  
NC  
GND  
GND  
GND  
BW3  
GND  
NC  
GND  
GND  
GND  
BW2  
GND  
NC  
NC  
DQb8  
DQb7  
VCCQ  
DQb3  
DQb1  
VCCQ  
DQa8  
DQa6  
VCCQ  
DQa2  
DQa1  
NC  
DQc3  
DQc4  
DQc6  
DQc8  
VCC  
DQd2  
DQd3  
DQd5  
DQd7  
NC  
CE  
DQb6  
DQb5  
DQb4  
DQb2  
VCC  
DQa7  
DQa5  
DQa4  
DQa3  
NC  
OE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
G
H
J
ADV  
GW  
VCC  
CLK  
NC  
VCC  
ZZ  
K
L
GND  
GND  
BW4  
GND  
GND  
GND  
MODE  
A10  
GND  
BW1  
GND  
GND  
GND  
GND  
A14  
DQa8  
DQa7  
VCCQ  
GND  
DQa6  
DQa5  
DQa4  
DQa3  
GND  
VCCQ  
DQa2  
DQa1  
NC  
DQd1  
DQd2  
VCCQ  
GND  
DQd3  
DQd4  
DQd5  
DQd6  
GND  
VCCQ  
DQd7  
DQd8  
NC  
M
N
P
R
T
BWE  
A1  
A0  
A5  
VCC  
A11  
NC  
A13  
NC  
NC  
NC  
ZZ  
U
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
VCCQ  
NC  
NC  
NC  
NC  
VCCQ  
128K x 32  
PIN DESCRIPTIONS  
A0, A1  
Synchronous Address Inputs. These  
pins must tied to the two LSBs of the  
address bus.  
GW  
Synchronous Global Write Enable  
CE, CE2, CE2 Synchronous Chip Enable  
OE  
Output Enable  
A2-A16  
CLK  
Synchronous Address Inputs  
Synchronous Clock  
DQa-DQd  
MODE  
VCC  
Synchronous Data Input/Output  
Burst Sequence Mode Selection  
+3.3V Power Supply  
Ground  
ADSP  
Synchronous Processor Address  
Status  
GND  
ADSC  
Synchronous Controller Address  
Status  
VCCQ  
Isolated Output Buffer Supply:  
+3.3V  
ADV  
Synchronous Burst Address Advance  
Individual Byte Write Enable  
ZZ  
Snooze Enable  
BW1-BW4  
BWE  
Synchronous Byte Write Enable  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
3
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
PIN CONFIGURATION  
119-pin PBGA (Top View)  
100-Pin TQFP  
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
100  
VCCQ  
NC  
A6  
A4  
A3  
ADSP  
ADSC  
VCC  
NC  
A8  
A16  
CE2  
VCCQ  
NC  
1
2
3
4
5
6
7
8
9
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQPb  
DQPc  
DQc1  
DQc2  
VCCQ  
GND  
DQc3  
DQc4  
DQc5  
DQc6  
GND  
VCCQ  
DQc7  
DQc8  
NC  
VCC  
NC  
DQb8  
DQb7  
VCCQ  
GND  
DQb6  
DQb5  
DQb4  
DQb3  
GND  
VCCQ  
DQb2  
DQb1  
GND  
CE2  
A9  
NC  
A7  
A2  
A12  
A15  
NC  
DQc1  
DQc2  
VCCQ  
DQc5  
DQc7  
VCCQ  
DQd1  
DQd4  
VCCQ  
DQd6  
DQd8  
NC  
DQPc  
DQc3  
DQc4  
DQc6  
DQc8  
VCC  
DQd2  
DQd3  
DQd5  
DQd7  
DQPd  
A5  
GND  
GND  
GND  
BW3  
GND  
NC  
GND  
GND  
GND  
BW2  
GND  
NC  
DQPb  
DQb6  
DQb5  
DQb4  
DQb2  
VCC  
DQa7  
DQa5  
DQa4  
DQa3  
DQPa  
A13  
DQb8  
DQb7  
VCCQ  
DQb3  
DQb1  
VCCQ  
DQa8  
DQa6  
VCCQ  
DQa2  
DQa1  
NC  
CE  
OE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
G
H
J
ADV  
GW  
VCC  
CLK  
NC  
NC  
VCC  
ZZ  
K
L
GND  
GND  
BW4  
GND  
GND  
GND  
MODE  
A10  
GND  
BW1  
GND  
GND  
GND  
GND  
A14  
DQa8  
DQa7  
VCCQ  
GND  
DQa6  
DQa5  
DQa4  
DQa3  
GND  
VCCQ  
DQa2  
DQa1  
DQPa  
DQd1  
DQd2  
VCCQ  
GND  
DQd3  
DQd4  
DQd5  
DQd6  
GND  
VCCQ  
DQd7  
DQd8  
DQPd  
M
N
P
R
T
BWE  
A1  
A0  
VCC  
A11  
NC  
NC  
NC  
NC  
ZZ  
U
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
VCCQ  
NC  
NC  
NC  
NC  
VCCQ  
128K x 36  
PIN DESCRIPTIONS  
A0, A1  
Synchronous Address Inputs. These  
pins must tied to the two LSBs of the  
address bus.  
GW  
Synchronous Global Write Enable  
CE, CE2, CE2 Synchronous Chip Enable  
OE  
Output Enable  
A2-A16  
CLK  
Synchronous Address Inputs  
Synchronous Clock  
DQa-DQd  
MODE  
VCC  
Synchronous Data Input/Output  
Burst Sequence Mode Selection  
+3.3V Power Supply  
Ground  
ADSP  
Synchronous Processor Address  
Status  
GND  
ADSC  
Synchronous Controller Address  
Status  
VCCQ  
Isolated Output Buffer Supply:  
+3.3V  
ADV  
Synchronous Burst Address Advance  
Individual Byte Write Enable  
ZZ  
Snooze Enable  
BW1-BW4  
BWE  
DQPa-DQPd Parity Data I/O  
Synchronous Byte Write Enable  
4
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
TRUTHTABLE  
Address  
Used  
Operation  
CE  
CE2  
CE2 ADSP ADSC ADV WRITE OE  
DQ  
Deselected, Power-down  
Deselected, Power-down  
Deselected, Power-down  
Deselected, Power-down  
Deselected, Power-down  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst Current  
Read Cycle, Suspend Burst Current  
Read Cycle, Suspend Burst Current  
Read Cycle, Suspend Burst Current  
Write Cycle, Suspend Burst Current  
Write Cycle, Suspend Burst Current  
None  
None  
None  
None  
None  
External  
External  
External  
Next  
Next  
Next  
Next  
Next  
H
L
L
X
X
L
X
X
L
X
L
X
H
X
H
X
L
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
L
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
Read  
Write  
Read  
Read  
Read  
Read  
Write  
Write  
Read  
Read  
Read  
Read  
Write  
Write  
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Q
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
Q
D
Q
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
High-Z  
Q
High-Z  
D
D
Q
High-Z  
Q
High-Z  
D
Next  
L
H
H
H
H
H
H
H
L
H
X
X
D
PARTIAL TRUTH TABLE  
Function  
GW  
BWE  
BW1  
BW2  
BW3  
BW4  
Read  
Read  
Write Byte 1  
Write All Bytes  
Write All Bytes  
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
H
H
L
X
H
H
L
X
X
X
Integrated Silicon Solution, Inc. — 1-800-379-4774  
5
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)  
External Address  
A1 A0  
1st Burst Address  
A1 A0  
2nd Burst Address  
A1 A0  
3rd Burst Address  
A1 A0  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
LINEAR BURST ADDRESS TABLE (MODE = GND)  
0,0  
A1', A0' = 1,1  
0,1  
1,0  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameter  
Value  
–40 to +85  
–55 to +150  
1.6  
Unit  
°C  
°C  
W
TBIAS  
TSTG  
PD  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
IOUT  
Output Current (per I/O)  
100  
mA  
V
V
VIN, VOUT Voltage Relative to GND for I/O Pins  
–0.5 to VCCQ + 0.3  
–0.5 to VCC + 0.5  
VIN  
Voltage Relative to GND for  
for Address and Control Inputs  
VCC  
Voltage on Vcc Supply Relatiive to GND  
–0.5 to 4.6  
V
Notes:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of  
this specification is not implied. Exposure to absolute maximum rating conditions for  
extendedperiodsmayaffectreliability.  
2. This device contains circuitry to protect the inputs against damage due to high static  
voltages or electric fields; however, precautions may be taken to avoid application of any  
voltage higher than maximum rated voltages to this high-impedance circuit.  
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.  
6
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
OPERATING RANGE  
Range  
Ambient Temperature  
VCC  
Commercial  
0°C to +70°C  
3.3V +10%, –5%  
Industrial  
–40°C to +85°C  
3.3V +10%, –5%  
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)  
Symbol Parameter  
Test Conditions  
IOH = –4.0 mA  
IOL = 8.0 mA  
Min.  
2.4  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
ILI  
Output HIGH Voltage  
—
0.4  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
—
V
2.0  
VCC + 0.3  
0.8  
V
–0.3  
V
(2)  
GND ≤ VIN ≤ VCCQ  
Com.  
Ind.  
–2  
–5  
2
5
µA  
ILO  
Output Leakage Current  
GND ≤ VOUT ≤ VCCQ, OE = VIH Com.  
–2  
–5  
2
5
µA  
Ind.  
POWER SUPPLY CHARACTERISTICS (Over Operating Range)  
7.5  
8
8.5  
10  
12  
Symbol  
Parameter  
TestConditions  
Max.  
Max.  
Max.  
Max.  
Max.  
Unit  
ICC  
ACOperating  
SupplyCurrent  
Device Selected,  
Com.  
Ind.  
270  
—
250  
260  
230  
240  
190  
200  
170  
180  
mA  
All Inputs = VIL or VIH  
OE = VIH, Vcc = Max.  
Cycle Time ≥ tKC min.  
ISB  
StandbyCurrent  
DeviceDeselected,  
VCC = Max.,  
All Inputs = VIH or VIL  
CLK Cycle Time ≥ tKC min.  
Com.  
Ind.  
50  
—
50  
60  
50  
60  
50  
60  
50  
60  
mA  
mA  
IZZ  
Power-down  
ModeCurrent  
ZZ = VCCQ  
ClockRunning  
Com.  
Ind.  
10  
—
10  
15  
10  
15  
10  
15  
10  
15  
All Inputs ≤ GND + 0.2V  
or ≥ Vcc – 0.2V  
Notes:  
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.  
2. The MODE pin should be tied to Vcc or GND. It exhibits 10 µA maximum leakage current when tied to ≤ GND + 0.2V  
or ≥ Vcc – 0.2V.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
7
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
CAPACITANCE(1,2)  
Symbol  
CIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
Unit  
pF  
Input Capacitance  
6
8
COUT  
Input/Output Capacitance  
VOUT = 0V  
pF  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.  
AC TEST CONDITIONS  
Parameter  
Input Pulse Level  
Input Rise and Fall Times  
Unit  
0V to 3.0V  
1.5 ns  
Input and Output Timing  
and Reference Level  
1.5V  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
317 Ω  
3.3V  
ZO = 50Ω  
OUTPUT  
Output  
Buffer  
50Ω  
30 pF  
351 Ω  
5 pF  
Including  
jig and  
scope  
1.5V  
Figure 1  
Figure 2  
8
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)  
7.5  
8
8.5  
Min. Max.  
10  
12  
Min. Max.  
Symbol  
Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(3)  
fMAX  
ClockFrequency  
—
8.5  
3
117  
—
—
—
7.5  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
—
—
—
10  
4
100  
—
—
—
8
—
11  
4.5  
4.5  
—
2
90  
—
—
—
8.5  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
—
2
66  
—
—
—
10  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
—
2
66  
—
—
—
12  
—
—
3.5  
5
(3)  
tKC  
Cycle Time  
tKH  
Clock High Time  
(3)  
tKL  
Clock Low Time  
3
4
(3)  
tKQ  
Clock Access Time  
—
2
—
2
(1)  
tKQX  
Clock High to Output Invalid  
Clock High to Output Low-Z  
Clock High to Output High-Z  
Output Enable to Output Valid  
OutputEnabletoOutputLow-Z  
OutputDisabletoOutputHigh-Z  
Address Setup Time  
Address Status Setup Time  
Write Setup Time  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
—
—
(1,2)  
tKQLZ  
0
0
0
0
0
(1,2)  
tKQHZ  
2
2
2
2
2
(3)  
tOEQ  
—
0
—
0
—
0
—
0
—
0
(1,2)  
tOELZ  
—
3.5  
—
—
—
—
—
—
—
—
—
—
(1,2)  
tOEHZ  
—
2
—
2
—
2
—
2
—
4
(3)  
tAS  
(3)  
tSS  
2
2
2
2
4
(3)  
tWS  
2
2
2
2
4
(3)  
tCES  
Chip Enable Setup Time  
Address Advance Setup Time  
Address Hold Time  
2
2
2
2
4
(3)  
tAVS  
2
2
2
2
4
(3)  
tAH  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
1.5  
1.5  
1.5  
1.5  
1.5  
(3)  
tSH  
Address Status Hold Time  
Write Hold Time  
(3)  
tWH  
(3)  
tCEH  
Chip Enable Hold Time  
Address Advance Hold Time  
(3)  
tAVH  
Notes:  
1. Guaranteed but not 100% tested. This parameter is periodically sampled.  
2. Tested with load in Figure 2.  
3. Tested with load in Figure 1.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
9
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
READ/WRITE CYCLE TIMING  
tKC  
CLK  
ADSP  
ADSC  
tKH  
tKL  
ADSP is blocked by CE inactive  
tSS  
tSH  
tSS  
tSH  
ADV  
tAS  
tAH  
A16-A0  
RD1  
WR1  
RD2  
RD3  
t
WS  
WS  
t
WH  
GW  
BWE  
t
tWH  
tWS  
tWH  
WR1  
BW4-BW1  
tCES  
tCEH  
CE Masks ADSP  
CE  
CE2  
CE2  
t
CES  
CES  
t
CEH  
CEH  
CE2 and CE2 only sampled with ADSP or ADSC  
Unselected with CE2  
t
t
tOEHZ  
OE  
tKQX  
tOEQX  
High-Z  
DATAOUT  
2a  
2b  
2c  
2d  
1a  
t
KQLZ  
tKQHZ  
t
KQX  
t
KQ  
t
KQHZ  
High-Z  
1a  
DATAIN  
tDS  
tDH  
Single Write  
Burst Read  
Single Read  
Flow-through  
Unselected  
10  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)  
7.5  
8
8.5  
10  
12  
Symbol  
Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(1)  
tKC  
Cycle Time  
8.5  
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10  
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11  
4.5  
4.5  
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)  
tKH  
Clock High Time  
(1)  
tKL  
Clock Low Time  
3
4
(1)  
tAS  
Address Setup Time  
Address Status Setup Time  
Write Setup Time  
2
2
(1)  
tSS  
2
2
2
2
4
(1)  
tWS  
2
2
2
2
4
(1)  
tDS  
Data In Setup Time  
Chip Enable Setup Time  
Address Advance Setup Time  
Address Hold Time  
Address Status Hold Time  
Data In Hold Time  
2
2
2
2
4
(1)  
tCES  
2
2
2
2
4
(1)  
tAVS  
2
2
2
2
4
(1)  
tAH  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
(1)  
tSH  
(1)  
tDH  
(1)  
tWH  
Write Hold Time  
(1)  
tCEH  
Chip Enable Hold Time  
Address Advance Hold Time  
(1)  
tAVH  
Notes:  
1. Tested with load in Figure 1.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
11  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
WRITE CYCLE TIMING  
tKC  
CLK  
tKH  
tKL  
ADSP is blocked by CE1 inactive  
ADSC initiate Write  
tSS  
tSH  
ADSP  
ADSC  
tAVH  
tAVS  
ADV must be inactive for ADSP Write  
ADV  
tAS  
tAH  
A16-A0  
WR1  
WR2  
WR3  
t
WS  
WS  
t
WH  
WH  
GW  
BWE  
t
t
tWS  
tWH  
tWS  
tWH  
BW4-BW1  
WR1  
WR2  
CE1 Masks ADSP  
WR3  
tCES  
tCEH  
CE  
CE2  
CE2  
t
CES  
CES  
t
CEH  
Unselected with CE2  
CE2 and CE3 only sampled with ADSP or ADSC  
t
tCEH  
OE  
DATAOUT  
DATAIN  
High-Z  
tDS  
tDH  
BW4-BW1 only are applied to first cycle of WR2  
2a 2b 2c 2d  
High-Z  
3a  
1a  
Burst Write  
Single Write  
Write  
Unselected  
12  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)  
7.5  
8
8.5  
10  
12  
Symbol  
Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
(3)  
tKC  
Cycle Time  
8.5  
3
—
—
—
7.5  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
10  
4
—
—
—
8
11  
4.5  
4.5  
—
2
—
—
—
8.5  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
—
2
—
—
—
10  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
15  
4.5  
4.5  
—
2
—
—
—
12  
—
—
3.5  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
cyc  
cyc  
(3)  
tKH  
Clock High Time  
(3)  
tKL  
Clock Low Time  
3
4
(3)  
tKQ  
Clock Access Time  
—
2
—
2
(1)  
tKQX  
Clock High to Output Invalid  
Clock High to Output Low-Z  
Clock High to Output High-Z  
Output Enable to Output Valid  
Output Enable to Output Low-Z  
Output Disable to Output High-Z  
Address Setup Time  
Address Status Setup Time  
Chip Enable Setup Time  
Address Hold Time  
—
—
3.5  
3.5  
—
3.5  
—
—
—
—
—
—
—
—
(1,2)  
tKQLZ  
0
0
0
0
0
(1,2)  
tKQHZ  
2
2
2
2
2
(3)  
tOEQ  
—
0
—
0
—
0
—
0
—
0
(1,2)  
tOELZ  
—
3.5  
—
—
—
—
—
—
—
—
(1,2)  
tOEHZ  
—
2
—
2
—
2
—
2
—
4
(3)  
tAS  
(3)  
tSS  
2
2
2
2
4
(3)  
tCES  
2
2
2
2
4
(3)  
tAH  
0.5  
0.5  
0.5  
2
0.5  
0.5  
0.5  
2
0.5  
0.5  
0.5  
2
0.5  
0.5  
0.5  
2
1.5  
1.5  
1.5  
2
(3)  
tSH  
Address Status Hold Time  
Chip Enable Hold Time  
ZZ Standby  
(3)  
tCEH  
tZZS  
tZZREC  
ZZ Recovery  
2
2
2
2
2
Notes:  
1. Guaranteed but not 100% tested. This parameter is periodically sampled.  
2. Tested with load in Figure 2.  
3. Tested with load in Figure 1.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
13  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
SNOOZE AND RECOVERY CYCLE TIMING  
t
KC  
CLK  
ADSP  
ADSC  
t
KH  
tKL  
t
SS  
tSH  
ADV  
t
AS  
tAH  
A16-A0  
RD1  
RD2  
GW  
BWE  
BW4-BW1  
t
CES  
tCEH  
CE  
CE2  
CE2  
t
t
CES  
CES  
t
CEH  
CEH  
t
t
OEHZ  
t
OEQ  
OE  
t
OEQX  
t
OELZ  
High-Z  
High-Z  
DATAOUT  
1a  
t
KQLZ  
t
KQX  
KQHZ  
t
KQ  
t
DATAIN  
ZZ  
t
ZZS  
tZZREC  
Snooze with Data Retention  
Single Read  
Read  
14  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Frequency  
Order Part Number  
Package  
7.5  
IS61SF12832-7.5TQ  
IS61SF12832-7.5B  
TQFP  
PBGA  
8
IS61SF12832-8TQ  
IS61SF12832-8B  
TQFP  
PBGA  
8.5  
10  
12  
IS61SF12832-8.5TQ  
IS61SF12832-8.5B  
TQFP  
PBGA  
IS61SF12832-10TQ  
IS61SF12832-10B  
TQFP  
PBGA  
IS61SF12832-12TQ  
IS61SF12832-12B  
TQFP  
PBGA  
Industrial Range: –40°C to +85°C  
Frequency  
Order Part Number  
IS61SF12832-8TQI  
IS61SF12832-8.5TQI  
IS61SF12832-10TQI  
IS61SF12832-12TQI  
Package  
TQFP  
8
8.5  
10  
12  
TQFP  
TQFP  
TQFP  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
15  
Rev. A  
04/17/01  
IS61SF12832  
IS61SF12836  
®
ISSI  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Frequency  
Order Part Number  
Package  
7.5  
IS61SF12836-7.5TQ  
IS61SF12836-7.5B  
TQFP  
PBGA  
8
IS61SF12836-8TQ  
IS61SF12836-8B  
TQFP  
PBGA  
8.5  
10  
12  
IS61SF12836-8.5TQ  
IS61SF12836-8.5B  
TQFP  
PBGA  
IS61SF12836-10TQ  
IS61SF12836-10B  
TQFP  
PBGA  
IS61SF12836-12TQ  
IS61SF12836-12B  
TQFP  
PBGA  
Industrial Range: –40°C to +85°C  
Frequency  
Order Part Number  
IS61SF12836-8TQI  
IS61SF12836-8.5TQI  
IS61SF12836-10TQI  
IS61SF12836-12TQI  
Package  
TQFP  
8
8.5  
10  
12  
TQFP  
TQFP  
TQFP  
®
ISSI  
Integrated Silicon Solution, Inc.  
2231 Lawson Lane  
Santa Clara, CA 95054  
Tel: 1-800-379-4774  
Fax: (408) 588-0806  
E-mail: sales@issi.com  
www.issi.com  
16  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
04/17/01  

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