IS61SPD25632T-150TQ [ISSI]
Cache SRAM, 256KX32, 3.8ns, CMOS, PQFP100, TQFP-100;
| 型号： | IS61SPD25632T-150TQ |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 256KX32, 3.8ns, CMOS, PQFP100, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
®
IS61SPD51218T/D IS61LPD51218T/D ISSI
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
DOUBLE-CYCLE DESELECT STATIC RAM
PRELIMINARYINFORMATION
SEPTEMBER 2000
FEATURES
DESCRIPTION
The ISSI IS61SPD25632,IS61SPD25636,S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are
high-speed, low-powersynchronousstaticRAMsdesigned
toprovideaburstable, high-performance, secondarycachefor
thePentium™,680X0™,andPowerPC™microprocessors.
The IS61SPD25632 and IS61LPD25632 are organized as
262,144 words by 32 bits and the IS61SPD25636 and
IS61LPD25636 are organized as 262,144 words by 36 bits.
The IS61SPD51218 and IS61LPS51218are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
passthroughregisterscontrolledbyapositive-edge-triggered
single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
•
Threechipenableoptionforsimpledepthexpansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O For SPD
Write cycles are internally self-timed and are initiated by
therisingedgeoftheclockinput. Writecyclescanbefromone
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
• 2.5V I/O For LPD
• Double cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
LinearburstisachievedwhenthispinistiedLOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-166*
3.5
6
-150
3.8
-133
4
-5
5
Units
ns
Clock Access Time
Cycle Time
tKC
6.7
7.5
133
10
100
ns
Frequency
166
150
MHz
*This speed available only in SPD version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
1
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
BLOCK DIAGRAM
MODE
Q0
A0'
A1'
A0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
256Kx32; 256Kx36;
512Kx18
ADSC
ADSP
CLR
MEMORY ARRAY
A18-A0
(61SPD51218,
61LPD51218)
18/19
16/17
18/19
D
Q
A17-A0
(61SPD25632/36,
61LPD25632/36)
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
D
Q
GW
BWE
DQd
BYTE WRITE
REGISTERS
BWd
(x32/x36)
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BWc
(x32/x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BWb
(x32/x36/x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BWa
(x32/x36/x18)
CLK
(T, D) CE
(T, D) CE2
(T) CE2
4
32, 36,
or 18
INPUT
OUTPUT
D
Q
DQa - DQd
REGISTERS
REGISTERS
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
A6
CE2
A7
A4
A3
ADSP
ADSC
VCC
NC
A8
A16
A17
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
A9
NC
A2
A12
GND
GND
GND
BWb
GND
NC
A15
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
GND
GND
GND
BWc
GND
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
CE
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
ADV
GW
VCC
CLK
NC
VCC
ZZ
GND
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
K
L
GND
BWd
GND
GND
GND
MODE
A10
GND
BWa
GND
GND
GND
NC
M
N
P
R
T
BWE
A1
A0
A5
VCC
A11
NC
A13
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A14
NC
NC
ZZ
U
VCCQ
NC
NC
NC
VCCQ
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
CE, CE2
OE
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
GND
Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
BWa-BWd
BWE
ZZ
Snooze Enable
GNDQ
Isolated Output Buffer Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
3
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
GND
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
A2-A17
CLK
Synchronous Address Inputs
Synchronous Clock
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
GND
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
BWa-BWd
BWE
ZZ
Snooze Enable
GNDQ
Isolated Output Buffer Ground
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
A
B
C
D
E
F
VCCQ
NC
A6
A4
A3
ADSP
ADSC
VCC
NC
A8
A16
A17
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
CE2
A9
NC
A7
A2
A12
GND
GND
GND
BWb
GND
NC
A15
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
GND
GND
GND
BWc
GND
NC
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
CE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
ADV
GW
VCC
CLK
NC
NC
VCC
ZZ
GND
K
L
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
GND
BWd
GND
GND
GND
MODE
A10
GND
BWa
GND
GND
GND
NC
M
N
P
R
T
BWE
A1
A0
VCC
A11
NC
NC
NC
A14
NC
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VCCQ
NC
NC
NC
VCCQ
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
CE, CE2
OE
A2-A17
Synchronous Address Inputs
Synchronous Clock
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
CLK
ADSP
Synchronous Processor Address
Status
GND
Ground
ADSC
Synchronous Controller Address
Status
VCCQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
Snooze Enable
BWa-BWd
BWE
DQPa-DQPd Parity Data I/O
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
5
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
ZZ
GND
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
A2-A17
Synchronous Address Inputs
Synchronous Clock
DQa-DQd
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
Synchronous Processor Address
Status
GND
ADSC
Synchronous Controller Address
Status
VCCQ
IsolatedOutputBufferSupply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
Snooze Enable
BWa-BWd
BWE
DQPa-DQPd Parity Data I/O
Synchronous Byte Write Enable
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VCCQ
NC
A6
CE2
A7
A4
A3
ADSP
ADSC
VCC
NC
A8
A16
A18
VCCQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
NC
NC
NC
VCCQ
GND
NC
A9
NC
A2
A12
GND
GND
GND
GND
GND
NC
A15
NC
DQb1
NC
NC
GND
GND
GND
BWb
GND
NC
DQPa
NC
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
DQb2
NC
CE
DQa8
VCCQ
DQa6
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCCQ
NC
OE
DQa7
NC
G
H
J
DQb3
NC
ADV
GW
VCC
CLK
NC
DQb4
VCCQ
NC
DQa5
VCC
NC
VCC
ZZ
VCC
DQb5
NC
VCCQ
DQa4
NC
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
K
L
GND
GND
GND
GND
GND
MODE
A10
GND
BWa
GND
GND
GND
NC
DQb6
VCCQ
DQb8
NC
DQa3
NC
M
N
P
R
T
DQb7
NC
BWE
A1
VCCQ
NC
NC
DQa2
NC
GND
VCCQ
NC
NC
NC
GND
VCCQ
NC
NC
NC
DQPb
A5
A0
DQa1
NC
NC
VCC
NC
A13
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
A11
NC
A14
NC
A17
ZZ
U
VCCQ
NC
NC
NC
VCCQ
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
CE, CE2
OE
A2-A18
CLK
Synchronous Address Inputs
Synchronous Clock
DQa-DQb
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
ADSP
Synchronous Processor Address
Status
GND
Ground
ADSC
Synchronous Controller Address
Status
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWa-BWb
BWE
DQPa-DQPb ParityDataI/ODQPaisparityforDQa1-8;
DQPbisparityforDQb1-8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
7
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PIN CONFIGURATION
100-Pin TQFP (T Version)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
GND
VCCQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
A2-A18
CLK
Synchronous Address Inputs
Synchronous Clock
DQa-DQb
MODE
VCC
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
ADSP
Synchronous Processor Address
Status
GND
ADSC
Synchronous Controller Address
Status
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWa-BWb
BWE
DQPa-DQPb ParityDataI/ODQPaisparityforDQa1-8;
DQPbisparityforDQb1-8
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
TRUTHTABLE
Address
Operation
Used
CE
H
L
CE2
X
X
L
CE2 ADSP ADSC ADV WRITE OE
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
None
X
None
L
L
X
None
L
X
L
H
H
L
X
None
L
L
X
External
External
External
Next
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
Q
L
L
L
D
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
Q
H
L
High-Z
Q
H
X
X
High-Z
D
D
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
Read
Write Byte 1
Write All Bytes
Write All Bytes
L
X
X
X
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
9
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
°C
°C
W
TBIAS
TSTG
PD
Temperature Under Bias
Storage Temperature
Power Dissipation
–40 to +85
–55 to +150
1.6
IOUT
Output Current (per I/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.5
–0.5 to VCC + 0.5
VIN
Voltage Relative to GND for
V
for Address and Control Inputs
VCC
Voltage on Vcc Supply Relatiive to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periodsmayaffectreliability.
2. Thisdevicecontainscircuitytoprotecttheinputsagainstdamageduetohighstaticvoltagesor
electricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigherthan
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
VCCQ
Commercial
0°C to +70°C
3.3V, +10%, –5%
2.375–3.6V
Industrial
–40°C to +85°C
3.3V, +10%, –5%
2.375–3.6V
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
IOH = –2.0 mA, VCCQ = 2.5V
IOH = –4.0 mA, VCCQ = 3.3V
1.7
2.4
—
—
V
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 2.0 mA, VCCQ = 2.5V
IOL = 8.0 mA, VCCQ = 3.3V
—
—
0.7
0.4
V
V
VCCQ = 2.5V
VCCQ = 3.3V
1.7
2.0
VCCQ + 0.3
VCCQ + 0.3
V
V
VCCQ = 2.5V
VCCQ = 3.3V
–0.3
–0.3
0.7
0.8
V
V
(2)
Input Leakage Current
Output Leakage Current
GND ≤ VIN ≤ VCCQ
Com.
Ind.
–2
–5
2
5
µA
ILO
GND ≤ VOUT ≤ VCCQ, OE = VIH Com.
–2
–5
2
5
µA
Ind.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166*
Max.
-150
Max.
-133
Max.
-100
Max.
Symbol Parameter
TestConditions
Unit
ICC
ACOperating
SupplyCurrent
Device Selected,
Com.
Ind.
400
—
370
400
350
380
300
330
mA
mA
All Inputs = VIL or VIH
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB
StandbyCurrent
DeviceDeselected,
VCC = Max.,
Com.
Ind.
110
—
105
110
90
95
80
85
mA
mA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
*This speed available only in SPD version
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or ≥ Vcc – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
11
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V for 3.3V I/O
VCCQ/2V for 2.5V I/O
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω/1667 Ω
ZO = 50Ω
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Output
Buffer
OUTPUT
50Ω
351 Ω/1538 Ω
5 pF
Including
jig and
scope
1.5V for 3,3V I/O
VCCQ/2V for 2.5V I/O
Figure 1
Figure 2
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166*
Min.
-150
Min.
-133
Min.
-100
Symbol Parameter
Max.
166
—
Max.
150
—
Max.
133
—
—
—
4
Min.
—
10
3
Max.
100
—
—
—
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMAX
tKC
tKH
tKL
ClockFrequency
—
6
—
—
Cycle Time
6.7
2.5
2.5
—
7.5
2.8
2.8
—
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
2.3
2.3
—
—
—
—
—
3
tKQ
3.5
—
3.8
—
—
1.5
0
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup Time
1.5
0
1.5
0
1.5
0
—
—
4
—
—
5
(1,2)
(1,2)
tKQLZ
—
—
tKQHZ
tOEQ
—
3.5
3.5
—
—
3.8
3.8
—
—
—
—
0
—
—
—
4
5
(1,2)
tOELZ
tOEHZ
tAS
0
0
0
—
4
—
5
(1,2)
—
3.2
—
—
3.8
—
—
—
2
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
—
—
2
tWS
—
—
2
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
—
—
2
—
—
2
—
—
0.5
0.5
0.5
0.5
0.5
tSH
Address Status Hold Time
Write Hold Time
—
—
tWH
tCEH
tAVH
—
—
Chip Enable Hold Time
Address Advance Hold Time
—
—
—
—
*This speed available only in SPD version
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
13
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
Address
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
BWx
WH
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166*
Min.
-150
-133
-100
Min.
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
6.7
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
7.5
2.8
2.8
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKC
Cycle Time
6
10
3
tKH
Clock High Pulse Width
Clock Low Pulse Width
Address Setup Time
Address Status Setup Time
Write Setup Time
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
tKL
3
tAS
2
tSS
2
tWS
tDS
2
Data In Setup Time
2
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
2
2
0.5
0.5
0.5
0.5
0.5
0.5
tSH
Address Status Hold Time
Data In Hold Time
tDH
tWH
tCEH
tAVH
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
*This speed available only in SPD version
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
15
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
ZZ ≥ Vih
Min.
—
—
2
Max.
30
2
Unit
mA
ISB2
tPDS
tPUS
tZZI
Current during SNOOZE MODE
ZZ active to input ignored
cycle
cycle
cycle
ns
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
—
2
—
0
tRZZI
—
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
17
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
PART IDENTIFICATION
6 1 X P D X X X X X X - X X X X X X
Rating
Commercial
I - Industrial
Package
TQ - TQFP
B - PBGA
Speed
166 - 166 MHz
150 - 150 MHz
133 - 133 MHz
5 - 100 MHz
T - Three chip selects
D - Two chip selects
Density 25632 - 256K x 32
25636 - 256K x 36
51218 - 512K x 18
D - double-cycle dedelect
S - single-cycle deselect
SP - 3.3V I/O synchronous pipeline
LP - 2.5V I/O synchronous pipeline
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
Speed
Order Part Number
Package
166 MHz
IS61SPD25632T-166TQ
IS61SPD25632D-166TQ
IS61SPD25632D-166B
TQFP
TQFP
PBGA
166 MHz
IS61SPD25636T-166TQ
IS61SPD25636D-166TQ
IS61SPD25636D-166B
TQFP
TQFP
PBGA
150 MHz
133 MHz
100 MHz
IS61SPD25632T-150TQ
IS61SPD25632D-150TQ
IS61SPD25632D-150B
TQFP
TQFP
PBGA
150 MHz
133 MHz
100 MHz
IS61SPD25636T-150TQ
IS61SPD25636D-150TQ
IS61SPD25636D-150B
TQFP
TQFP
PBGA
IS61SPD25632T-133TQ
IS61SPD25632D-133TQ
IS61SPD25632D-133B
TQFP
TQFP
PBGA
IS61SPD25636T-133TQ
IS61SPD25636D-133TQ
IS61SPD25636D-133B
TQFP
TQFP
PBGA
IS61SPD25632T-5TQ
IS61SPD25632D-5TQ
IS61SPD25632D-5B
TQFP
TQFP
PBGA
IS61SPD25636T-5TQ
IS61SPD25636D-5TQ
IS61SPD25636D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
Speed
Order Part Number
Package
150 MHz
IS61SPD25632T-150TQI
IS61SPD25632D-150TQI
TQFP
TQFP
150 MHz
IS61SPD25636T-150TQI
IS61SPD25636D-150TQI
TQFP
TQFP
133 MHz
100 MHz
IS61SPD25632T-133TQI
IS61SPD25632D-133TQI
TQFP
TQFP
133 MHz
100 MHz
IS61SPD25636T-133TQI
IS61SPD25636D-133TQI
TQFP
TQFP
IS61SPD25632T-5TQI
IS61SPD25632D-5TQI
TQFP
TQFP
IS61SPD25636T-5TQI
IS61SPD25636D-5TQI
TQFP
TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
19
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
166 MHz
IS61SPD51218T-166TQ
IS61SPD51218D-166TQ
IS61SPD51218D-166B
TQFP
TQFP
PBGA
150 MHz
133 MHz
100 MHz
IS61SPD51218T-150TQ
IS61SPD51218D-150TQ
IS61SPD51218D-150B
TQFP
TQFP
PBGA
IS61SPD51218T-133TQ
IS61SPD51218D-133TQ
IS61SPD51218D-133B
TQFP
TQFP
PBGA
IS61SPD51218T-5TQ
IS61SPD51218D-5TQ
IS61SPD51218D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
150 MHz
IS61SPD51218T-150TQI
IS61SPD51218D-150TQI
TQFP
TQFP
133 MHz
100 MHz
IS61SPD51218T-133TQI
IS61SPD51218D-133TQI
TQFP
TQFP
IS61SPD51218T-5TQI
IS61SPD51218D-5TQI
TQFP
TQFP
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
Speed
Order Part Number
Package
150 MHz
IS61LPD25632T-150TQ
IS61LPD25632D-150TQ
IS61LPD25632D-150B
TQFP
TQFP
PBGA
150 MHz
IS61LPD25636T-150TQ
IS61LPD25636D-150TQ
IS61LPD25636D-150B
TQFP
TQFP
PBGA
133 MHz
100 MHz
IS61LPD25632T-133TQ
IS61LPD25632D-133TQ
IS61LPD25632D-133B
TQFP
TQFP
PBGA
133 MHz
100 MHz
IS61LPD25636T-133TQ
IS61LPD25636D-133TQ
IS61LPD25636D-133B
TQFP
TQFP
PBGA
IS61LPD25632T-5TQ
IS61LPD25632D-5TQ
IS61LPD25632D-5B
TQFP
TQFP
PBGA
IS61LPD25636T-5TQ
IS61LPD25636D-5TQ
IS61LPD25636D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
Speed
Order Part Number
Package
133 MHz
IS61LPD25632T-133TQI
IS61LPD25632D-133TQI
TQFP
TQFP
133 MHz
IS61LPD25636T-133TQI
IS61LPD25636D-133TQI
TQFP
TQFP
100 MHz
IS61LPD25632T-5TQI
IS61LPD25632D-5TQI
TQFP
TQFP
100 MHz
IS61LPD25636T-5TQI
IS61LPD25636D-5TQI
TQFP
TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
21
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
150 MHz
IS61LPD51218T-150TQ
IS61LPD51218D-150TQ
IS61LPD51218D-150B
TQFP
TQFP
PBGA
133 MHz
100 MHz
IS61LPD51218T-133TQ
IS61LPD51218D-133TQ
IS61LPD51218D-133B
TQFP
TQFP
PBGA
IS61LPD51218T-5TQ
IS61LPD51218D-5TQ
IS61LPD51218D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
133 MHz
IS61LPD51218T-133TQI
IS61LPD51218D-133TQI
TQFP
TQFP
100 MHz
IS61LPD51218T-5TQI
IS61LPD51218D-5TQI
TQFP
TQFP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
相关型号：
IS61SPD25632T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
ISSI
IS61SPD25636T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
ISSI
IS61SPD51218T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
ISSI
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