IS61WV51216ALL [ISSI]
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY; 512K ×16高速异步的CMOS静态RAM与3.3V电源
| 型号： | IS61WV51216ALL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总20页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
OCTOBER2009
FEATURES
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
DESCRIPTION
The ISSI IS61WV51216ALL/BLL and IS64WV51216BLL
are high-speed, 8M-bit static RAMs organized as 512K
words by 16 bits. It is fabricated using ISSI's high-perform-
anceCMOStechnology.Thishighlyreliableprocesscoupled
withinnovativecircuitdesigntechniques,yieldshigh-perfor-
mance and low power consumption devices.
• Easy memory expansion with CE and OE op-
tions
• CE power-down
• Fully static operation: no clock or refresh
required
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• TTL compatible inputs and outputs
• Single power supply
VDD 1.65V to 2.2V (IS61WV51216ALL)
speed = 20ns for VDD 1.65V to 2.2V
VDD 2.4V to 3.6V (IS61/64WV51216BLL)
speed = 10ns for VDD 2.4V to 3.6V
speed = 8ns for VDD 3.3V + 5%
• Packages available:
The device is packaged in the JEDEC standard 44-pin
TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
–
48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
FUNCTIONAL BLOCK DIAGRAM
512K x 16
MEMORY ARRAY
A0-A18
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
48-pin mini BGA (9mmx11mm)
1
2
3
4
5
6
A0
A3
A1
A4
A2
LB
I/O
OE
UB
NC
I/O
A
B
C
D
E
F
CE
8
0
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
GND
VDD
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
VDD
GND
11
3
4
5
A16
A15
A13
A10
12
I/O
14
I/O
I/O
6
13
NC
A8
I/O
15
WE
I/O
7
G
H
A18
A9
A11
NC
PIN DESCRIPTIONS
A0-A18
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
OE
WE
LB
UB
NC
VDD
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
A0
A1
A2
A3
A4
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
2
3
4
5
CE
6
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
7
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
A18
A14
A13
A12
A11
A10
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A6
A7
A8
A9
PIN DESCRIPTIONS
A0-A18
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
UB
NC
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
ISB1, ISB2
ICC
Not Selected
OutputDisabled
X
H
X
X
X
High-Z
High-Z
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
VDD
Terminal Voltage with Respect to GND
VDD Relates to GND
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
V
V
°C
W
TSTG
PT
StorageTemperature
PowerDissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
OPERATING RANGE (VDD) (IS61WV51216ALL)
Range
AmbientTemperature
0°C to +70°C
VDD (20 nS)
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Commercial
Industrial
Automotive
–40°Cto+85°C
–40°Cto+125°C
OPERATING RANGE (VDD) (IS61WV51216BLL)(1)
Range
Commercial
Industrial
Note:
AmbientTemperature
0°C to +70°C
VDD (8 nS)
3.3V + 5%
3.3V + 5%
VDD (10 nS)
2.4V-3.6V
2.4V-3.6V
–40°Cto+85°C
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of
3.3V + 5%, the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV51216BLL)
Range
AmbientTemperature
VDD (10 nS)
Automotive
–40°Cto+125°C
2.4V-3.6V
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–1
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL (min.)=–2.0VAC(pulsewidth<10ns).Not100%tested.
IH(max.)=VDD +0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth<10 ns).Not100%tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter
TestConditions
Min.
1.8
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 1.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2.0
–0.3
–1
VDD + 0.3
V
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL(min.)=–2.0VAC(pulsewidth<10 ns).Not100%tested.
IH(max.)=VDD +0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth<10 ns).Not100%tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter
TestConditions
IOH = -0.1 mA
IOL = 0.1 mA
VDD
Min.
1.4
—
Max.
Unit
V
VOH
VOL
VIH
OutputHIGHVoltage
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakage
0.2
V
1.4
–0.2
–1
VDD + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Notes:
1. VIL (min.)= –0.3VDC; VIL (min.)= –2.0VAC(pulsewidth<10ns).Not100%tested.
VIH(max.)= VDD+0.3VDC;VIH(max.)= VDD+2.0VAC(pulsewidth<10ns).Not100%tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Unit
Unit
Unit
(2.4V-3.6V)
(3.3V + 5%)
(1.65V-2.2V)
Input Pulse Level
Input Rise and Fall Times
0.4V to VDD-0.3V
1.5ns
0.4V to VDD-0.3V
1.5ns
0.4V to VDD-0.2V
1.5ns
Input and Output Timing
VDD/2
VDD/2 + 0.05
VDD/2
andReferenceLevel(VRef)
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
-10
-20
Symbol Parameter
Test Conditions
Min.
Max.
Min. Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
—
110
115
—
—
—
—
90
95
140
—
—
—
50
60
100
mA
Supply Current
IOUT = 0 mA, f = fMAX
Auto.
typ.(2)
60
ICC1
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
85
90
—
—
—
—
85
90
110
—
—
—
45
55
90
mA
mA
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
30
35
—
—
—
—
30
35
70
—
—
—
30
35
70
ISB2
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VDD = Max.,
Com.
Ind.
—
—
—
20
25
—
—
—
—
20
25
60
—
—
—
15
20
60
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
typ.(2)
4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACE
DOE
ReadCycleTime
8
—
2.5
—
—
—
0
—
8
10
—
2.5
—
—
—
0
—
10
—
10
6.5
4
t
AddressAccessTime
OutputHoldTime
CEAccessTime
t
—
8
t
t
OEAccessTime
5.5
3
(2)
tHZOE
OEtoHigh-ZOutput
OEtoLow-ZOutput
CEtoHigh-ZOutput
CEtoLow-ZOutput
LB,UBAccessTime
LB,UBtoHigh-ZOutput
LB,UBtoLow-ZOutput
PowerUpTime
(2)
tLZOE
—
3
—
4
(2
t
HZCE
0
0
(2)
tLZCE
3
—
5.5
3
3
—
6.5
3
t
BA
—
0
—
0
(2)
tHZB
(2)
tLZB
0
—
—
8
0
—
—
10
tPU
0
0
tPD
PowerDownTime
—
—
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vandoutputloading
specifiedinFigure1.
2. TestedwiththeloadinFigure2. Transitionismeasured 500mVfromsteady-statevoltage.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol
tRC
Parameter
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
20
—
2.5
—
—
0
—
20
—
20
8
tAA
Address Access Time
Output Hold Time
tOHA
tACE
CE Access Time
tDOE
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
8
(2)
tLZOE
0
—
8
(2
tHZCE
0
(2)
tLZCE
3
—
8
tBA
—
0
tHZB
8
tLZB
0
—
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
CE
t
HZOE
t
DOE
t
t
LZOE
ACE
t
HZCE
t
LZCE
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Symbol
Parameter
Min.
8
Max.
—
Min.
10
8
Max.
—
Unit
ns
t
WC
SCE
AW
WriteCycleTime
CEtoWriteEnd
t
6.5
6.5
—
—
ns
t
AddressSetupTime
toWriteEnd
—
8
—
ns
t
HA
SA
PWB
PWE
PWE
SD
HD
HZWE
AddressHoldfromWriteEnd
AddressSetupTime
0
0
—
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
LB,UBValidtoEndofWrite
WEPulseWidth
6.5
6.5
8.0
5
8
t
1
8
t
2
WEPulseWidth (OE=LOW)
DataSetuptoWriteEnd
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
10
6
t
t
0
0
(2)
(2)
t
—
2
—
2
tLZWE
—
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vandoutputloading
specifiedinFigure1.
2. TestedwiththeloadinFigure2. Transitionismeasured 500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUBorLB,andWELOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,but
anyonecangoinactivetoterminatetheWrite. TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthat
terminatesthewrite.Shadedareaproductindevelopment
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns
Symbol
tWC
Parameter
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
20
12
12
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWB
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
12
12
17
9
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
(3)
tHZWE
—
3
(3)
tLZWE
—
Notes:
1. Test conditions for IS61WV51216ALL/BLL assume signal transition times of 1.5ns or less, timing
reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in
Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals
must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The
Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write.
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13
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC WAVEFORMS
WRITE CYCLE NO. 2(WE Controlled. OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC WAVEFORMS
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internalWritetimeisdefinedbytheoverlapofCE=LOW,UBand/orLB=LOW,andWE=LOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
anycanbedeassertedtoterminatetheWrite.The SD,and HDtimingisreferencedtotherisingorfallingedgeofthesignalthatterminatestheWrite.
t
SA,
t
HA,
t
t
2. TestedwithOEHIGHforaminimumof4nsbeforeWE=LOWtoplacetheI/OinaHIGH-Zstate.
3. WEmaybeheldLOWacrossmanyaddresscyclesandtheLB,UBpinscanbeusedtocontroltheWritefunction.
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CE ≥ VDD – 0.2V
1.2
3.6
IDR
Ind.
Auto.
—
—
20
50
mA
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
—
ns
ns
tRC
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10(81)
IS61WV51216BLL-10MI
48 mini BGA (9mm x 11mm)
IS61WV51216BLL-10MLI 48 mini BGA (9mm x 11mm), Lead-free
IS61WV51216BLL-10TI
IS61WV51216BLL-10TLI
TSOP (Type II)
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V - 3.6V
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed(ns)
Order Part No.
Package
20
IS61WV51216ALL-20MI
IS61WV51216ALL-20TI
48 mini BGA (9mm x 11mm)
TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10
IS64WV51216BLL-10MA3
IS64WV51216BLL-10MLA3
IS64WV51216BLL-10CTA3
IS64WV51216BLL-10CTLA3
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II), Copper Leadframe
TSOP(TypeII), Lead-free, CopperLeadframe
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. F
10/01/09
IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09
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