IS62C1024AL-35QLI-TR [ISSI]
IC SRAM 1M PARALLEL 32SOP;
| 型号： | IS62C1024AL-35QLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 1M PARALLEL 32SOP 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62C1024AL
IS65C1024AL
128K x 8 LOW POWER CMOS
STATIC RAM
DECEMBER 2017
FEATURES
DESCRIPTION
The ISSI IS62C1024AL/IS65C1024AL is a low power,
131,072-word by 8-bit CMOS static RAM. It is fabricated
using high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
•ꢀ High-speedꢀaccessꢀtime:ꢀ35,ꢀ45ꢀnsꢀ
• Low active power: 100 mW (typical)
• Low standby power: 20 µW (typical) CMOS
standby
•ꢀ OutputꢀEnableꢀ(OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
WhenCE1isHIGHorCE2isLOW(deselected),thedevice
assumes a standby mode at which the power dissipation
can be reduced by using CMOS input levels.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ
required
•ꢀ TTLꢀcompatibleꢀinputsꢀandꢀoutputs
•ꢀ Singleꢀ5Vꢀ(±10%)ꢀpowerꢀsupply
Easy memory expansion is provided by using two Chip
Enableinputs,CE1andCE2.TheactiveLOWWriteEnable
(WE) controls both writing and reading of the memory.
•ꢀ Commercial,ꢀIndustrial,ꢀandꢀAutomotiveꢀtem-
perature ranges available
•ꢀ StandardꢀPinꢀConfiguration:
—
32-pin SOP/ 32-pin TSOP (Type 1)
•ꢀ Leadꢀfreeꢀavailable
FUNCTIONAL BLOCK DIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE1
CONTROL
CIRCUIT
CE2
OE
WE
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP
32-Pin TSOP (Type 1)
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A11
A9
A8
A13
WE
CE2
A15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A15
CE2
WE
A13
A8
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
4
5
A6
6
A5
7
A9
A4
8
A11
OE
VDD
A3
9
NC
A16
A14
A12
A7
A6
A5
A4
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A1
A2
A3
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1
CE2
OE
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
OPERATING RANGE (IS62C1024AL)
Range
Commercialꢀ 0°Cꢀtoꢀ+70°Cꢀ
Industrialꢀ -40°Cꢀtoꢀ+85°Cꢀ
Ambient Temperature
Vdd
5Vꢀ±ꢀ10%
5Vꢀ±ꢀ10%
WE
I/O0-I/O7Input/Output
ꢀ
VDD
Power
GND
Ground
OPERATING RANGE (IS65C1024AL)
Range
Ambient Temperature
Vdd
Automotiveꢀ -40°Cꢀtoꢀ+125°Cꢀ
5Vꢀ±ꢀ10%
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation
Vdd Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
Isb1, Isb2
Isb1, Isb2
Output Disabled
Read
Write
H
H
L
L
L
L
H
H
H
H
L
X
High-Z
Dout
DIn
Icc
Icc
Icc
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
tstg
Pt
Parameter
Value
–0.5ꢀtoꢀ+7.0ꢀ
–65ꢀtoꢀ+125ꢀ
1.0
Unit
V
°C
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
Power Dissipation
W
Iout
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
CAPACITANCE(1,2)
Symbol
cIn
Parameter
Conditions
VIn = 0V
Max.
6ꢀ
Unit
pF
Input Capacitance
Output Capacitance
cout
Vout = 0V
8ꢀ
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVDDꢀ=ꢀ5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Options
Min.
2.4ꢀ
—ꢀ
2.2ꢀ
-0.5ꢀ
-1
-2
-5
Max.
Unit
V
V
V
V
Voh
Vol
VIh
VIl
IlI
OutputꢀHIGHꢀVoltageꢀ
VDD = Min., Ioh = –1.0ꢀmAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
0.4ꢀ
VDD + 0.5
0.8ꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)
Input Leakage
VDD = Min., Iol = 2.1ꢀmAꢀ
ꢀ
ꢀ
GND ≤ VIn ≤ VDD
Com.
Ind.
Auto.
1
2
5
µA
Ilo
Output Leakage
GND ≤ Vout ≤ VDD
CE1 = VIh, or
CE2 = VIl, or OE = VIh or
WE = VIl
Com.
Ind.
Auto.
-1
-2
-5
1
2
5
µA
Note:
1.ꢀVIlꢀ(min.)ꢀ=ꢀ-0.3VꢀDC;ꢀVIlꢀ(min.)ꢀ=ꢀ-2.0VꢀACꢀ(pulseꢀwidthꢀ-2.0ꢀns).ꢀNotꢀ100%ꢀtested.
VIhꢀ(max.)ꢀ=ꢀVDDꢀ+ꢀ0.3VꢀDC;ꢀVIhꢀ(max.)ꢀ=ꢀVDDꢀ+ꢀ2.0VꢀACꢀ(pulseꢀwidthꢀ-2.0ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
IS62C1024AL/IS65C1024AL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35 ns
Min. Max.
-45 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
Icc
Average operating
Current
CE1 = VIl, ce2 = VIh
Com.
Ind.
—
—
25
30
mA
VIn = VIh or VIl,
I I/o= 0 mA, f=0
Auto.
—
—
35
40
Icc1
V
DD Dynamic Operating VDD = Max., CE1 = VIl
Com.
Ind.
—
—
30
35
mA
Supply Current
I
V
out = 0 mA, f = fmax
In = VIh or VIl
CE2 = VIh
Auto.
typ.(2)
—
20
I
I
sb
1
2
TTL Standby Current
(TTL Inputs)
V
DD = Max.,
Com.
Ind.
Auto.
—
—
1
1.5
mA
µA
V
In = VIh or VIl, CE1 ≥ VIh
,
or CE2 ≤ꢀVIl, f = 0
—
—
2
sb
CMOS Standby
Current (CMOS Inputs) CE1 ≥ VDD – 0.2V, or
V
DD = Max.,
Com.
Ind.
—
—
5
10
ce2 ≤ 0.2V, VIn ≥ VDD – 0.2V, Auto.
or VIn ≤ Vss + 0.2V, f = 0
45
typ.(2)
—
4
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.ꢀTypicalꢀValuesꢀareꢀmeasuredꢀatꢀVDDꢀ=ꢀ5V,ꢀTa = 25oCꢀandꢀnotꢀ100%ꢀtested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-35 ns
-45 ns
Symbol
trc
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
35
—
3
—
35
—
35
35
10
—
10
—
—
10
45
—
3
—
45
—
45
45
20
—
15
—
—
15
taa
Address Access Time
Output Hold Time
toha
tace1
tace2
tDoe
CE1 Access Time
CE2 Access Time
OE Access Time
—
—
—
3
—
—
—
5
(2)
tlzoe
OE to Low-Z Output
OE to High-Z Output
CE1 to Low-Z Output
CE2 to Low-Z Output
CE1 or CE2 to High-Z Output
(2)
thzoe
0
0
tlzce1(2)
tlzce2(2)
3
5
3
5
(2)
thzce
0
0
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.6ꢀ
toꢀ2.4VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1a.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ1b.ꢀꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0.6Vꢀtoꢀ2.4V
5ꢀns
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
1.5V
and Reference Level
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1aꢀandꢀ1b
AC TEST LOADS
1838 Ω
1838 Ω
5V
5V
OUTPUT
OUTPUT
993 Ω
993 Ω
100 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figureꢀ1a.
Figureꢀ1b.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
t
OHA
tOHA
DATA VALID
DOUT
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
tHZOE
t
DOE
CE1
t
LZOE
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIl, CE2 = VIh.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-35 ns
-45 ns
Symbol
twc
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
35
25
25
25
0
—
—
—
—
—
—
—
—
—
10
—
45
35
35
35
0
—
—
—
—
—
—
—
—
—
15
—
tsce1
tsce2
taw
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
tha
tsa
0
0
(4)
tPwe
25
20
0
35
25
0
tsD
thD
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
(2)
thzwe
—
3
—
5
(2)
tlzwe
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.6ꢀtoꢀ2.4Vꢀ
andꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1a.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ1b.ꢀꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
tSCE1
tSCE2
CE2
t
AW
(4)
tPWE
WE
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATA-IN VALID
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
tSA
t
HA
tSCE1
CE1
tSCE2
CE2
t
AW
t
(4)
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
SD
DATA-IN VALID
DATA UNDEFINED
t
HD
t
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIh.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
ꢀ ꢀ VDr DDꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
Test Condition
Min.
Typ.
Max. Unit
ꢀ
V
SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
2.0ꢀ
ꢀ
5.5ꢀ
V
IDr
ꢀ
V
DDꢀ=ꢀ2.0V,ꢀCE1 ≥ꢀVDDꢀ–ꢀ0.2Vꢀ
Com.ꢀ
Ind.
—ꢀ
—
—ꢀ
—
5ꢀ
µA
or CE2 ≤ 0.2V
10
VIn ≥ VDD – 0.2V, or VIn
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
≤
Vss + 0.2V
Auto.
—
0
—
45
—
—
t
t
sDr
rDr
ns
ns
trc
Note:
ꢀ 1.ꢀTypicalꢀValuesꢀareꢀmeasuredꢀatꢀVDDꢀ=ꢀ5V,ꢀT
= 25oCꢀandꢀnotꢀ100%ꢀtested.
a
DATA RETENTION WAVEFORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE1 ≥ VDD - 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
VDD
CE2
4.5V
2.2V
t
t
RDR
SDR
V
DR
CE2 ≤ 0.2V
0.4V
GND
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
35
35
IS62C1024AL-35QLI
IS62C1024AL-35TLI
Plastic SOP, Lead-free
TSOP, Type 1, Lead-free
ORDERING INFORMATION: IS65C1024AL
Automotive Range: -40°C to +125°C
Speed (ns)
Order Part No.
Package
45
45
IS65C1024AL-45QLA3 Plastic SOP, Lead-free
IS65C1024AL-45TLA3 TSOP, Type 1, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. H1
12/01/2017
IS62C1024AL
IS65C1024AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. H1
12/01/2017
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