IS62C256 [ISSI]
32K x 8 LOW POWER CMOS STATIC RAM; 32K ×8低功耗CMOS静态RAM
| 型号： | IS62C256 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ISSI
IS62C256
32K x 8 LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-
performance, low power CMOS technology.
• Access time: 45, 70 ns
• Low active power: 200 mW (typical)
• Low standby power
WhenCSisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down to
250 µW (typical) at CMOS input levels.
— 250 µW (typical) CMOS standby
— 28 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using an active LOW
ChipSelect(CS)inputandanactiveLOWOutputEnable(OE)
input. TheactiveLOWWriteEnable(WE)controlsbothwriting
and reading of the memory.
• TTL compatible inputs and outputs
• Single 5V power supply
The IS62C256 is pin compatible with other 32K x 8 SRAMs in
plastic SOP or TSOP (Type I) package.
FUNCTIONAL BLOCK DIAGRAM
32K X 8
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CS
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
1
®
IS62C256
ISSI
PIN CONFIGURATION
28-Pin TSOP
PIN CONFIGURATION
28-Pin SOP
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CS
2
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
A8
A6
4
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A5
5
A9
A4
6
A11
OE
A3
7
2
A2
8
A10
CS
3
A1
9
4
5
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
6
A1
A2
I/O0
I/O1
I/O2
GND
7
8
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE
X
CS
H
OE I/O Operation Vcc Current
A0-A14
CS
Address Inputs
Not Selected
(Power-down)
X
High-Z
ISB1, ISB2
Chip Select Input
OE
Output Enable Input
Write Enable Input
Input/Output
Power
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
I/O0-I/O7
Vcc
Write
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–55 to +125
–65 to +150
0.5
V
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
®
IS62C256
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
5V ± 10%
5V ± 10%
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.2
VCC + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–2
–10
2
10
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC,
Outputs Disabled
Com.
Ind.
–2
–10
2
10
µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45 ns
Min. Max.
-70 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC1
Vcc Operating
Supply Current
VCC = Max., CS = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
60
70
—
—
60
70
mA
ICC2
ISB1
Vcc Dynamic Operating
Supply Current
VCC = Max., CS = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
70
80
—
—
65
75
mA
mA
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CS ≥ VIH, f = 0
Com.
Ind.
—
—
5
10
—
—
5
10
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
0.5
1.0
—
—
0.5
1.0
mA
CS ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
3
®
IS62C256
ISSI
DATA RETENTION CHARACTERISTICS
Symbol
VDR
Parameter
Test Conditions
Min.
2.0
—
Max.
—
Units
V
VCC for retention of data
Data retention current
Data retention current
IDR1
VDR = 3.0V, TA = 0°C to +25°C
VDR = 3.0V, TA = 0°C to +70°C
200
200
µA
IDR2
—
µA
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45 ns
-70 ns
Min.
Symbol Parameter
Min.
Max.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
45
—
2
—
70
—
2
tAA
Address Access Time
Output Hold Time
CS Access Time
45
—
70
—
tOHA
tACS
tDOE
tLZOE
—
—
0
45
25
—
—
—
0
70
35
—
OE Access Time
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CS to Low-Z Output
CS to High-Z Output
CS to Power-Up
tHZOE
0
20
—
0
25
—
(2)
tLZCS
tHZCS
3
3
(2)
0
20
—
0
25
—
(3)
tPU
0
0
(3)
tPD
CS to Power-Down
—
30
—
50
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
100 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1.
Figure 2.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
®
IS62C256
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CS
t
HZCS
t
LZCS
HIGH-Z
DOUT
DATA VALID
CS_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = VIL.
3. Address is valid prior to or coincident with CS LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
5
®
IS62C256
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-45 ns
-70ns
Min.
Symbol Parameter
Min.
Max.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCS
tAW
tHA
Write Cycle Time
45
35
25
0
—
70
60
60
0
CS to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
—
—
tSA
0
—
0
—
(4)
tPWE
tSD
WE Pulse Width
25
20
0
—
55
30
0
—
Data Setup to Write End
Data Hold from Write End
—
—
tHD
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(
CS Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCS
ADDRESS
CS
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
®
IS62C256
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 2(
OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CS
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR2.eps
WRITE CYCLE NO. 3(
OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CS
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
7
®
IS62C256
ISSI
ORDERING INFORMATION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commerical Range: 0°C to +70°C
Speed
Speed
(ns)
Order Part No.
Package
(ns)
Order Part No.
Package
45
IS62C256-45TI
IS62C256-45UI
TSOP
Plastic SOP
45
IS62C256-45T
IS62C256-45U
TSOP
Plastic SOP
70
IS62C256-70TI
IS62C256-70UI
TSOP
Plastic SOP
70
IS62C256-70T
IS62C256-70U
TSOP
Plastic SOP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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