IS62LV2568LL-70T [ISSI]

256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM; 256K ×8低功耗和低Vcc的CMOS静态RAM
IS62LV2568LL-70T
型号: IS62LV2568LL-70T
厂家: INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述:

256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
256K ×8低功耗和低Vcc的CMOS静态RAM

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中文:  中文翻译
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®
IS62LV2568LL  
256K x 8 LOW POWER and LOW Vcc  
CMOS STATIC RAM  
ISSI  
APRIL 2000  
FEATURES  
DESCRIPTION  
• Access times of 70 and 85 ns  
The ISSI IS62LV2568LL is a low voltage, 262,144 words  
CMOS low power operation:  
— 120 mW (typical) operating  
— 6 µW (typical) standby  
by 8 bits, CMOS SRAM. It is fabricated using ISSI’s low  
voltage, six transistor (6T), CMOS technology. The device is  
targeted to satisfy the demands of the state-of-the-art  
technologies such as cell phones and pagers.  
• Low data retention voltage: 2V (min.)  
When CE is HIGH (deselected), the device assumes a  
standbymodeatwhichthepowerdissipationcanbereduced  
down with CMOS input levels. Additionally, easy memory  
expansion is provided by using Chip Enable and Output  
Enable inputs, CE and OE. The active LOW Write Enable (WE)  
controls both writing and reading of the memory.  
• Output Enable (OE) and two Chip Enable  
(CE1 and CE2) inputs for ease in applications  
• TTL compatible inputs and outputs  
• Fully static operation:  
— No clock or refresh required  
The IS62LV2568LL is available in 32-pin TSOP (Type I),  
STSOP (Type I), and 36-pin mini BGA.  
• Single 2.5V to 3.0V power supply  
• Available in 32-pin TSOP (Type I), STSOP (Type I),  
and 36-pin mini BGA  
FUNCTIONAL BLOCK DIAGRAM  
256K x 8  
MEMORY ARRAY  
A0-A17  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE1  
CE2  
CONTROL  
CIRCUIT  
OE  
WE  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
PIN CONFIGURATION  
36-pin mini BGA (B)  
PIN DESCRIPTIONS  
A0-A17  
CE1  
Address Inputs  
1
2
3
4
5
6
Chip Enable 1 Input  
Chip Enable 2 Input  
Output Enable Input  
Write Enable Input  
Input/Output  
CE2  
OE  
WE  
A
B
C
D
E
F
A0  
I/O4  
I/O5  
GND  
Vcc  
I/O6  
I/O7  
A9  
A1  
A2  
CE2  
WE  
NC  
A3  
A4  
A5  
A6  
A7  
A8  
I/O0  
I/O1  
Vcc  
I/O0-I/O7  
NC  
No Connection  
Power  
Vcc  
GND  
Ground  
GND  
I/O2  
I/O3  
A14  
NC  
CE1  
A11  
A17  
A16  
A12  
OE  
A15  
A13  
G
H
A10  
32-Pin TSOP (Type I), STSOP (Type I)  
A11  
A9  
A8  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
GND  
I/O2  
I/O1  
I/O0  
A0  
A13  
WE  
CE2  
A15  
VCC  
A17  
A16  
A14  
A12  
A7  
9
10  
11  
12  
13  
14  
15  
16  
A6  
A5  
A4  
A1  
A2  
A3  
2
Integrated Silicon Solution, Inc. 1-800-379-4774  
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
TRUTH TABLE  
Mode  
WE  
CE1 CE2 OE  
I/O Operation  
Vcc Current  
Not Selected  
(Power-down)  
X
X
H
X
X
L
X
X
High-Z  
High-Z  
ISB1, ISB2  
ISB1, ISB2  
Output Disabled H  
L
L
L
H
H
H
H
L
X
High-Z  
DOUT  
DIN  
ICC  
ICC  
ICC  
Read  
Write  
H
L
OPERATING RANGE  
Range  
Ambient Temperature  
VCC  
Commercial  
0°C to +70°C  
2.5V to 3.0V  
Industrial  
40°C to +85°C  
2.5V to 3.0V  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameter  
Value  
Unit  
VTERM  
VCC  
Terminal Voltage with Respect to GND  
Vcc related to GND  
Temperature Under Bias  
Storage Temperature  
0.5 to Vcc + 0.5  
0.3 to +4.6  
40 to +85  
65 to +150  
0.7  
V
V
°C  
°C  
W
TBIAS  
TSTG  
PT  
Power Dissipation  
Note:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of  
this specification is not implied. Exposure to absolute maximum rating conditions for  
extendedperiodsmayaffectreliability.  
CAPACITANCE(1,2)  
Symbol  
CIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
Unit  
pF  
Input Capacitance  
Output Capacitance  
6
8
COUT  
VOUT = 0V  
pF  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.  
Integrated Silicon Solution, Inc. 1-800-379-4774  
3
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)  
Symbol Parameter  
Test Conditions  
Min.  
Max.  
Unit  
VOH  
VOL  
VIH  
VIL  
ILI  
Output HIGH Voltage  
VCC = Min., IOH = 1.0 mA  
2.0  
2.2  
0.3  
1  
0.4  
VCC + 0.3  
V
V
V
V
µA  
µA  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage(1)  
Input Leakage  
VCC = Min., IOL = 2.1 mA  
0.4  
1
1
GND VIN VCC  
GND VOUT VCC  
ILO  
Output Leakage  
1  
Note:  
1. VIL = 3.0V for pulse width less than 10 ns.  
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)  
-70  
Min.  
-85  
Min.  
Symbol Parameter  
Test Conditions  
Max.  
Max.  
Unit  
ICC  
Vcc Dynamic  
Operating  
VCC = Max., CE = VIL  
IOUT = 0 mA, f = fMAX  
Com.  
Ind.  
30  
35  
25  
30  
mA  
Supply Current  
ISB1  
ISB2  
TTL Standby  
Current  
(TTL Inputs)  
VCC = Max.,  
VIN = VIH or VIL,  
CE1 VIH or CE2 VIL, f = 0  
Com.  
Ind.  
0.4  
1.0  
0.4  
1.0  
mA  
µA  
CMOS Standby VCC = Max., f = 0  
Current CE1 VCC 0.2V,  
(CMOS Inputs) CE2 0.2V,  
or VIN VCC 0.2V, VIN 0.2V  
Com.  
Ind.  
5
5
5
5
Note:  
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.  
4
Integrated Silicon Solution, Inc. 1-800-379-4774  
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
-70  
-85  
Symbol  
tRC  
Parameter  
Min.  
70  
10  
5
Max.  
Min.  
85  
15  
5
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
tAA  
Address Access Time  
Output Hold Time  
70  
85  
tOHA  
tACE1  
tACE2  
tDOE  
CE1 Access Time  
CE2 Access Time  
OE Access Time  
70  
70  
35  
25  
85  
85  
45  
25  
(2)  
tHZOE  
OE to High-Z Output  
OE to Low-Z Output  
CE1 to Low-Z Output  
CE2 to Low-Z Output  
CE1 or CE2 to High-Z Output  
(2)  
tLZOE  
tLZCE1(2)  
tLZCE2(2)  
10  
10  
0
10  
10  
0
(2)  
tHZCE  
25  
25  
Notes:  
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and  
outputloadingspecifiedinFigure1.  
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.  
AC TEST CONDITIONS  
Parameter  
Input Pulse Level  
Input Rise and Fall Times  
Unit  
0.4V to 2.2V  
5 ns  
Input and Output Timing  
and Reference Level  
1.3V  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
3070  
3070 Ω  
2.8V  
2.8V  
OUTPUT  
OUTPUT  
3150 Ω  
3150 Ω  
30 pF  
Including  
jig and  
5 pF  
Including  
jig and  
scope  
scope  
Figure 1  
Figure 2  
Integrated Silicon Solution, Inc. 1-800-379-4774  
5
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
AC WAVEFORMS  
READ CYCLE NO. 1(1,2)  
t
RC  
ADDRESS  
DOUT  
t
AA  
t
OHA  
t
OHA  
DATA VALID  
READ CYCLE NO. 2(1,3)  
tRC  
ADDRESS  
OE  
tAA  
tOHA  
tHZOE  
tDOE  
tLZOE  
CE1  
tACE1/tACE2  
CE2  
tLZCE1/  
tLZCE2  
tHZCE  
HIGH-Z  
DOUT  
DATA VALID  
Notes:  
1. WE is HIGH for a Read Cycle.  
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.  
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.  
6
Integrated Silicon Solution, Inc. 1-800-379-4774  
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)  
-70 -85  
Symbol  
tWC  
Parameter  
Min.  
70  
65  
65  
65  
0
Max.  
Min.  
85  
70  
70  
70  
0
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Cycle Time  
tSCE1  
tSCE2  
tAW  
CE1 to Write End  
CE2 to Write End  
Address Setup Time to Write End  
Address Hold from Write End  
Address Setup Time  
WE Pulse Width  
tHA  
tSA  
0
0
(4)  
tPWE  
60  
30  
0
60  
35  
0
tSD  
tHD  
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
(2)  
tHZWE  
5
33  
5
25  
(2)  
tLZWE  
Notes:  
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof1.3V,inputpulselevelsof0.4Vto2.2VandoutputloadingspecifiedinFigure1.  
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.  
3. TheinternalwritetimeisdefinedbytheoverlapofCE1LOW,CE2HIGHandWELOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactiveto  
terminatetheWrite. TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatestheWrite.  
4. Tested with OE HIGH.  
AC WAVEFORMS  
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)  
t
WC  
ADDRESS  
CE1  
t
HA  
tSCE1  
tSCE2  
CE2  
tAW  
(4)  
t
PWE  
WE  
DOUT  
DIN  
t
SA  
tHZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
tSD  
t
HD  
DATA-IN VALID  
Integrated Silicon Solution, Inc. 1-800-379-4774  
7
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)  
t
WC  
ADDRESS  
OE  
t
HA  
tSCE1  
CE1  
tSCE2  
CE2  
tAW  
t
PWE1, 2  
WE  
t
SA  
tHZWE  
t
LZWE  
HIGH-Z  
SD  
DOUT  
DIN  
DATA UNDEFINED  
t
tHD  
DATA-IN VALID  
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)  
t
WC  
ADDRESS  
OE  
t
HA  
tSCE1  
CE1  
tSCE2  
CE2  
tAW  
t
PWE1, 2  
WE  
t
SA  
tHZWE  
t
LZWE  
HIGH-Z  
SD  
DOUT  
DIN  
DATA UNDEFINED  
t
tHD  
DATA-IN VALID  
8
Integrated Silicon Solution, Inc. 1-800-379-4774  
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
DATA RETENTION SWITCHING CHARACTERISTICS  
Symbol Parameter  
Test Condition  
Min. Max.  
Unit  
VDR  
Vcc for Data Retention  
Data Retention Current  
See Data Retention Waveform  
Vcc = 2.0V, CE1 Vcc 0.2V  
2.0  
3.6  
V
IDR  
Com.  
Ind.  
2
5
µA  
µA  
tSDR  
tRDR  
Data Retention Setup Time See Data Retention Waveform  
Recovery Time See Data Retention Waveform  
0
ns  
ns  
tRC  
DATA RETENTION WAVEFORM (CE1 Controlled)  
t
Data Retention Mode  
t
RDR  
SDR  
V
CC  
DR  
3.0V  
2.2V  
V
CE1 V  
CC  
Ð 0.2V  
CE1  
GND  
DATA RETENTION WAVEFORM (CE2 Controlled)  
Data Retention Mode  
V
CC  
3.0  
t
t
RDR  
SDR  
CE2  
2.2V  
V
DR  
0.4V  
GND  
CE2 0.2V  
Integrated Silicon Solution, Inc. 1-800-379-4774  
9
Rev. B  
05/03/00  
®
IS62LV2568LL  
ISSI  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Speed (ns) Order Part No.  
Package  
70  
IS62LV2568LL-70B  
IS62LV2568LL-70T  
IS62LV2568LL-70H  
mini BGA (6mm x 8mm)  
TSOP, Type I  
STSOP, Type I  
85  
IS62LV2568LL-85B  
IS62LV2568LL-85T  
IS62LV2568LL-85H  
mini BGA (6mm x 8mm)  
TSOP, Type I  
STSOP, Type I  
Industrial Range: 40°C to +85°C  
Speed (ns) Order Part No.  
Package  
70  
IS62LV2568LL-70BI  
IS62LV2568LL-70TI  
IS62LV2568LL-70HI  
mini BGA (6mm x 8mm)  
TSOP, Type I  
STSOP, Type I  
85  
IS62LV2568LL-85BI  
IS62LV2568LL-85TI  
IS62LV2568LL-85HI  
mini BGA (6mm x 8mm)  
TSOP, Type I  
STSOP, Type I  
®
ISSI  
IntegratedSiliconSolution, Inc.  
2231 Lawson Lane  
Santa Clara, CA 95054  
Tel: 1-800-379-4774  
Fax: (408) 588-0806  
E-mail: sales@issi.com  
www.issi.com  
10  
Integrated Silicon Solution, Inc. 1-800-379-4774  
Rev. B  
05/03/00  

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