IS62WV102416ALL [ISSI]
1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM; 1M ×16高速低功率异步CMOS静态RAM
| 型号： | IS62WV102416ALL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM |
| 文件： | 总17页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POWER
ASYNCHRONOUS CMOS STATIC RAM
JANUARY2008
FEATURES
• High-speed access times:
25, 35 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
DESCRIPTION
TheISSIIS62WV102416ALL/BLLandIS65WV102416BLL
are high-speed, 16M-bit static RAMs organized as 1024K
wordsby16bits. ItisfabricatedusingISSI'shigh-perform-
anceCMOStechnology.Thishighlyreliableprocesscoupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
• Easy memory expansion with CS1 and OE
options
• CS1 power-down
• Fully static operation: no clock or refresh
required
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LBandUBareHIGH, thedeviceassumesastandbymode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• TTL compatible inputs and outputs
• Single power supply
VDD 1.65V to 2.2V (IS62WV102416ALL)
speed = 35ns for VDD 1.65V to 2.2V
VDD 2.4V to 3.6V (IS62/65WV102416BLL)
speed = 25ns for VDD 2.4V to 3.6V
• Packages available:
The device is packaged in the JEDEC standard 48-pin
TSOP Type I and 48-pin Mini BGA (9mm x 11mm).
–
48-ball miniBGA (9mm x 11mm)
– 48-pin TSOP (Type I)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
FUNCTIONAL BLOCK DIAGRAM
1024K x 16
MEMORY ARRAY
A0-A19
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS1
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
1Mx16 LOW POWER PIN CONFIGURATIONS
48-Pin mini BGA (9mmx11mm)
1
2
3
4
5
6
A0
A3
A1
A4
A2
LB
I/O
OE
UB
CS2
A
B
C
D
E
F
CS1
I/O
0
8
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
GND
VDD
A7
I/O
I/O
A17
NC
A14
A12
I/O
I/O
I/O
VDD
GND
11
3
4
5
A16
A15
A13
A10
12
I/O
14
I/O
I/O
6
13
A19
A8
I/O
15
WE
I/O
7
G
H
A18
A9
A11
NC
PIN DESCRIPTIONS
A0-A19
I/O0-I/O15
CS1, CS2
OE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
WE
LB
UB
NC
VDD
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
48-pin TSOP-I (12mm x 20mm)
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A5
A6
A7
A8
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
NC
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A9
A19
A18
A17
A16
A15
A10
A11
A12
A13
A14
PIN DESCRIPTIONS
A0-A19
I/O0-I/O15
CS1
OE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
WE
LB
UB
NC
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
TRUTH TABLE
I/O PIN
Mode
WE CS1 CS2
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
X
X
X
H
X
X
X
L
X
X
X
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
ICC
ICC
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
Write
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
V
°C
W
VTERM
VDD
Terminal Voltage with Respect to GND
VDD Relates to GND
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
TSTG
PT
StorageTemperature
PowerDissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
OPERATING RANGE (VDD) (IS62WV102416ALL)
Range
AmbientTemperature
0°C to +70°C
VDD (35 nS)
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Commercial
Industrial
Automotive
–40°Cto+85°C
–40°Cto+125°C
OPERATING RANGE (VDD) (IS62WV102416BLL)(1)
Range
Commercial
Industrial
Note:
AmbientTemperature
0°C to +70°C
VDD (25 nS)
2.4V-3.6V
2.4V-3.6V
–40°Cto+85°C
1. When operated in the range of 2.4V-3.6V, the device meets 10ns.
OPERATING RANGE (VDD) (IS65WV102416BLL)
Range
AmbientTemperature
VDD (25 nS)
Automotive
–40°Cto+125°C
2.4V-3.6V
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5
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter
TestConditions
Min.
1.8
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 1.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2.0
–0.3
–1
VDD + 0.3
V
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL(min.)=–2.0VAC(pulsewidth <10ns).Not100%tested.
IH(max.)=VDD+0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth<10ns).Not100%tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter
TestConditions
IOH = -0.1 mA
IOL = 0.1 mA
VDD
Min.
Max.
Unit
V
VOH
VOL
VIH
OutputHIGHVoltage
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
Vcc – 0.4V
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakage
—
1.4
–0.2
–1
0.2
V
VDD + 0.2
V
(1)
VIL
0.4
1
V
ILI
ILO
GND ≤ VIN ≤ VDD
µA
µA
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Notes:
1. VIL(min.)= –0.3VDC; VIL(min.)= –2.0VAC(pulsewidth<10ns).Not100%tested.
VIH(max.)= VDD+0.3VDC;VIH(max.)= VDD+2.0VAC(pulsewidth<10ns).Not100%tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Unit
Unit
(2.4V-3.6V)
(1.65V-2.2V)
Input Pulse Level
Input Rise and Fall Times
0.4V to VDD-0.3V
1.5ns
0.4V to VDD-0.2V
1.5ns
Input and Output Timing
VDD/2
VDD/2
andReferenceLevel(VRef)
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
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7
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
-35
Symbol
Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = fMAX
VIN = 0.4V or VDD –0.3V
Com.
Ind.
—
—
—
30
35
60
—
—
—
25
30
60
mA
Auto.
typ.(2)
25
ICC1
ISB1
ISB2
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
VIN = 0.4V or VDD –0.3V
Com.
Ind.
Auto.
—
—
—
20
30
50
—
—
—
20
30
50
mA
mA
mA
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CS1 ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
15
20
40
—
—
—
15
20
40
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
—
0.8
1.2
2
—
—
—
0.8
1.2
2
CS1 ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
typ.(2)
0.1
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
25 ns
35 ns
Symbol
tRC
Parameter
Min.
Max.
—
25
—
25
12
8
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
25
—
3
35
—
3
tAA
Address Access Time
Output Hold Time
35
—
tOHA
tACS1/tACS2
tDOE
CS1/CS2 Access Time
OE Access Time
—
—
—
5
—
—
—
5
35
15
10
—
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
tLZOE
—
8
(2)
tHZCS1/tHZCS2
0
0
10
—
(2)
tLZCS1/tLZCS2
10
—
0
—
25
8
10
—
0
tBA
35
10
—
tHZB
tLZB
0
—
0
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4toVDD-0.2V/0.4VtoVDD-0.3Vand
outputloadingspecifiedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured 500mVfromsteady-statevoltage.Not100%tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
tOHA
DATA VALID
DQ0-D15
PREVIOUS DATA VALID
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9
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
t
RC
ADDRESS
tAA
tOHA
OE
t
HZOE
t
DOE
t
LZOE
CS1
s
t
ACE1/tACE2
CS2
s
s
tLZCE1/
tLZCE2
t
t
HZCS1/
HZCS1
LBs, UB
tBA
tHZB
tLZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE,CS1,UB,orLB=VIL. CS2=WE=VIH
3. AddressisvalidpriortoorcoincidentwithCS1LOWtransition.
.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
25ns
35 ns
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
25
18
15
0
—
—
—
—
—
—
—
—
—
12
—
35
25
25
0
—
—
—
—
—
—
—
—
—
20
—
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
tHA
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tSA
0
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
18
18
12
0
25
30
15
0
(4)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
(3)
tLZWE
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof 0.4toVDD-0.2V/0.4VtoVDD-0.3Vand
outputloadingspecifiedinFigure1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. TestedwiththeloadinFigure2.Transitionismeasured 500mVfromsteady-statevoltage.Not100%tested.
4. tPWE >tHZWE +tSD whenOEisLOW.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
t
PWB
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1,CS2andWEinputsandatleastoneoftheLBandUBinputs
beingintheLOWstate.
2. WRITE=(CS1)[(LB)=(UB)](WE).
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11
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
tHA
tSCS1
tSCS2
CS1
CS2
tAW
tPWE
WE
LB, UB
DOUT
DIN
tSA
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DATA-IN VALID
tHD
12
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Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
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13
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CS1 ≥ VDD – 0.2V
1.2
3.6
IDR
Com.
Ind.
Auto.
—
—
—
0.1
0.1
0.1
0.8
1.2
2
mA
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
Note:
o
1. Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CS1 ≥ VDD - 0.2V
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
V
DD
3.0
t
t
RDR
SDR
CE2
2.2V
V
DR
CS2 ≤ 0.2V
0.4V
GND
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/18/08
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
25
IS62WV102416BLL-25MI
48 mini BGA (9mm x 11mm)
IS62WV102416BLL-25MLI 48 mini BGA (9mm x 11mm), Lead-free
IS62WV102416BLL-25TI
IS62WV102416BLL-25TLI
TSOP (Type I)
TSOP (Type I), Lead-free
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed(ns)
Order Part No.
Package
35
IS62WV102416ALL-35MI
48 mini BGA (9mm x 11mm)
IS62WV102416ALL-35MLI 48 mini BGA (9mm x 11mm), Lead-free
IS62WV102416ALL-35TI
IS62WV102416ALL-35TLI
TSOP (Type I)
TSOP (Type I), Lead-free
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
25
IS65WV102416BLL-25MA3 48 mini BGA (9mm x 11mm)
IS65WV102416BLL-25TA3 TSOP (Type I)
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. A
01/18/08
PACKAGING INFORMATION
Plastic TSOP - 48 pins
Package Code: T (Type I)
A
A1
1
N
E
b
e
D1
D
SEATING PLANE
L
α
C
Plastic TSOP (T - Type I)
Millimeters Inches
Notes:
Symbol Min
Ref. Std.
Max
Min
Max
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and should be measured from the bottom of the
N
A
48
—
1.20
—
0.047
A1
b
C
D
D1
E
0.05 0.15
0.17 0.27
0.10 0.21
19.8 20.2
18.2 18.6
11.8 12.2
0.50 BSC
0.002 0.006
0.007 0.011
0.004 0.008
0.780 0.795
0.716 0.732
0.464 0.480
0.020 BSC
package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
e
L
0.50 0.70
0.020 0.028
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T48 Rev. B 07/17/97
相关型号：
IS62WV102416DBLL-45TLI
Standard SRAM, 1MX16, 45ns, CMOS, PDSO48, 12 X 20 MM, LEAD FREE, TSOP1-48
ISSI
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