IS62WV1288ALL-70BI [ISSI]
128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM; 128K ×8低电压，超低功耗CMOS静态RAM
| 型号： | IS62WV1288ALL-70BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 文件： | 总15页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62WV1288ALL
IS62WV1288BLL
ISSI
JUNE2005
128K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS62WV1288ALL / IS62WV1288BLL are high-
speed, 1M bit static RAMs organized as 128K words by 8
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
• High-speed access time: 45ns, 55ns, 70ns
• CMOS low power operation:
30 mW (typical) operating
15 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected),thedeviceassumesastandbymodeatwhich
the power dissipation can be reduced down with CMOS
input levels.
1.65V--2.2V VDD (62WV1288ALL)
2.5V--3.6V VDD (62WV1288BLL)
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
TheIS62WV1288ALLandIS62WV1288BLLarepackaged
in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP
(TYPEI), SOP, and 36-pin mini BGA.
• Three state outputs
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
1
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
PIN CONFIGURATION
32-pin TSOP (TYPE I) (T),
32-pin sTSOP (TYPE I) (H)
36-pin mini BGA (B) (6mm x 8mm)
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A11
A9
1
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
2
A8
3
A13
WE
CS2
A15
4
A
B
C
D
E
F
A0
A1
A2
CS2
WE
NC
A3
A4
A5
A6
A7
A8
5
I/O4
I/O5
GND
I/O0
I/O1
6
7
V
DD
8
V
DD
NC
A16
A14
A12
A7
9
V
DD
GND
I/O2
I/O3
A14
10
11
12
13
14
15
16
I/O6
I/O7
A9
NC
CS1
A11
NC
A16
A12
OE
A15
A13
G
H
A10
A1
A6
A2
A5
A3
A4
PIN DESCRIPTIONS
32-pin SOP (Q)
A0-A16
CS1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
CS2
2
A15
CS2
WE
A13
A8
OE
3
4
WE
5
I/O0-I/O7
NC
A6
6
NoConnection
Power
A5
7
A9
A4
8
A11
OE
VDD
A3
9
GND
Ground
A2
10
11
12
13
14
15
16
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
A1
A0
I/O0
I/O1
I/O2
GND
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
Parameter
Value
–0.2 to VDD+0.3
–0.2 to +3.8
–65 to +150
1.0
Unit
V
Terminal Voltage with Respect to GND
VDD Related to GND
StorageTemperature
PowerDissipation
V
TSTG
PT
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (VDD)
Range
AmbientTemperature
0°C to +70°C
IS62WV1288ALL
1.65V - 2.2V
IS62WV1288BLL
2.5V - 3.6V
Commercial
Industrial
–40°Cto+85°C
1.65V - 2.2V
2.5V - 3.6V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
VDD
Min.
Max.
Unit
VOH
OutputHIGHVoltage
IOH = -0.1 mA
IOH = -1 mA
1.65-2.2V
2.5-3.6V
1.4
2.2
—
—
V
V
VOL
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
IOL = 0.1 mA
IOL = 2.1 mA
1.65-2.2V
2.5-3.6V
—
—
0.2
0.4
V
V
(2)
VIH
1.65-2.2V
2.5-3.6V
1.4
2.2
VDD + 0.2
VDD + 0.3
V
V
(1)
VIL
ILI
1.65-2.2V
2.5-3.6V
–0.2
–0.2
0.4
0.6
V
V
InputLeakage
GND ≤ VIN ≤ VDD
–1
–1
1
1
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
Notes:
1. Undershoot: –1.0V for pulse width less than 10 ns. Not 100% tested.
2. Overshoot: VDD + 1.0V for pulse width less than 10 ns. Not 100% tested.
TRUTH TABLE
Mode
WE
CS1
CS2
OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
3
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
InputCapacitance
Input/OutputCapacitance
COUT
VOUT = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
62WV1288ALL
62WV1288BLL
(Unit)
0.4V to VDD-0.2V
5 ns
(Unit)
0.4V to VDD-0.3V
5ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
VREF
VREF
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
1.65V - 2.2V
2.5V - 3.6V
3070
R1(Ω)
R2(Ω)
VREF
3070
3150
0.9V
1.8V
3150
1.5V
VTM
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
5 pF
Including
jig and
R2
30 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV1288ALL(1.65V-2.2V)
Symbol Parameter
DD DynamicOperating
TestConditions
Max.
70ns
Unit
ICC
V
VDD =Max.,
Com.
Ind.
8
8
5
mA
SupplyCurrent
IOUT =0mA,f=fMAX
typ.(2)
I
CC
1
OperatingSupply
Current
V
I
DD =Max.,
OUT =0mA,f=0
DD =Max.,
IN =VIH orVIL
CS1=VIH ,CS2=VIL
f=1MH
Com.
Ind.
5
5
mA
mA
ISB
1
TTLStandbyCurrent
(TTLInputs)
V
V
Com.
Ind.
0.8
0.8
,
Z
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
DD =Max.,
CS1 DD–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
10
10
5
µA
≥V
typ.(2)
V
IN
≥
≤
V
DD –0.2V,or
VIN
0.2V,f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=1.8V, TA=25oC. Not 100% tested.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV1288BLL(2.5V-3.6V)
Symbol Parameter
DD DynamicOperating
TestConditions
Max.
45ns
Max.
55ns
Unit
ICC
V
VDD=Max.,
Com.
Ind.
17
17
12
15
15
10
mA
SupplyCurrent
IOUT =0mA,f=fMAX
typ.(2)
I
CC
1
OperatingSupply
Current
V
DD=Max.,
Com.
Ind.
5
5
5
5
mA
mA
I
OUT =0mA,f=0
ISB
1
TTLStandbyCurrent
(TTLInputs)
VDD=Max.,
Com.
Ind.
0.8
0.8
0.8
0.8
VIN =VIH orVIL
CS1=VIH ,CS2=VIL
,
f=1MH
Z
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
DD=Max.,
CS1 DD–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
10
10
5
10
10
5
µA
≥V
typ.(2)
V
IN
≥
≤
V
DD –0.2V,or
VIN
0.2V,f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.0V, TA=25oC. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
5
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
45ns
Min. Max.
55 ns
Min. Max.
70ns
Max.
Symbol
Parameter
Min.
70
—
10
—
—
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACS1/
DOE
ReadCycleTime
45
—
10
—
—
0
—
45
—
45
20
15
—
15
—
55
—
10
—
—
0
—
55
—
55
25
20
—
20
—
—
70
—
70
35
25
—
25
—
t
AddressAccessTime
OutputHoldTime
t
t
t
ACS2
CS1/CS2AccessTime
OEAccessTime
t
(2)
tHZOE
OEtoHigh-ZOutput
OEtoLow-ZOutput
CS1/CS2toHigh-ZOutput
CS1/CS2toLow-ZOutput
(2)
t
LZOE
HZCS1/
LZCS1/
5
5
5
(2)
t
t
HZCS2
0
0
0
(2)
t
t
LZCS2
5
10
10
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CS1
tACS1/tACS2
CS2
tLZCS1/
tLZCS2
tHZCS
DATA VALID
HIGH-Z
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
7
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
45 ns
55 ns
70 ns
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
SCS1/
AW
HA
SA
PWE
SD
HD
HZWE
WriteCycleTime
45
35
35
0
—
—
—
—
—
—
—
—
20
—
55
45
45
0
—
—
—
—
—
—
—
—
20
—
70
60
60
0
—
—
—
—
—
—
—
—
20
—
t
t
SCS2
CS1/CS2toWriteEnd
AddressSetupTimetoWriteEnd
AddressHoldfromWriteEnd
AddressSetupTime
t
t
t
0
0
0
t
WEPulseWidth
35
20
0
40
25
0
50
t
DataSetuptoWriteEnd
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
30
0
t
(3)
(3)
t
—
5
—
5
—
5
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V
to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
t
SCS1
t
SCS2
CS2
t
AW
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
9
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
TestCondition
Min.
1.2
—
Max.
Unit
V
VDR
IDR
VDD for Data Retention
DataRetentionCurrent
SeeDataRetentionWaveform
VDD = 1.2V, CS1 ≥ VDD – 0.2V
3.6
5
µA
ns
tSDR
tRDR
Data Retention Setup Time SeeDataRetentionWaveform
RecoveryTime SeeDataRetentionWaveform
0
—
—
tRC
ns
DATA RETENTION WAVEFORM (CS1 Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
V
DR
CS1 ≥ V
0.2V
DD
-
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
V
DD
t
t
RDR
SDR
CS2
V
DR
CS2 ≤ 0.2V
GND
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/20/05
®
IS62WV1288ALL, IS62WV1288BLL
ISSI
ORDERING INFORMATION
IS62WV1288ALL (1.65V - 2.2V)
Industrial Range: -40°C to +85°C
Speed(ns)
Order Part No.
Package
70
IS62WV1288ALL-70BI
IS62WV1288ALL-70HI
mini BGA (6mm x 8mm)
sTSOP, TYPE I
IS62WV1288BLL (2.5V-3.6V)
Industrial Range: -40°C to +85°C
Speed(ns)
Order Part No.
Package
45
IS62WV1288BLL-45TI
IS62WV1288BLL-45BI
IS62WV1288BLL-45HI
IS62WV1288BLL-45QI
TSOP, TYPE I
mini BGA (6mm x 8mm)
sTSOP, TYPE I
SOP
55
IS62WV1288BLL-55TI
IS62WV1288BLL-55TLI
TSOP, TYPE I
TSOP, TYPE I, Lead-free
IS62WV1288BLL-55BI
mini BGA (6mm x 8mm)
IS62WV1288BLL-55HI
IS62WV1288BLL-55HLI
sTSOP, TYPE I
sTSOP, TYPE I, Lead-free
IS62WV1288BLL-55QI
IS62WV1288BLL-55QLI
SOP
SOP,Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11
06/20/05
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: B (36-pin)
Top View
Bottom View
φ b (36x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
Min. Typ. Max.
36
MILLIMETER
INCHES
Min. Typ. Max.
36
Sym. Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
Leads
N0.
Leads
36
36
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
0.009
0.024
A1
A2
D
0.24
0.60
0.009
0.024
7.90 8.00 8.10
5.25BSC
0.311 0.315 0.319
0.207BSC
9.90 10.00 10.10
5.25BSC
0.390 0.394 0.398
.207BSC
D1
E
D1
E
5.90 6.00 6.10
3.75BSC
0.232 0.236 0.240
0.148BSC
7.90 8.00 8.10
3.75BSC
0.311 0.315 0.319
0.148BSC
E1
e
E1
e
0.75BSC
0.030BSC
0.75BSC
0.030BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
01/15/03
®
PACKAGING INFORMATION
450-mil Plastic SOP
ISSI
Package Code: Q (32-pin)
N
E1 E
1
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
—
0.10
0.36
0.15
20.14
13.87
11.18
3.00
—
—
0.118
—
0.004
0.014
0.006
0.793
0.546
0.440
0.51
0.30
20.75
14.38
11.43
0.020
0.012
0.817
0.566
0.450
E1
e
1.27 BSC
0.050 BSC
L
α
0.58
0°
0.99
10°
0.023
0°
0.039
10°
S
—
0.86
—
0.034
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
®
PACKAGING INFORMATION
ISSI
Plastic STSOP - 32 pins
Package Code: H (Type I)
A2
A
A1
1
N
E
b
e
D1
D
S
SEATING PLANE
L
α
C
Plastic STSOP (H - Type I)
Millimeters
Inches
Notes:
Symbol Min Max
Min
Max
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and should be measured from the bottom of the package
Ref. Std.
N
32
A
A1
A2
b
C
D
D1
E
e
—
0.05
1.25
—
—
0.049
—
0.041
0.009
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
0.002
0.037
0.007
0.95 1.05
0.17 0.23
0.14 0.16
13.20 13.60
11.70 11.90
7.90 8.10
0.50 BSC
0.0055 0.0063
0.520
0.461
0.311
0.535
0.469
0.319
0.020 BSC
L
S
0.30 0.70
0.28 Typ.
0.012
0.011 Typ.
0.028
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197H32 Rev.B 04/21/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP-Type I
Package Code: T (32-pin)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
H
e
—
1.20
0.25
0.23
0.17
8.10
—
0.047
0.010
0.009
0.007
0.319
0.728
0.795
0.05
0.17
0.12
7.90
18.30
19.80
0.002
0.007
0.005
0.311
0.720
0.780
18.50
20.20
0.50 BSC
0.020 BSC
L
α
0.40
0°
0.60
8°
0.016
0°
0.024
8°
S
0.25 REF
0.010 REF
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
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