IS64LP25618-150BA3 [ISSI]
Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA119, PLASTIC, BGA-119;
| 型号： | IS64LP25618-150BA3 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA119, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS64LP12832
IS64LP12836, IS64LP25618
128K x 32, 128K x 36, 256K x 18
SYNCHRONOUS
ISSI
ADVANCED INFORMATION
JANUARY 2003
PIPELINED STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS64LP12832, IS64LP12836, and IS64LP25618
are high-speed synchronous static RAMs designed to
provide high-performance memory with burst for high-
speed networking and communication applications.
IS64LP12832 is organized as 131,072 words by 32 bits.
IS64LP12836 is organized as 131,072 words by 36 bits.
IS64LP25618 isorganizedas262,144wordsby18bits.The
IS64LP12832, IS64LP12836, and IS64LP25618 arefabri-
cated with ISSI's advanced CMOS technology. These
devices integrate a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power-down snooze mode
• Power Supply
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
+ 3.3V VDD
+ 3.3V OR 2.5V VDDQ (I/O)
• Temperature offerings
Option A1: -400 C to +850 C
Option A2: -400 C to +1050 C
Option A3: -400 C to +1250 C
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls
DQc, BW4 controls DQd, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be
written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-166
3.5
6
-150
3.8
Units
ns
Clock Access Time
Cycle Time
tKC
6.7
ns
Frequency
166
150
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
1
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
BLOCK DIAGRAM
MODE
A0
A0'
A1'
Q0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
ADSC
ADSP
128K x 32/128K x 36,
256K x 18
CLR
MEMORY ARRAY
17/18
16/17
18/19
D
Q
A
ADDRESS
REGISTER
CE
CLK
32 or 36
or 18
32 or 36
or 18
D
Q
GW
BWE
DQd
BYTE WRITE
REGISTERS
BW4
(x32/ x36)
CLK
D
Q
DQc
BYTE WRITE
REGISTERS
BW3
(x32/ x36)
CLK
D
Q
DQb
BYTE WRITE
REGISTERS
BW2
(x32/ x36/ x18)
CLK
D
Q
DQa
BYTE WRITE
REGISTERS
BW1
(x32/ x36/ x18)
CLK
32 or 36
or 18
CE
CE2
CE2
4
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DQa-d
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
A
B
C
D
E
F
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQb
DQb
NC
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDDQ
NC
A6
CE2
A77
A4
A3
ADSP
ADSC
VDD
NC
A8
A9
A1166
VDDQ
NC
CE2
A1155
NC
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
NC
A2
A12
GND
GND
GND
BW2
GND
NC
NC
DQc11
DQc22
VDDQ
DQc55
DQc77
VDDQ
DQd11
DQd4
VDDQ
DQd66
DQd8
NC
NC
GND
GND
GND
BW3
GND
NC
DQb8
DQb77
VDDQ
DQb33
DQb11
VDDQ
DQa88
DQa66
VDDQ
DQa22
DQa11
NC
DQc33
DQc4
DQc6
DQc8
VDD
DQd22
DQd33
DQd55
DQd77
NC
CE
DQb66
DQb55
DQb44
DQb22
VDD
DQa77
DQa55
DQa44
DQa33
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
ADV
GW
VDD
CLK
NC
VDD
NC
VDD
ZZ
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
NC
K
L
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
NC
GND
BW4
GND
GND
GND
MODE
A1100
GND
BW1
GND
GND
GND
NC
M
N
P
R
T
BWE
A1
A0
A5
VDD
A11
NC
A1133
NC
NC
A1144
NC
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VDDQ
NC
NC
NC
VDDQ
128K x 32
PIN DESCRIPTIONS
GW
SynchronousGlobalWriteEnable
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
ADV
SynchronousControllerAddress
Status
VDDQ
Isolated Output Buffer Supply: +3.3V
or 2.5V
Synchronous Burst Address Ad-
vance
ZZ
SnoozeEnable
BW1-BW4
Individual Byte Write Enable
BWE
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
3
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP
1
2
3
4
5
6
7
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
A
B
C
D
E
F
VDDQ
NC
A6
CE2
A4
A3
ADSP
ADSC
VDD
NC
A8
A9
A1166
VDDQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
CE2
NC
A77
A2
A1122
GND
GND
GND
BW2
GND
NC
A1155
DQPb
DQb66
DQb55
DQb44
DQb22
VDD
NC
DQc11
DQc2
VDDQ
DQc55
DQc7
VDDQ
DQd11
DQd4
VDDQ
DQd66
DQd8
NC
DQPc
DQc3
DQc4
DQc6
DQc8
VDD
DQd22
DQd33
DQd55
DQd77
DQPd
A55
GND
GND
GND
BW3
GND
NC
DQb8
DQb77
VDDQ
DQb33
DQb11
VDDQ
DQa88
DQa66
VDDQ
DQa22
DQa11
NC
CE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OE
G
H
J
ADV
GW
VDD
CLK
NC
VDD
NC
VDD
ZZ
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
K
L
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
GND
BW4
GND
GND
GND
MODE
A1100
GND
BW1
GND
GND
GND
NC
DQa77
DQa55
DQa44
DQa33
DQPa
A1133
M
N
P
R
T
BWE
A1
A0
VDD
A1111
NC
NC
NC
A14
NC
NC
ZZ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
U
VDDQ
NC
NC
NC
VDDQ
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQd
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
GND
ADSC
SynchronousControllerAddress
Status
VDDQ
Isolated Output Buffer Supply: +3.3V or
2.5V
ADV
Synchronous Burst Address Advance
Individual Byte Write Enable
ZZ
SnoozeEnable
Parity Data I/O
BW1-BW4
BWE
DQPa-DQPd
Synchronous Byte Write Enable
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP
1
2
3
4
5
6
7
A
B
C
D
E
F
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
VDDQ
NC
A66
CE2
A77
A4
A3
ADSP
ADSC
VDD
NC
A8
A9
A16
VDDQ
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
GND
NC
DQPa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
NC
NC
NC
NC
VDDQ
GND
NC
CE2
NC
A2
A12
GND
GND
GND
GND
GND
NC
A1155
DQPa
NC
NC
DQb
NC
NC
GND
GND
GND
BW2
GND
NC
NC
NC
DQb
DQb
GND
VDDQ
DQb
DQb
NC
DQb
NC
CE
DQa
VDDQ
DQa
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
NC
OE
DQa
NC
G
H
J
DQb
NC
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
DQa
VDD
NC
VDD
NC
VDD
ZZ
VDD
DQb
NC
VDDQ
DQa
NC
GND
DQb
DQb
VDDQ
GND
DQb
DQb
DQPb
NC
GND
VDDQ
NC
NC
NC
K
L
DQa
DQa
VDDQ
GND
DQa
DQa
NC
GND
GND
GND
GND
GND
MODE
A
GND
BW1
GND
GND
GND
GND
A
DQb
VDDQ
DQb
NC
DQa
NC
M
N
P
R
T
DQb
NC
BWE
A1
VDDQ
NC
NC
DQa
NC
GND
VDDQ
NC
NC
NC
DQPb
A
A0
DQa
NC
NC
VDD
NC
A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
SynchronousGlobalWriteEnable
CE, CE2, CE2 SynchronousChipEnable
OE
OutputEnable
A
Synchronous Address Inputs
SynchronousClock
DQa-DQb
MODE
VDD
SynchronousDataInput/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
CLK
ADSP
SynchronousProcessorAddress
Status
ADSC
SynchronousControllerAddress
Status
GND
VDDQ
Isolated Output Buffer Supply: +3.3V
SnoozeEnable
ADV
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
ZZ
BW1-BW2
BWE
DQPa-DQPb
ParityDataI/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
5
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
TRUTH TABLE
Address
Operation
Used
CE
H
L
CE2
X
X
L
CE2 ADSP ADSC ADV WRITE OE
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected,Power-down
Deselected,Power-down
Deselected,Power-down
Deselected,Power-down
Deselected,Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
None
X
None
L
L
X
None
X
X
L
X
L
H
H
L
X
None
L
X
External
External
External
Next
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
Q
L
L
L
D
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
Q
H
L
High-Z
Q
H
X
X
High-Z
D
D
PARTIAL TRUTH TABLE
Function
GW
H
BWE
BW1
BW2
X
BW3
X
BW4
Read
H
L
L
L
X
X
H
L
X
H
H
L
Read
H
H
H
Write Byte 1
Write All Bytes
Write All Bytes
H
H
H
H
L
L
L
L
X
X
X
X
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
°C
W
TSTG
PD
StorageTemperature
–55 to +150
1.6
PowerDissipation
IOUT
OutputCurrent(perI/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VDDQ + 0.3
–0.5 to VDD + 0.5
VIN
Voltage Relative to GND for
for Address and Control Inputs
V
VDD
Voltage on VDD Supply Relative to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periodsmayaffectreliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
orelectricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
7
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
OPERATING RANGE
3.3V (I/O)
2.5V (I/O)
Range AmbientTemperature
VDD
VDDQ
VDDQ
A1
A2
A3
–40°Cto+85°C
–40°Cto+105°C
–40°Cto+125°C
3.3V, +10%, –5%
3.3V, +10%, –5%
3.3V, +10%, –5%
3.3V, +10%, –5%
3.3V, +10%, –5%
3.3V, +10%, –5%
2.5V + 5%
2.5V + 5%
2.5V + 5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
2.5V (I/O)
3.3V (I/O)
Symbol
Parameter
TestConditions
Min.
Max.
Min.
Max.
Unit
VOH
OutputHIGHVoltage
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
VOL
OutputLOWVoltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
VIH
VIL
ILI
InputHIGHVoltage
InputLOWVoltage
1.7
–0.3
–5
VDD + 0.3
2.0
–0.3
–5
VDD + 0.3
V
V
0.7
5
0.8
5
InputLeakageCurrent
OutputLeakageCurrent
GND ≤VIN ≤VDD
µA
µA
ILO
GND≤VOUT ≤VDDQ,
OE = VI
–5
5
–5
5
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166
-150
Symbol
Parameter
Test Conditions
Max.
Max.
Unit
ICC
AC Operating
Supply Current
Device Selected,
A1
A2
A3
290
-
-
mA
mA
All Inputs = VIL or VIH
OE = VIH, VDD = Max.
Cycle Time ≥ tKC min.
280
290
ISB
IZZ
Standby Current
Device Deselected,
VDD = Max.,
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
A1
A2
A3
70
-
-
80
90
mA
mA
Power-down Mode ZZ = VDD
Current Clock Running
A1
A2
A3
15
-
-
20
25
mA
mA
All Inputs ≤ GND + 0.2V
or ≥ VDD – 0.2V
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VDD.
2. The MODE pin should be tied to VDD or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V
or ≥ VDD – 0.2V.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
1.5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
ZO = 50Ω
+3.3V
Output
OUTPUT
50Ω
5 pF
Including
jig and
351 Ω
scope
1.5V
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
9
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
0V to 2.5V
1ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.25V
OutputLoad
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
ZO = 50Ω
+2.5V
Output
OUTPUT
50Ω
5 pF
Including
jig and
1538 Ω
scope
1.25V
Figure 3
Figure 4
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-150
Min.
Symbol
Parameter
Min. Max.
Max.
150
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)
fMAX
Clock Frequency
—
6.0
2.4
2.4
—
166
—
—
6.7
2.6
2.6
—
(3)
tKC
Cycle Time
tKH
Clock High Time
—
—
(3)
tKL
Clock Low Time
—
—
(3)
tKQ
Clock Access Time
3.5
—
3.8
—
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
3.0
0
3.0
0
(1,2)
tKQLZ
—
—
(1,2)
tKQHZ
1.5
—
3.5
3.8
—
1.5
—
3.5
3.8
—
(3)
tOEQ
(1)
tOEQX
0
0
(1,2)
tOELZ
0
—
0
—
(1,2)
tOEHZ
2.0
2.0
1.5
1.5
2.0
1.5
1.0
1.0
1.0
1.0
1.0
3.5
—
2.0
2.0
1.5
1.5
2.0
1.5
1.0
1.0
1.0
1.0
1.0
3.5
—
(3)
tAS
(3)
tSS
Address Status Setup Time
Write Setup Time
—
—
(3)
tWS
—
—
(3)
tCES
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
—
—
(3)
tAVS
—
—
(3)
tAH
—
—
(3)
tSH
Address Status Hold Time
Write Hold Time
—
—
(3)
tWH
—
—
(3)
tCEH
Chip Enable Hold Time
Address Advance Hold Time
—
—
(3)
tAVH
—
—
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
11
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
A
t
AS
tAH
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
BW4-BW1
t
CES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Min.
-150
Min.
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tKC
tKH
Cycle Time
6
6.7
2.6
2.6
2.0
1.5
1.5
1.5
2.0
1.5
1.0
1.0
1.0
1.0
1.0
1.0
(1)
Clock High Time
2.4
2.4
2.0
1.5
1.5
1.5
2.0
1.5
1.0
1.0
1.0
1.0
1.0
1.0
(1)
(1)
tKL
Clock Low Time
tAS
tSS
Address Setup Time
Address Status Setup Time
Write Setup Time
(1)
(1)
tWS
(1)
tDS
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
(1)
tCES
tAVS
(1)
(1)
tAH
tSH
tDH
(1)
(1)
(1)
tWH
Write Hold Time
(1)
(1)
tCEH
tAVH
Chip Enable Hold Time
Address Advance Hold Time
Note:
1. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
13
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
A
t
AS
tAH
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BW4-BW1
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-166
Min.
-150
Min.
Symbol Parameter
Max.
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
(3)
tKC
tKH
Cycle Time
6
2.4
2.4
—
1.5
0
6.7
2.6
2.6
—
1.5
0
(3)
Clock High Time
—
—
(3)
(3)
tKL
Clock Low Time
—
—
tKQ
Clock Access Time
3.5
—
3.8
—
(1)
tKQX
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
(1,2)
tKQLZ
—
—
(1,2)
tKQHZ
1.5
—
0
3.5
3.5
—
1.5
—
0
3.5
3.5
—
(3)
tOEQ
(1)
tOEQX
(1,2)
tOELZ
0
—
0
—
(1,2)
tOEHZ
2
3.5
—
2
3.5
—
(3)
tAS
2.0
1.5
2.0
1.0
1.0
1.0
2
2.0
1.5
2.0
1.0
1.0
1.0
2
(3)
tSS
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
—
—
(3)
tCES
—
—
(3)
tAH
tSH
—
—
(3)
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby
—
—
(3)
tCEH
tZZS
—
—
—
—
tZZREC
ZZ Recovery
2
—
2
—
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
15
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
t
SS
tSH
ADV
A
t
AS
tAH
RD1
RD2
GW
BWE
BW4-BW1
t
CES
tCEH
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
t
t
OEHZ
t
OEQ
OE
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
1a
t
KQLZ
t
KQX
KQHZ
t
KQ
t
DATAIN
ZZ
t
ZZS
tZZREC
Snooze with Data Retention
Single Read
Read
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
®
IS64LP12836, IS64LP25618
ISSI
ORDERING INFORMATION
Temperature Range (A1): –40°C to +85°C
Speed
Order Part No.
Organization
Package
166 MHz
IS64LP12832-166TQA1
IS64LP12832-166BA1
IS64LP12836-166TQA1
IS64LP12836-166BA1
IS64LP25618-166TQA1
IS64LP25618-166BA1
128Kx32
128Kx32
128Kx36
128Kx36
256Kx18
256Kx18
TQFP
PBGA
TQFP
PBGA
TQFP
PBGA
Temperature Range (A2): –40°C to +105°C
Speed
Order Part No.
Organization
Package
150 MHz
IS64LP12832-150TQA2
IS64LP12832-150BA2
IS64LP12836-150TQA2
IS64LP12836-150BA2
IS64LP25618-150TQA2
IS64LP25618-150BA2
128Kx32
128Kx32
128Kx36
128Kx36
256Kx18
256Kx18
TQFP
PBGA
TQFP
PBGA
TQFP
PBGA
Temperature Range (A3): –40°C to +125°C
Speed
Order Part No.
Organization
Package
150 MHz
IS64LP12832-150TQA3
IS64LP12832-150BA3
IS64LP12836-150TQA3
IS64LP12836-150BA3
IS64LP25618-150TQA3
IS64LP25618-150BA3
128Kx32
128Kx32
128Kx36
128Kx36
256Kx18
256Kx18
TQFP
PBGA
TQFP
PBGA
TQFP
PBGA
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
17
01/20/03
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