IS64LPS204818B-166TQLA3 [ISSI]
Cache SRAM, 2MX18, 3.8ns, CMOS, PQFP100, LQFP-100;
| 型号： | IS64LPS204818B-166TQLA3 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Cache SRAM, 2MX18, 3.8ns, CMOS, PQFP100, LQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总35页 (文件大小：1141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
wordsꢀbyꢀ32ꢀbits.
36ꢀbits.ꢀTheꢀIS61LPS102432Bꢀisꢀorganizedꢀasꢀ1,048,476ꢀ
TheꢀIS61LPS/VPS204818Bꢀisꢀorganizedꢀ
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
1M x 36, 1M x 32, 2M x 18
36 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
NOVEMBER 2017
FEATURES
DESCRIPTION
Theꢀ36Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ
synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ
high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-
workingꢀapplications.ꢀTheꢀIS61LPS/VPS102436Bꢀandꢀ
IS64LPS102436Bꢀareꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ
•ꢀ Internalꢀself-timedꢀwriteꢀcycle
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ
control
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ
asꢀ2,096,952ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ
advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ
2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-
driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ
synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ
aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-
pansionꢀandꢀaddressꢀpipelining
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
•ꢀ AutoꢀPower-downꢀduringꢀdeselect
•ꢀ Singleꢀcycleꢀdeselect
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ
oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ
inputs.
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage
•ꢀ PowerꢀSupply
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ
writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ
individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ
Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ
regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.
ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)
VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
•ꢀ JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-
ballꢀBGAꢀpackages
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ
Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-
atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ
advance)ꢀinputꢀpin.ꢀ
•ꢀ Lead-freeꢀavailable
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ
orꢀleftꢀfloating.
FAST ACCESS TIME
Symbol
tkq
Parameter
250
2.8
4
200
3.1
5
166
Units
ns
Clock Access Time
Cycle Time
3.8
6
tkc
ns
Frequency
250
200
166
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BLOCK DIAGRAM
MODE
A0
A0`
A1`
CLK
Q0
Q1
BINARY
COUNTER
/CKE
/ADV
A1
/CE
/ADSC
/ADSP
/CLR
20/21
1Mx36;
2Mx18
Memory Array
D
Q
A0-x
x18: x=20
x36: x=19
ADDRESS
REGISTER
18/19
/CE
CLK
/GW
D
Q
/BWE
DQ(a-d)
BYTE WRITE
REGISTERS
/BW(a-x)
x18:x=b,
x32,x36:x=d
INPUT
REGISTER
CLK
/CE
D
Q
CE2
/CE2
CLK
ENABLE
OUTPUT
REGISTER
REGISTERS
DQ(a-x)
x18:x=b,
x32,x36:x=d
CLK
CLK
Power
Down
ZZ
D
Q
ENABLE DELAY
REGISTERS
CLK
/OE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165-PIN BgA
119-PIN BgA
119-Ball,ꢀ14x22ꢀmmꢀBGA
165-Ball,ꢀ13x15ꢀmmꢀBGA
BOTTOMꢀVIEW
BOTTOMꢀVIEW
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION-1M x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A
A
A
A
ADSP
ADSC
VDD
NC
A
A
A
A
VDDQ
NC
NC
A
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQbꢀ
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CE
OE
g
H
J
ADV
GW
VDD
CLK
NC
K
L
Vss
BWd
Vss
Vss
Vss
MODE
A
M
N
P
R
T
BWE
A1*
A0*
VDD
A
NC
NC
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: ꢀ*ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
OEꢀ
Pin Name
Symbol
Aꢀ
Pin Name
AsynchronousꢀOutputꢀEnable
AsynchronousꢀPowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
SynchronousꢀAddressꢀInputs
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ZZꢀ
A0,ꢀA1ꢀ
ADVꢀ
ꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
MODEꢀ
TCK,ꢀTDO
ꢀꢀTMS,ꢀTDI
NCꢀ
ADSP
ADSC
GWꢀ
SynchronousꢀAddressꢀStatusꢀProcessor
SynchronousꢀAddressꢀStatusꢀController
SynchronousꢀGlobalꢀWriteꢀEnable
SynchronousꢀClock
NoꢀConnect
DQa-DQd
Synchronous Data Inputs/Outputs
CLKꢀ
DQPa-DQPd Synchronous Parity Data
CE,ꢀCE2
BWa-BWdꢀ
BWE
SynchronousꢀChipꢀSelect
Inputs/Outputs
SynchronousꢀByteꢀWriteꢀControls
SynchronousꢀByteꢀWriteꢀEnable
Vdd
PowerꢀSupply
I/OꢀPowerꢀSupply
Groundꢀ
Vddq
Vss
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION
2Mx18 (TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A
A
A
A
ADSP
ADSC
VDD
NC
A
A
A
A
VDDQ
NCꢀꢀꢀꢀ
NC
NC
A
A
A
A
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NCꢀꢀꢀꢀꢀ
DQa
VDDQ
DQa
NC
CE
VDDQ
NC
OE
g
H
J
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDDQ
DQa
NC
K
L
Vss
Vss
Vss
Vss
Vss
MODE
A
DQb
VDDQ
DQb
NC
M
N
P
R
T
BWE
A1*
VDDQ
NC
A0*
DQa
NC
NC
VDD
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: ꢀ*ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
OEꢀ
Pin Name
Symbol
Aꢀ
Pin Name
Asynchronous OutputꢀEnable
Asynchronous PowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
SynchronousꢀAddressꢀInputs
SynchronousꢀBurstꢀAddressꢀInputsꢀ
ZZꢀ
A0,ꢀA1ꢀ
ADVꢀ
ꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
MODEꢀ
TCK,ꢀTDO
TMS,ꢀTDI
NCꢀ
ADSP
ADSC
GWꢀ
SynchronousꢀAddressꢀStatusꢀProcessor
SynchronousꢀAddressꢀStatusꢀController
SynchronousꢀGlobalꢀWriteꢀEnable
SynchronousꢀClock
NoꢀConnect
DQa-DQb
Synchronous Data Inputs/Outputs
CLKꢀ
DQPa-DQPb Synchronous Parity Data
CE,ꢀCE2
BWa-BWbꢀ
BWE
SynchronousꢀChipꢀSelect
Inputs/Outputs
SynchronousꢀByteꢀWriteꢀControls
SynchronousꢀByteꢀWriteꢀEnable
Vdd
PowerꢀSupply
I/OꢀPowerꢀSupply
Groundꢀ
Vddq
Vss
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165 BGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
1
2
3
4
5
6
7
8
ADSC
OE
9
10
A
11
NC
A
B
C
D
E
F
NC
A
CE
BWc
BWd
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADV
ADSP
Vddq
Vddqꢀꢀꢀꢀ
Vddq
Vddq
Vddq
NC
NC
A
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
A
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQPc
DQc
DQc
DQc
DQc
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
A
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
NC
DQb
DQb
DQb
DQb
NC
g
H
J
DQd
DQd
DQd
DQd
DQPd
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
Vddq
Vddq
Vddq
Vddq
Vddq
A
dqa
dqa
dqa
dqa
dqa
dqa
dqa
dqa
K
L
M
N
P
R
N C ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ DQPa
TDI
TMS
A1*
A0*
TDO
TCK
A
A
A
A
MODE
A
A
A
A
Note: ꢀ*ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
Aꢀ
Pin Name
Symbol
BWE
OEꢀ
Pin Name
SynchronousꢀAddressꢀInputs
SynchronousꢀBurstꢀAddressꢀInputsꢀ
SynchronousꢀByteꢀWriteꢀEnable
AsynchronousꢀOutputꢀEnable
AsynchronousꢀPowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
A0,ꢀA1ꢀ
ADVꢀ
ꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
ZZꢀ
MODEꢀ
ADSP
ADSC
GW
SynchronousꢀAddressꢀStatusꢀProcessor
SynchronousꢀAddressꢀStatusꢀController
SynchronousꢀGlobalꢀWriteꢀEnable
SynchronousꢀClock
TCK,ꢀTDO
TMS,ꢀTDI
NCꢀ
NoꢀConnect
CLKꢀ
DQa-DQd
Synchronous Data Inputs/Outputs
CE, CE2, CE2 SynchronousꢀChipꢀSelect
BWa-BWdꢀ SynchronousꢀByteꢀWriteꢀControls
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Vdd
PowerꢀSupply
I/OꢀPowerꢀSupplyꢀꢀꢀꢀ
Ground
Vddq
Vssꢀ
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165 BGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
1
NC
2
3
4
5
6
7
8
ADSC
OE
9
10
A
11
A
A
B
C
D
E
F
A
CE
BWb
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
NC
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
ADV
ADSP
Vddq
Vddqꢀꢀꢀꢀ
Vddqꢀꢀꢀꢀ
Vddqꢀꢀꢀꢀ
Vddqꢀꢀꢀꢀ
NC
NC
A
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
A
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
NC
NC
NC
NC
NC
NC
dqa
dqa
dqa
dqa
NC
A
NC
NC
NC
g
H
J
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
Vddq
Vddq
Vddq
Vddq
Vddq
A
NC
NC
NC
NC
NC
A
K
L
M
N
P
R
TDI
TMS
A1*
A0*
TDO
TCK
MODE
A
A
A
A
A
A
Note: ꢀ*ꢀA0ꢀandꢀA1ꢀareꢀtheꢀtwoꢀleastꢀsignificantꢀbitsꢀ(LSB)ꢀofꢀtheꢀaddressꢀfieldꢀandꢀsetꢀtheꢀinternalꢀburstꢀcounterꢀifꢀburstꢀisꢀdesired.ꢀ
PIN DESCRIPTIONS
Symbol
Aꢀ
Pin Name
Symbol
BWE
OEꢀ
Pin Name
SynchronousꢀAddressꢀInputs
SynchronousꢀBurstꢀAddressꢀInputsꢀ
SynchronousꢀByteꢀWriteꢀEnable
AsynchronousꢀOutputꢀEnable
AsynchronousꢀPowerꢀSleepꢀModeꢀ
BurstꢀSequenceꢀSelection
JTAGꢀPins
A0,ꢀA1ꢀ
ADVꢀ
ꢀ
SynchronousꢀBurstꢀAddressꢀ
Advance
ZZꢀ
MODEꢀ
ADSP
ADSC
GW
SynchronousꢀAddressꢀStatusꢀProcessor
SynchronousꢀAddressꢀStatusꢀController
SynchronousꢀGlobalꢀWriteꢀEnableꢀ
SynchronousꢀClock
TCK,ꢀTDO
TMS,ꢀTDI
NCꢀ
NoꢀConnect
CLKꢀ
DQa-DQb
Synchronous Data Inputs/Outputs
CE, CE2, CE2 SynchronousꢀChipꢀSelect
BWa-BWbꢀ SynchronousꢀByteꢀWriteꢀControls
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Vdd
3.3V/2.5VꢀPowerꢀSupply
I/OꢀPowerꢀSupplyꢀꢀꢀꢀ
Ground
Vddq
Vssꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PIN CONFIGURATION
100-PIN QFP (1M x 36)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
addressꢀbus.
DQa-DQd
Synchronous Data Inputs/Outputs
DQPa-DQPd Synchronous Parity Data
Inputs/Outputs
Aꢀ
SynchronousꢀAddressꢀInputs
GWꢀ
ꢀ
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
AsynchronousꢀOutputꢀEnable
PowerꢀSupply
ADSCꢀꢀ
ADSPꢀꢀ
ADVꢀꢀ
SynchronousꢀControllerꢀAddressꢀStatus
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
MODEꢀꢀ ꢀ
OEꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddꢀ
Vddqꢀ
Vssꢀ
ZZꢀ
BWa-BWdꢀ
BWEꢀ
I/OꢀPowerꢀSupply
Ground
CE, CE2, CE2ꢀ SynchronousꢀChipꢀEnable
CLKꢀꢀ SynchronousꢀClock
AsynchronousꢀSnoozeꢀEnable
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PIN CONFIGURATION
100-PIN QFP (1M x 32)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
NC
VDD
ZZ
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
addressꢀbus.
DQa-DQd
GWꢀ
MODEꢀꢀ ꢀ
Synchronous Data Inputs/Outputs
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
AsynchronousꢀOutputꢀEnable
PowerꢀSupply
ꢀ
Aꢀ
SynchronousꢀAddressꢀInputs
OEꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ADSCꢀꢀ
ADSPꢀꢀ
ADVꢀꢀ
SynchronousꢀControllerꢀAddressꢀStatus
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
Vddꢀ
Vddqꢀ
Vssꢀ
ZZꢀ
I/OꢀPowerꢀSupply
Ground
BWa-BWdꢀ
BWEꢀ
AsynchronousꢀSnoozeꢀEnable
CE, CE2, CE2ꢀ SynchronousꢀChipꢀEnable
CLKꢀꢀ SynchronousꢀClock
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
PIN CONFIGURATION
100-PIN QFP (2M x 18)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VDD
ZZ
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable Option)
PIN DESCRIPTIONS
DQPa-DQPb Synchronous Parity Data
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
addressꢀbus.
Inputs/Outputs
GWꢀ
ꢀ
SynchronousꢀGlobalꢀWriteꢀEnable
BurstꢀSequenceꢀModeꢀSelection
AsynchronousꢀOutputꢀEnable
PowerꢀSupply
Aꢀ
SynchronousꢀAddressꢀInputs
MODEꢀꢀ ꢀ
ADSCꢀꢀ
ADSPꢀꢀ
ADVꢀꢀ
SynchronousꢀControllerꢀAddressꢀStatus
SynchronousꢀProcessorꢀAddressꢀStatus
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
SynchronousꢀByteꢀWriteꢀEnable
OEꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddꢀ
Vddqꢀ
Vssꢀ
ZZꢀ
I/OꢀPowerꢀSupply
BWa-BWbꢀ
BWEꢀ
Ground
AsynchronousꢀSnoozeꢀEnable
CE,ꢀCE2,ꢀCE2ꢀ SynchronousꢀChipꢀEnable
CLKꢀꢀ
SynchronousꢀClock
DQa-DQb
Synchronous Data Inputs/Outputs
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE
CLK
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Xꢀ
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
DeselectꢀCycle,ꢀPower-Downꢀ
SnoozeꢀꢀMode,ꢀPower-Downꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
WriteꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀBeginꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
WriteꢀCycle,ꢀContinueꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
ReadꢀCycle,ꢀSuspendꢀBurstꢀ
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
WriteꢀCycle,ꢀSuspendꢀBurstꢀ
Noneꢀ
Noneꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Noneꢀ
Lꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Noneꢀ
Lꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Noneꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Nextꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
L-Hꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
Lꢀ
High-Z
D
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Nextꢀ
Lꢀ
Hꢀ
Lꢀ
High-Z
Q
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
High-Z
D
Nextꢀ
Lꢀ
Nextꢀ
Lꢀ
Lꢀ
D
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Currentꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Q
Hꢀ
Lꢀ
High-Z
Q
Hꢀ
Xꢀ
Xꢀ
High-Z
D
Lꢀ
D
NOTE:
1.ꢀ Xꢀmeansꢀ“Don’tꢀCare.”ꢀHꢀmeansꢀlogicꢀHIGH.ꢀLꢀmeansꢀlogicꢀLOW.
2.ꢀ ForꢀWRITE,ꢀLꢀmeansꢀoneꢀorꢀmoreꢀbyteꢀwriteꢀenableꢀsignalsꢀ(BWa-d)ꢀandꢀBWEꢀareꢀLOWꢀorꢀGWꢀisꢀLOW.ꢀWRITEꢀ=ꢀHꢀforꢀallꢀ
BWx,ꢀBWE,ꢀGWꢀHIGH.
3.ꢀ BWaꢀenablesꢀWRITEsꢀtoꢀDQa’sꢀandꢀDQPa.ꢀBWbꢀenablesꢀWRITEsꢀtoꢀDQb’sꢀandꢀDQPb.ꢀBWcꢀenablesꢀWRITEsꢀtoꢀDQc’sꢀ andꢀ
DQPc.ꢀBWdꢀenablesꢀWRITEsꢀtoꢀDQd’sꢀandꢀDQPd.ꢀDQPaꢀandꢀDQPbꢀareꢀavailableꢀonꢀtheꢀx18ꢀversion.ꢀ DQPa-DQPdꢀareꢀavail-
ableꢀonꢀtheꢀx36ꢀversion.
4.ꢀ AllꢀinputsꢀexceptꢀOEꢀandꢀZZꢀmustꢀmeetꢀsetupꢀandꢀholdꢀtimesꢀaroundꢀtheꢀrisingꢀedgeꢀ(LOWꢀtoꢀHIGH)ꢀofꢀCLK.
5.ꢀ Waitꢀstatesꢀareꢀinsertedꢀbyꢀsuspendingꢀburst.
6.ꢀ ForꢀaꢀWRITEꢀoperationꢀfollowingꢀaꢀREADꢀoperation,ꢀOEꢀmustꢀbeꢀHIGHꢀbeforeꢀtheꢀinputꢀdataꢀsetupꢀtimeꢀandꢀheldꢀHIGHꢀduringꢀ
theꢀinputꢀdataꢀholdꢀtime.
7.ꢀ ThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputsꢀwillꢀbeꢀinꢀHigh-Zꢀduringꢀpower-up.
8.ꢀ ADSPꢀLOWꢀalwaysꢀinitiatesꢀanꢀinternalꢀREADꢀatꢀtheꢀL-HꢀedgeꢀofꢀCLK.ꢀAꢀWRITEꢀisꢀperformedꢀbyꢀsettingꢀoneꢀorꢀmoreꢀbyteꢀwriteꢀ
enableꢀsignalsꢀandꢀBWEꢀLOWꢀorꢀGWꢀLOWꢀforꢀtheꢀsubsequentꢀL-HꢀedgeꢀofꢀCLK.ꢀSeeꢀWRITEꢀtimingꢀdiagramꢀforꢀclarification.
PARTIAL TRUTH TABLE
Function
GW
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
BWE
Hꢀ
BWa
Xꢀ
BWb
Xꢀ
BWc
Xꢀ
BWd
Xꢀ
Readꢀ
Readꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
WriteꢀByteꢀ1ꢀ
WriteꢀAllꢀBytesꢀ
WriteꢀAllꢀBytesꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
POwER UP SEQUENCE
1
Vddqꢀ→ꢀVdd ꢀ→ꢀꢀI/OꢀPins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POwER-UP INITIALIZATION TIMINg
VDD
power > 1ms
Device ready for
normal operation
VDD
Device Initialization
VDDQ
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
ꢀ
ꢀ
ꢀ
ꢀ
00ꢀ
01ꢀ
10ꢀ
11ꢀ
01ꢀ
00ꢀ
11ꢀ
10ꢀ
10ꢀ
11ꢀ
00ꢀ
01ꢀ
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
ABSOLUTE MAXIMUM RATINgS(1)
Symbol Parameter
LPS Value
–55ꢀtoꢀ+150ꢀ
1.6ꢀ
VPS/VVPS Value
–55ꢀtoꢀ+150ꢀ
1.6ꢀ
Unit
°C
W
ꢀ TsTg
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
ꢀ Pd
ꢀ IOuTꢀ
OutputꢀCurrentꢀ(perꢀI/O)ꢀ
100ꢀ
100ꢀ
mA
V
V
ꢀ VIN, VOuTꢀ VoltageꢀRelativeꢀtoꢀVssꢀforꢀI/OꢀPinsꢀ
–0.5ꢀtoꢀVddq + 0.5
–0.5ꢀtoꢀVdd + 0.5
–0.5ꢀtoꢀVddq + 0.3
–0.5ꢀtoꢀVdd + 0.3
ꢀ VINꢀ
VoltageꢀRelativeꢀtoꢀVssꢀforꢀꢀ
forꢀAddressꢀandꢀControlꢀInputs
ꢀ Vddꢀ
VoltageꢀonꢀVddꢀSupplyꢀRelativeꢀtoꢀVssꢀ –0.5ꢀtoꢀVdd + 0.5ꢀ
–0.3ꢀtoꢀVdd + 0.3
V
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀ
Thisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀ
theꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀ
periodsꢀmayꢀaffectꢀreliability.ꢀ
2.ꢀThisꢀdeviceꢀcontainsꢀcircuityꢀtoꢀprotectꢀtheꢀinputsꢀagainstꢀdamageꢀdueꢀtoꢀhighꢀstaticꢀvoltagesꢀorꢀelectricꢀfields;ꢀhowever,ꢀ
precautionsꢀmayꢀbeꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀhigherꢀthanꢀmaximumꢀratedꢀvoltagesꢀtoꢀthisꢀhigh-impedanceꢀ
circuit.
3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHigh-Zꢀatꢀpowerꢀup.
OPERATINg RANgE (IS61/64LPSXXXXX)
Ranꢀe
Ambient Temperature
VDD
VDDq
ꢀ
ꢀ
ꢀ
Commercialꢀ
Industrialꢀ
Automotiveꢀ
0°Cꢀtoꢀ+70°Cꢀ
3.3Vꢀ+ꢀ5%ꢀ
3.3Vꢀ+ꢀ5%ꢀ
3.3Vꢀ+ꢀ5%ꢀ
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
3.3Vꢀ/ꢀ2.5Vꢀ+ꢀ5%
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
OPERATINg RANgE (IS61/64VPSXXXXX)
Ranꢀe
Ambient Temperature
VDD
VDDq
ꢀ
ꢀ
ꢀ
Commercialꢀ
Industrialꢀ
Automotiveꢀ
0°Cꢀtoꢀ+70°Cꢀ
2.5Vꢀ+ꢀ5%ꢀ
ꢀ2.5Vꢀ+ꢀ5%ꢀ
ꢀ2.5Vꢀ+ꢀ5%ꢀ
ꢀ2.5Vꢀ+ꢀ5%
ꢀ2.5Vꢀ+ꢀ5%
ꢀ2.5Vꢀ+ꢀ5%
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
OPERATINg RANgE (IS61/64VVPSXXXXX)
Ranꢀe
Ambient Temperature
VDD
VDDq
ꢀ
ꢀ
ꢀ
Commercialꢀ
Industrialꢀ
Automotiveꢀ
0°Cꢀtoꢀ+70°Cꢀ
1.8Vꢀ+ꢀ5%ꢀ
ꢀ1.8Vꢀ+ꢀ5%ꢀ
ꢀ1.8Vꢀ+ꢀ5%ꢀ
ꢀ1.8Vꢀ+ꢀ5%
ꢀ1.8Vꢀ+ꢀ5%
ꢀ1.8Vꢀ+ꢀ5%
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)ꢀ1,ꢀ2,ꢀ3
3.3V
2.5V
Min. Max.
1.8V
Symbol Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
ꢀ ꢀ
Oh
OutputꢀHIGHꢀVoltageꢀ
ꢀ
I
I
Oh = –4.0ꢀmAꢀ(3.3V)ꢀ
Oh = –1.0ꢀmAꢀ(2.5V,ꢀ1.8V)
2.4ꢀ
ꢀ
—ꢀ
2.0ꢀ
ꢀ
—
V
ddq - 0.4ꢀ —ꢀ
Vꢀ
ꢀ VOl
ꢀ ꢀ
OutputꢀLOWꢀVoltageꢀ
ꢀ
I
I
Ol = 8.0ꢀmAꢀ(3.3V)ꢀ
Ol = 1.0ꢀmAꢀ(2.5V,ꢀ1.8V)
—ꢀ
ꢀ
0.4ꢀ
—ꢀ
ꢀ
0.4ꢀ
—ꢀ
ꢀ
0.4ꢀ
Vꢀ
ꢀ VIh
ꢀ VIl
InputꢀHIGHꢀVoltageꢀꢀ
InputꢀLOWꢀVoltageꢀ
InputꢀLeakageꢀCurrentꢀ
InputꢀCurrentꢀofꢀMODEꢀ Vssꢀ≤ꢀVIN ≤ Vdd
InputꢀCurrentꢀofꢀZZꢀ Vssꢀ≤ꢀVIN ≤ Vdd
ꢀ
ꢀ
2.0ꢀ
V
dd +ꢀ0.3ꢀ
1.7
V
dd + 0.3 0.6Vdd
V
dd + 0.3
V
-0.3ꢀ ꢀ 0.8ꢀ
-0.3ꢀ ꢀ 0.7ꢀ
-0.3ꢀ ꢀ 0.3Vdd
ꢀ
V
(1,4)ꢀ
ꢀ IlI
ꢀ ꢀ
ꢀ ꢀ
Vssꢀ≤ꢀVIN ≤ Vdd
-5ꢀ
-30ꢀ ꢀ
-5ꢀ
-5ꢀ
ꢀ
5ꢀ
5ꢀ
30ꢀ
-5ꢀ
-30ꢀ
-5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
5ꢀ
30ꢀ
-5ꢀ
-30ꢀ
-5ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
5ꢀ
30
µAꢀ
ꢀ
(5)ꢀ
(6)ꢀ
ꢀ
ꢀ
IlO
OutputꢀLeakageꢀCurrentꢀ Vssꢀ≤ꢀVOuT ≤ Vddq, ꢀ
ꢀ OE = VIh
5ꢀ
-5ꢀ
ꢀ
5ꢀ
-5ꢀ
ꢀ
5ꢀ
µAꢀ
ꢀ ꢀ
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. Except MODE and ZZ
5. MODE is connected to pull-up resister internally.
6. ZZ is connected to pull-down resister internally.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250
-200
-166
MAX
MAX
MAX
Symbol Parameter
Test Conditions
Temp. range
x18
x36
x18
x36
x18
x36
Unit
icc
isb
Isbi
AC Operating
Supply Current
Device Selected,
OE = Vih, ZZ ≤ Vil,
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Auto
Cycle Time ≥ tkc min.
Com.
ind.
400
450
-
400
450
-
350
400
500
350
400
500
320
350
450
320
350
450
mA
Standby Current
TTL Input
Device Deselected,
Vdd = Max.,
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Com.
Ind.
Auto
200
220
-
200
220
-
200
220
350
200
220
350
200
220
350
200
220
350
mA
Standby Current
cMOs Input
Device Deselected,
Vdd = Max.,
Com.
Ind.
180
200
-
180
200
-
180
200
320
180
200
320
180
200
320
180
200
320
mA
Vin
≤ Vss + 0.2V or ≥Vdd – 0.2V Auto
f = 0
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
6ꢀ
Unit
pF
CIN
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ COuTꢀ
VOuT = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTa = 25°C, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ3.0V
1.5ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀRefeꢀrenceꢀLevelꢀ
1.5Vꢀ
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
AC TEST LOADS
317 Ω
3.3V
Z
O
= 50Ω
OUTPUT
Output
50Ω
351 Ω
5 pF
Including
jig and
1.5V
scope
Fiꢀure 1
Fiꢀure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
2.5V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ2.5V
1.5ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ
1.25Vꢀ
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ3ꢀandꢀ4
2.5 I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
2.5V
Z
O
= 50Ω
OUTPUT
Output
50Ω
1,538 Ω
5 pF
Including
jig and
scope
1.25V
Fiꢀure 3
Fiꢀure 4
1.8V I/O AC TEST CONDITIONS
Parameter
Unit
0Vꢀtoꢀ1.8V
1.5ꢀns
InputꢀPulseꢀLevelꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ
0.9Vꢀ
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ5ꢀandꢀ6
1.8 I/O OUTPUT LOAD EQUIVALENT
1K Ω
1.8V
Z
O
= 50Ω
OUTPUT
Output
50Ω
1K Ω
5 pF
Including
jig and
0.9V
scope
Fiꢀure 5
Fiꢀure 6
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
READ/wRITE CYCLE SwITCHINg CHARACTERISTICS (OverꢀOperatingꢀRange)
-250
-200
Min.
-166
Min.
Symbol
fMaxꢀ
tkCꢀ
Parameter
Min.
—ꢀ
Max.
250ꢀ
—ꢀ
—ꢀ
—ꢀ
2.8ꢀ
—ꢀ
—ꢀ
2.8ꢀ
2.8ꢀ
—ꢀ
2.8ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
Max.
200ꢀ
—ꢀ
—ꢀ
—ꢀ
3.1ꢀ
—ꢀ
—ꢀ
3.1ꢀ
3.1ꢀ
—ꢀ
3.1ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
Max.
166ꢀ
—ꢀ
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ClockꢀFrequencyꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
6ꢀ
ꢀ
ꢀ
CycleꢀTimeꢀ
4.0ꢀ
1.7ꢀ
1.7ꢀ
—ꢀ
tkhꢀ
ClockꢀHighꢀTimeꢀ
2ꢀ
2.4ꢀ ꢀ —ꢀ
2.3ꢀ ꢀ —ꢀ
tklꢀ
ClockꢀLowꢀTimeꢀ
2ꢀ
tkqꢀ
ClockꢀAccessꢀTimeꢀꢀ
—ꢀ
1.5ꢀ
1ꢀ
—ꢀ
ꢀ
3.8ꢀ
tkqx(2)ꢀ
tkqlZ(2,3)ꢀ
tkqhZ(2,3)ꢀ
tOEqꢀ
tOElZ(2,3)ꢀ
tOEhZ(2,3)ꢀ
tasꢀ
ClockꢀHighꢀtoꢀOutputꢀInvalidꢀ
ClockꢀHighꢀtoꢀOutputꢀLow-Zꢀ
ClockꢀHighꢀtoꢀOutputꢀHigh-Zꢀ
OutputꢀEnableꢀtoꢀOutputꢀValidꢀ
OutputꢀEnableꢀtoꢀOutputꢀLow-Zꢀ
OutputꢀDisableꢀtoꢀOutputꢀHigh-Zꢀ
AddressꢀSetupꢀTimeꢀ
0.8ꢀ
0.8ꢀ
—ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
0ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3.8ꢀ
3.8ꢀ
—ꢀ
—ꢀ
0ꢀ
—ꢀ
—ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
1ꢀ
—ꢀ
3.8ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
1.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
0.4ꢀ
1ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
1.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
0.5ꢀ ꢀ —ꢀ
tss
AddressꢀStatusꢀSetupꢀTimeꢀ
Read/WriteꢀSetupꢀTimeꢀ
ChipꢀEnableꢀSetupꢀTimeꢀ
AddressꢀAdvanceꢀSetupꢀTimeꢀ
DataꢀSetupꢀTimeꢀ
tWsꢀ
tCEsꢀ
taVsꢀ
tds
tahꢀ
AddressꢀHoldꢀTime
tsh
AddressꢀStatusꢀHoldꢀTime
WriteꢀHoldꢀTimeꢀ
tWhꢀ
tCEhꢀ
taVhꢀ
tdhꢀ
ChipꢀEnableꢀHoldꢀTimeꢀ
AddressꢀAdvanceꢀHoldꢀTimeꢀ
DataꢀHoldꢀTimeꢀ
(4)
tPOWEr
Vddꢀ(typical)ꢀtoꢀFirstꢀAccessꢀ
1ꢀ
ꢀ
—ꢀ
Note:
1.ꢀꢀConfigurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.ꢀ
2.ꢀꢀGuaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled.
3.ꢀ TestedꢀwithꢀloadꢀinꢀFigureꢀ2.
4. tpOwer is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
READ CYCLE TIMINg
tKC
CLK
ADSP
ADSC
tKH
tKL
ADSP is blocked by CE inactive
tSS
tSH
tSS
tSH
ADSC initiate read
t
AVH
t
SS
tSH
t
AVS
Suspend Burst
ADV
tAS
tAH
Address
RD1
RD2
RD3
t
WS
WS
t
t
WH
GW
BWE
BWx
t
WH
tCES
tCEH
CE Masks ADSP
CE
CE2
CE2
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
tOEHZ
tOEQ
OE
t
KQX
tOELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
tKQ
DATAIN
Pipelined Read
Burst Read
Single Read
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
wRITE CYCLE TIMINg
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
t
AVH
tAVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
Address
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
BWx
t
WS
t
WH
t
WS
tWH
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2
CE2
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
t
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Unselected
Single Write
Write
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
19
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions Temperature
Min. Max.
Unit
Ranꢀe
Isb2ꢀ
ꢀ
ꢀ
CurrentꢀduringꢀSNOOZEꢀMODEꢀ ZZ ≥ Vdd - 0.2Vꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ 120ꢀ
—ꢀ 130ꢀ
—ꢀ 250
mAꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tPdsꢀ
tPusꢀ
tZZIꢀ
ZZꢀactiveꢀtoꢀinputꢀignoredꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
2ꢀ
2ꢀ
—ꢀ
2ꢀ
cycle
cycle
cycle
ns
ZZꢀinactiveꢀtoꢀinputꢀsampledꢀ
ZZꢀactiveꢀtoꢀSNOOZEꢀcurrentꢀ
ZZꢀinactiveꢀtoꢀexitꢀSNOOZEꢀcurrentꢀ
—ꢀ
0ꢀ
trZZIꢀ
—ꢀ
SNOOZE MODE TIMINg
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
ISB2
tRZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAg)
TEST ACCESS PORT (TAP) - TEST CLOCK
TheꢀserialꢀboundaryꢀscanꢀTestꢀAccessꢀPortꢀ(TAP)ꢀisꢀonlyꢀ
availableꢀ inꢀ theꢀ BGAꢀ package.ꢀ (Theꢀ QFPꢀ packageꢀ notꢀ
TheꢀtestꢀclockꢀisꢀonlyꢀusedꢀwithꢀtheTAPꢀcontroller.ꢀAllꢀinputsꢀ
areꢀcapturedꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputsꢀareꢀ
drivenꢀfromꢀtheꢀfallingꢀedgeꢀofꢀTCK.
available.)ꢀThisꢀ portꢀ operatesꢀ inꢀ accordanceꢀ withꢀ IEEE
ꢀ
Standardꢀ1149.1-1900,ꢀbutꢀdoesꢀnotꢀincludeꢀallꢀfunctionsꢀ
requiredꢀforꢀfullꢀ1149.1ꢀcompliance.ꢀTheseꢀfunctionsꢀfromꢀ
theꢀ IEEEꢀ specificationꢀ areꢀ excludedꢀ becauseꢀ theyꢀ placeꢀ
addedꢀdelayꢀinꢀtheꢀcriticalꢀspeedꢀpathꢀofꢀtheꢀSRAM.ꢀTheꢀ
TAPꢀcontrollerꢀoperatesꢀinꢀaꢀmannerꢀthatꢀdoesꢀnotꢀconflictꢀ
withꢀtheꢀperformanceꢀofꢀotherꢀdevicesꢀusingꢀ1149.1ꢀfullyꢀ
compliantꢀTAPs.
TEST MODE SELECT (TMS)
TheꢀTMSꢀinputꢀisꢀusedꢀtoꢀsendꢀcommandsꢀtoꢀtheꢀTAPꢀ
controllerꢀandꢀisꢀsampledꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCK.ꢀThisꢀ
pinꢀmayꢀbeꢀleftꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀnotꢀused.ꢀTheꢀpinꢀ
isꢀinternallyꢀpulledꢀup,ꢀresultingꢀinꢀaꢀlogicꢀHIGHꢀlevel.
TEST DATA-IN (TDI)
DISABLINg THE JTAg FEATURE
TheꢀTDIꢀpinꢀisꢀusedꢀtoꢀseriallyꢀinputꢀinformationꢀtoꢀtheꢀ
registersꢀandꢀcanꢀbeꢀconnectedꢀtoꢀtheꢀinputꢀofꢀanyꢀregis-
ter.ꢀTheꢀregisterꢀbetweenꢀTDIꢀandꢀTDOꢀisꢀchosenꢀbyꢀtheꢀ
instructionꢀ loadedꢀ intoꢀ theꢀTAPꢀ instructionꢀ register.ꢀ Forꢀ
informationꢀonꢀinstructionꢀregisterꢀloading,ꢀseeꢀtheꢀTAPꢀ
ControllerꢀStateꢀDiagram.ꢀTDIꢀisꢀinternallyꢀpulledꢀupꢀandꢀ
canꢀbeꢀdisconnectedꢀifꢀtheꢀTAPꢀisꢀunusedꢀinꢀanꢀapplica-
tion.ꢀTDIꢀisꢀconnectedꢀtoꢀtheꢀMostꢀSignificantꢀBitꢀ(MSB)ꢀ
TheꢀSRAMꢀcanꢀoperateꢀwithoutꢀusingꢀtheꢀJTAGꢀfeature.ꢀ
Toꢀ disableꢀ theꢀTAPꢀ controller,ꢀTCKꢀ mustꢀ beꢀ tiedꢀ LOWꢀ
(Vss)ꢀtoꢀpreventꢀclockingꢀofꢀtheꢀdevice.ꢀTDIꢀandꢀTMSꢀareꢀ
internallyꢀpulledꢀupꢀandꢀmayꢀbeꢀdisconnected.ꢀTheyꢀmayꢀ
alternatelyꢀbeꢀconnectedꢀtoꢀVddꢀthroughꢀaꢀpull-upꢀresistor.ꢀ
TDOꢀshouldꢀbeꢀleftꢀdisconnected.ꢀOnꢀpower-up,ꢀtheꢀdeviceꢀ
willꢀstartꢀinꢀaꢀresetꢀstateꢀwhichꢀwillꢀnotꢀinterfereꢀwithꢀtheꢀ
deviceꢀoperation.
onꢀanyꢀregister.
TAP CONTROLLER BLOCK DIAgRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
Selection Circuitry
TDO
31 30 29 . . .
2
2
1
1
0
0
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
21
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TEST DATA OUT (TDO)
Boundary Scan Reꢀister
TheꢀTDOꢀoutputꢀpinꢀisꢀusedꢀtoꢀseriallyꢀclockꢀdata-outꢀfromꢀ
theꢀregisters.ꢀTheꢀoutputꢀisꢀactiveꢀdependingꢀonꢀtheꢀcurrentꢀ
stateꢀofꢀtheꢀTAPꢀstateꢀmachineꢀ(seeꢀTAPꢀControllerꢀStateꢀ
Diagram).ꢀTheꢀoutputꢀchangesꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCKꢀ
andꢀTDOꢀisꢀconnectedꢀtoꢀtheꢀLeastꢀSignificantꢀBitꢀ(LSB)ꢀ
ofꢀanyꢀregister.
Theꢀboundaryꢀscanꢀregisterꢀisꢀconnectedꢀtoꢀallꢀinputꢀandꢀ
outputꢀpinsꢀonꢀtheꢀSRAM.ꢀSeveralꢀnoꢀconnectꢀ(NC)ꢀpinsꢀareꢀ
alsoꢀincludedꢀinꢀtheꢀscanꢀregisterꢀtoꢀreserveꢀpinsꢀforꢀhigherꢀ
densityꢀdevices.ꢀTheꢀx36ꢀconfigurationꢀhasꢀaꢀ75-bit-longꢀ
registerꢀandꢀtheꢀx18ꢀconfigurationꢀalsoꢀhasꢀaꢀ75-bit-longꢀ
register.ꢀTheꢀboundaryꢀscanꢀregisterꢀisꢀloadedꢀwithꢀtheꢀ
contentsꢀofꢀtheꢀRAMꢀInputꢀandꢀOutputꢀringꢀwhenꢀtheꢀTAPꢀ
controllerꢀisꢀinꢀtheꢀCapture-DRꢀstateꢀandꢀthenꢀplacedꢀbe-
tweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀwhenꢀtheꢀcontrollerꢀisꢀmovedꢀ
toꢀtheꢀShift-DRꢀstate.ꢀTheꢀEXTEST,ꢀSAMPLE/PRELOADꢀ
andꢀSAMPLE-Zꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀcaptureꢀtheꢀ
contentsꢀofꢀtheꢀInputꢀandꢀOutputꢀring.
PERFORMINg A TAP RESET
AꢀResetꢀisꢀperformedꢀbyꢀforcingꢀTMSꢀHIGHꢀ(Vdd)ꢀforꢀfiveꢀ
risingꢀedgesꢀofꢀTCK.ꢀRESETꢀmayꢀbeꢀperformedꢀwhileꢀtheꢀ
SRAMꢀisꢀoperatingꢀandꢀdoesꢀnotꢀaffectꢀitsꢀoperation.ꢀAtꢀ
power-up,ꢀtheꢀTAPꢀisꢀinternallyꢀresetꢀtoꢀensureꢀthatꢀTDOꢀ
comesꢀupꢀinꢀaꢀhigh-Zꢀstate.
TheꢀBoundaryꢀScanꢀOrderꢀtablesꢀshowꢀtheꢀorderꢀinꢀwhichꢀ
theꢀbitsꢀareꢀconnected.ꢀEachꢀbitꢀcorrespondsꢀtoꢀoneꢀofꢀtheꢀ
bumpsꢀonꢀtheꢀSRAMꢀpackage.ꢀTheꢀMSBꢀofꢀtheꢀregisterꢀisꢀ
connectedꢀtoꢀTDI,ꢀandꢀtheꢀLSBꢀisꢀconnectedꢀtoꢀTDO.
TAP REgISTERS
RegistersꢀareꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
andꢀallowꢀdataꢀtoꢀbeꢀscannedꢀintoꢀandꢀoutꢀofꢀtheꢀSRAMꢀ
testꢀcircuitry. Onlyꢀoneꢀregisterꢀcanꢀbeꢀselectedꢀatꢀaꢀtimeꢀ
throughꢀtheꢀinstructionꢀregisters.ꢀDataꢀisꢀseriallyꢀloadedꢀ
intoꢀtheꢀTDIꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀTCKꢀandꢀoutputꢀonꢀ
theꢀTDOꢀpinꢀonꢀtheꢀfallingꢀedgeꢀofꢀTCK.
Scan Reꢀister Sizes
Reꢀister
Bit Size
(x18)
3ꢀ
Bit Size
(x36)
3ꢀ
Name
Instruction Reꢀister
Instructionꢀ
Bypassꢀ
Three-bitꢀinstructionsꢀcanꢀbeꢀseriallyꢀloadedꢀintoꢀtheꢀin-
structionꢀregister.ꢀThisꢀregisterꢀisꢀloadedꢀwhenꢀitꢀisꢀplacedꢀ
betweenꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀ(SeeꢀTAPꢀControllerꢀBlockꢀ
Diagram)ꢀ Atꢀpower-up,ꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀ
withꢀtheꢀIDCODEꢀinstruction.ꢀItꢀisꢀalsoꢀloadedꢀwithꢀtheꢀ
IDCODEꢀinstructionꢀifꢀtheꢀcontrollerꢀisꢀplacedꢀinꢀaꢀresetꢀ
stateꢀasꢀpreviouslyꢀdescribed.
1ꢀ
1ꢀ
IDꢀ
32ꢀ
32ꢀ
BoundaryꢀScanꢀ
75ꢀ
75ꢀ
Identification (ID) Reꢀister
TheꢀIDꢀregisterꢀisꢀloadedꢀwithꢀaꢀvendor-specific,ꢀ32-bitꢀ
codeꢀduringꢀtheꢀCapture-DRꢀstateꢀwhenꢀtheꢀIDCODEꢀcom-
mandꢀisꢀloadedꢀtoꢀtheꢀinstructionꢀregister.ꢀTheꢀIDCODEꢀ
isꢀhardwiredꢀintoꢀtheꢀSRAMꢀandꢀcanꢀbeꢀshiftedꢀoutꢀwhenꢀ
theꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀShift-DRꢀstate.ꢀTheꢀIDꢀregisterꢀ
hasꢀvendorꢀcodeꢀandꢀotherꢀinformationꢀdescribedꢀinꢀtheꢀ
IdentificationꢀRegisterꢀDefinitionsꢀtable.
WhenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-IRꢀstate,ꢀtheꢀtwoꢀ
leastꢀsignificantꢀbitsꢀareꢀloadedꢀwithꢀaꢀbinaryꢀ“01”ꢀpatternꢀ
toꢀallowꢀforꢀfaultꢀisolationꢀofꢀtheꢀboardꢀlevelꢀserialꢀtestꢀpath.
Bypass Reꢀister
Toꢀsaveꢀtimeꢀwhenꢀseriallyꢀshiftingꢀdataꢀthroughꢀregisters,ꢀ
itꢀisꢀsometimesꢀadvantageousꢀtoꢀskipꢀcertainꢀstates.ꢀTheꢀ
bypassꢀregisterꢀisꢀaꢀsingle-bitꢀregisterꢀthatꢀcanꢀbeꢀplacedꢀ
betweenꢀTDIꢀandꢀTDOꢀpins.ꢀThisꢀallowsꢀdataꢀtoꢀbeꢀshiftedꢀ
throughꢀtheꢀSRAMꢀwithꢀminimalꢀdelay.ꢀTheꢀbypassꢀreg-
isterꢀisꢀsetꢀLOWꢀ(Vss)ꢀwhenꢀtheꢀBYPASSꢀinstructionꢀisꢀ
executed.
IDENTIFICATION REgISTER DEFINITIONS
Instruction Field
Description
1M x 36
xxxxꢀ
2M x 18
xxxxꢀ
RevisionꢀNumberꢀ (31:28)ꢀꢀ
DeviceꢀDepthꢀ (27:23)ꢀ
DeviceꢀWidthꢀ (22:18)ꢀ
ISSIꢀDeviceꢀIDꢀ (17:12)ꢀ
ISSIꢀJEDECꢀIDꢀ (11:1)ꢀ
IDꢀRegisterꢀPresenceꢀ (0)ꢀ
Reservedꢀforꢀversionꢀnumber.ꢀ
DefinesꢀdepthꢀofꢀSRAM.ꢀ1Mꢀorꢀ2Mꢀ
DefinesꢀwidthꢀofꢀtheꢀSRAM.ꢀx36ꢀorꢀx18ꢀ
Reservedꢀforꢀfutureꢀuse.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
01001ꢀ
00100ꢀ
xxxxxꢀ
01010ꢀ
00011ꢀ
xxxxxꢀ
AllowsꢀuniqueꢀidentificationꢀofꢀSRAMꢀvendor.ꢀ
IndicateꢀtheꢀpresenceꢀofꢀanꢀIDꢀregister.ꢀ
00001010101ꢀ
1ꢀ
00001010101
1ꢀ
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
The
TAPꢀcontrollerꢀrecognizesꢀanꢀall-0ꢀinstruction.Whenꢀanꢀ
Eightꢀinstructionsꢀareꢀpossibleꢀwithꢀtheꢀthree-bitꢀinstructionꢀ
registerꢀandꢀallꢀcombinationsꢀareꢀlistedꢀinꢀtheꢀInstructionꢀ
SAMPLE/PRELOADꢀisꢀaꢀ1149.1ꢀmandatoryꢀinstruction.Theꢀ
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TAP INSTRUCTION SET
SAMPLE/PRELOAD
PRELOADꢀportionꢀofꢀthisꢀinstructionꢀisꢀnotꢀimplemented,ꢀsoꢀ
theꢀTAPꢀcontrollerꢀisꢀnotꢀfullyꢀ1149.1ꢀcompliant.ꢀWhenꢀtheꢀ
SAMPLE/PRELOADꢀinstructionꢀisꢀloadedꢀtoꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀtheꢀCapture-DRꢀ
state,ꢀaꢀsnapshotꢀofꢀdataꢀonꢀtheꢀinputsꢀandꢀoutputꢀpinsꢀisꢀ
capturedꢀinꢀtheꢀboundaryꢀscanꢀregister.
Codeꢀtable.ꢀThreeꢀinstructionsꢀareꢀlistedꢀasꢀRESERVED
ꢀ
andꢀshouldꢀnotꢀbeꢀusedꢀandꢀtheꢀotherꢀfiveꢀinstructionsꢀareꢀ
describedꢀbelow.ꢀTheꢀTAPꢀcontrollerꢀusedꢀinꢀthisꢀSRAMꢀ
isꢀnotꢀfullyꢀcompliantꢀwithꢀtheꢀ1149.1ꢀconventionꢀbecauseꢀ
someꢀmandatoryꢀinstructionsꢀareꢀnotꢀfullyꢀimplemented.ꢀ
TheꢀTAPꢀcontrollerꢀcannotꢀbeꢀusedꢀtoꢀloadꢀaddress,ꢀdataꢀorꢀ
controlꢀsignalsꢀandꢀcannotꢀpreloadꢀtheꢀInputꢀorꢀOutputꢀbuf-
fers.ꢀTheꢀSRAMꢀdoesꢀnotꢀimplementꢀtheꢀ1149.1ꢀcommandsꢀ
EXTESTꢀorꢀINTESTꢀorꢀtheꢀPRELOADꢀportionꢀofꢀSAMPLE/
PRELOAD;ꢀinsteadꢀitꢀperformsꢀaꢀcaptureꢀofꢀtheꢀInputsꢀandꢀ
Outputꢀringꢀwhenꢀtheseꢀinstructionsꢀareꢀexecuted.ꢀInstruc-
tionsꢀareꢀloadedꢀintoꢀtheꢀTAPꢀcontrollerꢀduringꢀtheꢀShift-IRꢀ
stateꢀwhenꢀtheꢀinstructionꢀregisterꢀisꢀplacedꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀDuringꢀthisꢀstate,ꢀinstructionsꢀareꢀshiftedꢀfromꢀ
theꢀinstructionꢀregisterꢀthroughꢀtheꢀTDIꢀandꢀTDOꢀpins.ꢀToꢀ
executeꢀanꢀinstructionꢀonceꢀitꢀisꢀshiftedꢀin,ꢀtheꢀTAPꢀcontrol-
lerꢀmustꢀbeꢀmovedꢀintoꢀtheꢀUpdate-IRꢀstate.
ItꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀtheꢀTAPꢀcontrollerꢀclockꢀoper-
atesꢀatꢀaꢀfrequencyꢀupꢀtoꢀ10ꢀMHz,ꢀwhileꢀtheꢀSRAMꢀclockꢀ
runsꢀmoreꢀthanꢀanꢀorderꢀofꢀmagnitudeꢀfaster.ꢀBecauseꢀofꢀ
theꢀclockꢀfrequencyꢀdifferences,ꢀitꢀisꢀpossibleꢀthatꢀduringꢀ
theꢀCapture-DRꢀstate,ꢀanꢀinputꢀorꢀoutputꢀwillꢀunder-goꢀaꢀ
transition.ꢀTheꢀTAPꢀmayꢀattemptꢀaꢀsignalꢀcaptureꢀwhileꢀinꢀ
transitionꢀ(metastableꢀstate).Theꢀdeviceꢀwillꢀnotꢀbeꢀharmed,ꢀ
butꢀthereꢀisꢀnoꢀguaranteeꢀofꢀtheꢀvalueꢀthatꢀwillꢀbeꢀcapturedꢀ
orꢀrepeatableꢀresults.
Toꢀguaranteeꢀthatꢀtheꢀboundaryꢀscanꢀregisterꢀwillꢀcaptureꢀ
theꢀcorrectꢀsignalꢀvalue,ꢀtheꢀSRAMꢀsignalꢀmustꢀbeꢀstabilizedꢀ
longꢀenoughꢀtoꢀmeetꢀtheꢀTAPꢀcontroller’sꢀcaptureꢀset-upꢀ
plusꢀholdꢀtimesꢀ(tCsꢀandꢀtCh).ꢀToꢀinsureꢀthatꢀtheꢀSRAMꢀclockꢀ
inputꢀisꢀcapturedꢀcorrectly,ꢀdesignsꢀneedꢀaꢀwayꢀtoꢀstopꢀ(orꢀ
slow)ꢀtheꢀclockꢀduringꢀaꢀSAMPLE/PRELOADꢀinstruction.ꢀ
Ifꢀthisꢀisꢀnotꢀanꢀissue,ꢀitꢀisꢀpossibleꢀtoꢀcaptureꢀallꢀotherꢀ
signalsꢀandꢀsimplyꢀignoreꢀtheꢀvalueꢀofꢀtheꢀCLKꢀcapturedꢀ
inꢀtheꢀboundaryꢀscanꢀregister.
EXTEST
EXTESTꢀisꢀaꢀmandatoryꢀ1149.1ꢀinstructionꢀwhichꢀisꢀtoꢀbeꢀ
executedꢀwheneverꢀtheꢀinstructionꢀregisterꢀisꢀloadedꢀwithꢀ
allꢀ0s.ꢀBecauseꢀEXTESTꢀisꢀnotꢀimplementedꢀinꢀtheꢀTAPꢀ
controller,ꢀthisꢀdeviceꢀisꢀnotꢀ1149.1ꢀstandardꢀcompliant.ꢀ
Onceꢀtheꢀdataꢀisꢀcaptured,ꢀitꢀisꢀpossibleꢀtoꢀshiftꢀoutꢀtheꢀdataꢀ
byꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀShift-DRꢀstate.ꢀThisꢀplacesꢀtheꢀ
boundaryꢀscanꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpins.
EXTESTꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregister,ꢀ
theꢀSRAMꢀrespondsꢀasꢀifꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ
hasꢀbeenꢀloaded.ꢀThereꢀisꢀaꢀdifferenceꢀbetweenꢀtheꢀinstruc-
tions,ꢀunlikeꢀtheꢀSAMPLE/PRELOADꢀinstruction,ꢀEXTESTꢀ
placesꢀtheꢀSRAMꢀoutputsꢀinꢀaꢀHigh-Zꢀstate.
NoteꢀthatꢀsinceꢀtheꢀPRELOADꢀpartꢀofꢀtheꢀcommandꢀisꢀnotꢀ
implemented,ꢀputtingꢀtheꢀTAPꢀintoꢀtheꢀUpdateꢀtoꢀtheꢀUpdate-
DRꢀstateꢀwhileꢀperformingꢀaꢀSAMPLE/PRELOADꢀinstructionꢀ
willꢀhaveꢀtheꢀsameꢀeffectꢀasꢀtheꢀPause-DRꢀcommand.
IDCODE
Theꢀ IDCODEꢀ instructionꢀ causesꢀ aꢀ vendor-specific,ꢀ 32-
bitꢀcodeꢀtoꢀbeꢀloadedꢀintoꢀtheꢀinstructionꢀregister.ꢀItꢀalsoꢀ
placesꢀtheꢀinstructionꢀregisterꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pinsꢀandꢀallowsꢀtheꢀIDCODEꢀtoꢀbeꢀshiftedꢀoutꢀofꢀtheꢀdeviceꢀ
whenꢀtheꢀTAPꢀcontrollerꢀentersꢀtheꢀShift-DRꢀstate.ꢀTheꢀ
IDCODEꢀinstructionꢀisꢀloadedꢀintoꢀtheꢀinstructionꢀregisterꢀ
uponꢀpower-upꢀorꢀwheneverꢀtheꢀTAPꢀcontrollerꢀisꢀgivenꢀaꢀ
testꢀlogicꢀresetꢀstate.
BYPASS
WhenꢀtheꢀBYPASSꢀinstructionꢀisꢀloadedꢀinꢀtheꢀinstruc-
tionꢀregisterꢀandꢀtheꢀTAPꢀisꢀplacedꢀinꢀaꢀShift-DRꢀstate,ꢀ
theꢀbypassꢀregisterꢀisꢀplacedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀ
pins.ꢀTheꢀadvantageꢀofꢀtheꢀBYPASSꢀinstructionꢀisꢀthatꢀitꢀ
shortensꢀtheꢀboundaryꢀscanꢀpathꢀwhenꢀmultipleꢀdevicesꢀ
areꢀconnectedꢀtogetherꢀonꢀaꢀboard.
SAMPLE-Z
RESERVED
Theꢀ SAMPLE-Zꢀ instructionꢀ causesꢀ theꢀ boundaryꢀ scanꢀ
registerꢀtoꢀbeꢀconnectedꢀbetweenꢀtheꢀTDIꢀandꢀTDOꢀpinsꢀ
whenꢀtheꢀTAPꢀcontrollerꢀisꢀinꢀaꢀShift-DRꢀstate.ꢀItꢀalsoꢀplacesꢀ
allꢀSRAMꢀoutputsꢀintoꢀaꢀHigh-Zꢀstate.
Theseꢀinstructionsꢀareꢀnotꢀimplementedꢀbutꢀareꢀreservedꢀ
forꢀfutureꢀuse.ꢀDoꢀnotꢀuseꢀtheseꢀinstructions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
23
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
INSTRUCTION CODES
Code
Instruction
Description
000ꢀ
EXTESTꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbe-
tweenꢀtheꢀTDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputsꢀtoꢀHigh-Zꢀstate.ꢀThisꢀꢀ
instructionꢀisꢀnotꢀ1149.1ꢀcompliant.
001ꢀ
010ꢀ
IDCODEꢀ
LoadsꢀtheꢀIDꢀregisterꢀwithꢀtheꢀvendorꢀIDꢀcodeꢀandꢀplacesꢀtheꢀregisterꢀbetweenꢀTDIꢀ
andꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀaffectꢀSRAMꢀoperation.
SAMPLE-Zꢀ
CapturesꢀtheꢀInput/Outputꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀbetweenꢀ
TDIꢀandꢀTDO.ꢀForcesꢀallꢀSRAMꢀoutputꢀdriversꢀtoꢀaꢀHigh-Zꢀstate.
011ꢀ
100ꢀ
RESERVEDꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
SAMPLE/PRELOAD
ꢀ
CapturesꢀtheꢀInput/Outputꢀringꢀcontents.ꢀPlacesꢀtheꢀboundaryꢀscanꢀregisterꢀ
betweenꢀTDIꢀandꢀTDO.ꢀDoesꢀnotꢀaffectꢀtheꢀSRAMꢀoperation.ꢀThisꢀinstructionꢀdoesꢀnotꢀ
implementꢀ1149.1ꢀpreloadꢀfunctionꢀandꢀisꢀthereforeꢀnotꢀ1149.1ꢀcompliant.
101ꢀ
110ꢀꢀ
111ꢀ
RESERVEDꢀ
RESERVEDꢀ
BYPASSꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.ꢀꢀ
DoꢀNotꢀUse:ꢀThisꢀinstructionꢀisꢀreservedꢀforꢀfutureꢀuse.
PlacesꢀtheꢀbypassꢀregisterꢀbetweenꢀTDIꢀandꢀTDO.ꢀThisꢀoperationꢀdoesꢀnotꢀ
affectꢀSRAMꢀoperation.
TAP CONTROLLER STATE DIAgRAM
Test Logic Reset
1
0
1
1
1
Run Test/Idle
Select DR
0
Select IR
0
0
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
0
1
0
1
Update DR
0
Update IR
0
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TAP Electrical Characteristics (Vddq = 3.3V Operating Range)
Symbol
VOh1
VOh2
VOl1
VOl2
Vih
Parameter
Test Conditions
IOh = -4 mA
Min.
2.4
2.9
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOh = -100 µA
IOl = 8 mA
—
V
0.4
V
IOl = 100 µA
—
0.2
V
2.0
–0.3
–30
Vdd+0.3
0.8
V
Vil
V
Ix
Vss ≤ Vin ≤ Vddq
30
mA
TAP Electrical Characteristics (Vddq = 2.5V Operating Range)
Symbol
VOh1
VOh2
VOl1
VOl2
Vih
Parameter
Test Conditions
IOh = -1 mA
Min.
2.0
2.1
—
Max.
—
Units
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOh = -100 µA
IOl = 1 mA
—
V
0.4
V
IOl = 100 µA
—
0.2
V
1.7
-0.3
–30
Vdd+0.3
0.7
V
Vil
V
Ix
Vss ≤ Vin ≤ Vddq
30
mA
TAP Electrical Characteristics (Vddq = 1.8V Operating Range)
Symbol
VOh1
VOl1
Vih
Parameter
Test Conditions
IOh = -1 mA
Min.
Vdd -0.4
—
Max.
—
Units
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOl = 1 mA
0.5
V
1.3
Vdd +0.3
0.7
V
Vil
-0.3
V
Ix
Vss ≤ V I ≤ Vddq
-30
30
mA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
25
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
TAP AC ELECTRICAL CHARACTERISTICS(OꢀER OPERATINꢁ RANꢁE)
Parameter
Symbol
tTHTH
tTHTL
Min
100
40
40
10
10
10
10
–
Max
–
Units
ns
TCK cycle time
TCK high pulse width
TCK low pulse width
TMS Setup
–
ns
tTLTH
–
ns
tMVTH
tTHMX
tDVTH
tTHDX
tTLOV
–
ns
TMS Hold
–
ns
TDI Setup
–
ns
TDI Hold
–
ns
TCK Low to Valid Data
20
ns
TAP AC TEST CONDITIONS (1.8V/2.5V/3.3V)
Inputꢀpulseꢀlevelsꢀ
0ꢀtoꢀ1.8V/0ꢀtoꢀ2.5V/0ꢀtoꢀ3.0V
TAP Output Load Equivalent
Inputꢀriseꢀandꢀfallꢀtimesꢀ
Inputꢀtimingꢀreferenceꢀlevelsꢀ
Outputꢀreferenceꢀlevelsꢀ
Testꢀloadꢀterminationꢀsupplyꢀvoltageꢀ
Vtrigꢀ
1.5ns
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
50Ω
Vtrig
TDO
20 pF
GND
Z0
= 50Ω
TAP TIMINg
1
2
3
4
5
6
tTHTH
tTLTH
TCK
TMS
tTHTL
t
t
MVTH THMX
t
DVTH
tTHDX
TDI
tTLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BOUNDARY SCAN ORDER
165 BꢁA
119 BꢁA
X36
X36
Bump ID
X18
Bump ID
X18
Bump ID
Bit #
1
Signal
A9
Signal
A9
NC
NC
A8
A18
A17
A16
A15
A14
A13
A12
ZZ
Bit #
1
2
3
4
5
6
7
8
Bump ID
C7
R5
R7
U6
B5
C6
T3
T4
T5
T6
R6
T7
P6
N7
M6
L7
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
ZZ
DQa0
DQa1
DQa2
DQa6
DQa7
DQa3
DQa4
DQa5
DQa8
NC
Signal
NC
N6
N7
N10
P11
P8
R8
R9
P9
N6
N7
N10
P11
P8
R8
R9
P9
C7
R5
R7
U6
B5
C6
T3
T4
T5
T6
R6
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
-
2
3
4
5
6
7
8
9
NC
NC
A8
A18
A17
A16
A15
A14
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
ZZ
NC
NC
NC
NC
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A13
A12
ZZ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DQa0
DQa1
DQa2
DQa6
DQa7
DQa3
DQa4
DQa5
DQa8
NC
NC
NC
NC
NC
NC
K6
P7
N6
L6
K7
-
NC
DQa8
DQa7
DQa6
DQa5
NC
DQa8
DQa7
DQa6
DQa5
NC
NC
NC
-
NC
-
NC
DQb8
DQb7
DQb5
DQb4
DQb6
DQb3
DQb2
DQb1
DQb0
NC
DQa4
DQa3
DQa2
DQa1
NC
NC
NC
NC
H6
G7
F6
E7
H7
G6
E6
D7
D6
T1
R1
A6
A5
G4
A4
B7
B4
F4
M4
H4
K4
DQb8
DQb7
DQb5
DQb4
DQb6
DQb3
DQb2
DQb1
DQb0
NC
H6
G7
F6
E7
H7
G6
E6
D7
D6
T1
R1
A6
A5
G4
A4
B7
B4
F4
M4
H4
K4
DQa4
DQa3
DQa2
DQa1
NC
NC
NC
NC
DQa0
NC
DQa0
A20
NC
NC
A11
A10
NC
A11
A10
NC
A11
A11
A10
/ADV
/ADSP
NC
/ADSC
/OE
/BWE
/GW
CLK
A10
/ADV
/ADSP
NC
/ADSC
/OE
/BWE
/GW
CLK
/ADV
/ADSP
NC
/ADSC
/OE
/BWE
/GW
CLK
/ADV
/ADSP
NC
/ADSC
/OE
/BWE
/GW
CLK
B9
C10
A8
B8
A7
B9
C10
A8
B8
A7
B7
B6
B7
B6
Continued on next page
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
27
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165 BꢁA
119 BꢁA
X36
X36
Bump ID
X18
Bump ID
X18
Bump ID
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Signal
/CE2
/Bwa
/Bwb
/Bwc
/Bwd
CE2
/CE1
A7
Signal
/CE2
/Bwa
NC
/Bwb
NC
CE2
/CE1
A7
A6
NC
NC
NC
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Bump ID
B6
L5
G5
G3
L3
B2
E4
A3
A2
B1
C1
D4
D2
E1
F2
G1
H2
D1
E2
G2
H1
-
Signal
A9
Signal
A9
/Bwa
NC
/Bwb
NC
A8
/CE1
A7
A6
NC
NC
NC
NC
NC
NC
NC
NC
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H2
H3
J1
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H2
H3
J1
B6
L5
G5
G3
L3
B2
E4
A3
A2
B1
C1
D4
D2
E1
F2
G1
H2
D1
E2
G2
H1
-
/Bwa
/Bwb
/Bwc
/Bwd
A8
/CE1
A7
A6
A6
NC
NC
NC
NC
NC
NC
DQc0
DQc1
DQc2
DQc6
DQc7
DQc3
DQc4
DQc5
DQc8
NC
NC
NC
NC
NC
DQc0
DQc1
DQc2
DQc6
DQc7
DQc3
DQc4
DQc5
DQc8
NC
NC
DQb8
DQb7
DQb6
DQb5
NC
DQb8
DQb7
DQb6
DQb5
NC
NC
NC
NC
NC
-
-
NC
NC
-
-
NC
NC
DQd8
DQd7
DQd5
DQd4
DQd6
DQd3
DQd2
DQd1
DQd0
NC
NC
MODE
A5
A4
A3
NC
A19
A2
NC
A1
A0
Int
DQb4
DQb3
DQb2
DQb1
NC
NC
NC
NC
DQb0
NC
NC
MODE
A5
A4
A3
NC
A19
A2
NC
A1
K2
L1
M2
N1
K1
L2
N2
P1
P2
L4
J5
R3
C2
B3
C3
R2
C5
T2
J3
DQd8
DQd7
DQd5
DQd4
DQd6
DQd3
DQd2
DQd1
DQd0
NC
NC
MODE
A4
A3
A2
A5
A19
NC
NC
A1
A0
Int
K2
L1
M2
N1
K1
L2
N2
P1
P2
L4
J5
R3
C2
B3
C3
R2
C5
T2
J3
N4
P4
*
DQb4
DQb3
DQb2
DQb1
NC
NC
NC
NC
DQb0
NC
NC
MODE
A4
A3
A2
K1
L1
M1
J2
K1
L1
M1
J2
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
*
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
*
A5
A19
A20
NC
A1
A0
N4
P4
*
A0
Int
Int
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
ORDERINg INFORMATION
Commercial Ranꢀe: 0°C to 70°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed
x36
x18
Package
250MHz
IS61LPS102436B-250TQ
IS61LPS102436B-250B3
IS61LPS102436B-250B2
IS61LPS102436B-250TQL
IS61LPS102436B-250B3L
IS61LPS102436B-250B2L
IS61LPS102436B-200TQ
IS61LPS102436B-200B3
IS61LPS102436B-200B2
IS61LPS102436B-200TQL
IS61LPS102436B-200B3L
IS61LPS102436B-200B2L
IS61LPS102436B-166TQ
IS61LPS102436B-166B3
IS61LPS102436B-166B2
IS61LPS102436B-166TQL
IS61LPS102436B-166B3L
IS61LPS102436B-166B2L
IS61LPS204818B-250TQ
IS61LPS204818B-250B3
IS61LPS204818B-250B2
IS61LPS204818B-250TQL
IS61LPS204818B-250B3L
IS61LPS204818B-250B2L
IS61LPS204818B-200TQ
IS61LPS204818B-200B3
IS61LPS204818B-200B2
IS61LPS204818B-200TQL
IS61LPS204818B-200B3L
IS61LPS204818B-200B2L
IS61LPS204818B-166TQ
IS61LPS204818B-166B3
IS61LPS204818B-166B2
IS61LPS204818B-166TQL
IS61LPS204818B-166B3L
IS61LPS204818B-166B2L
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
200MHz
166MHz
Commercial Ranꢀe: 0°C to 70°C (VDD = 2.5V / VDDQ = 2.5V)
Speed
x36
x18
Package
250MHz
IS61VPS102436B-250TQ
IS61VPS102436B-250B3
IS61VPS102436B-250B2
IS61VPS102436B-250TQL
IS61VPS102436B-250B3L
IS61VPS102436B-250B2L
IS61VPS102436B-200TQ
IS61VPS102436B-200B3
IS61VPS102436B-200B2
IS61VPS102436B-200TQL
IS61VPS102436B-200B3L
IS61VPS102436B-200B2L
IS61VPS102436B-166TQ
IS61VPS102436B-166B3
IS61VPS102436B-166B2
IS61VPS102436B-166TQL
IS61VPS102436B-166B3L
IS61VPS102436B-166B2L
IS61VPS204818B-250TQ
IS61VPS204818B-250B3
IS61VPS204818B-250B2
IS61VPS204818B-250TQL
IS61VPS204818B-250B3L
IS61VPS204818B-250B2L
IS61VPS204818B-200TQ
IS61VPS204818B-200B3
IS61VPS204818B-200B2
IS61VPS204818B-200TQL
IS61VPS204818B-200B3L
IS61VPS204818B-200B2L
IS61VPS204818B-166TQ
IS61VPS204818B-166B3
IS61VPS204818B-166B2
IS61VPS204818B-166TQL
IS61VPS204818B-166B3L
IS61VPS204818B-166B2L
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
200MHz
166MHz
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
29
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Commercial Ranꢀe: 0°C to 70°C (VDD = 1.8V / VDDQ = 1.8V)
Speed
x36
x18
Package
200MHz
Please contat ISSI (SRAM@issi.com)
166MHz
IS61VVPS102436B-166TQ
IS61VVPS102436B-166B3
IS61VVPS102436B-166B2
IS61VVPS102436B-166TQL
IS61VVPS102436B-166B3L
IS61VVPS102436B-166B2L
IS61VVPS204818B-166TQ
IS61VVPS204818B-166B3
IS61VVPS204818B-166B2
IS61VVPS204818B-166TQL
IS61VVPS204818B-166B3L
IS61VVPS204818B-166B2L
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
Industrial Ranꢀe: -40°C to +85°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed
x36
x18
Package
250MHz
IS61LPS102436B-250TQI
IS61LPS102436B-250B3I
IS61LPS102436B-250B2I
IS61LPS102436B-250TQLI
IS61LPS102436B-250B3LI
IS61LPS102436B-250B2LI
IS61LPS102436B-200TQI
IS61LPS102436B-200B3I
IS61LPS102436B-200B2I
IS61LPS102436B-200TQLI
IS61LPS102436B-200B3LI
IS61LPS102436B-200B2LI
IS61LPS102436B-166TQI
IS61LPS102436B-166B3I
IS61LPS102436B-166B2I
IS61LPS102436B-166TQLI
IS61LPS102436B-166B3LI
IS61LPS102436B-166B2LI
IS61LPS204818B-250TQI
IS61LPS204818B-250B3I
IS61LPS204818B-250B2I
IS61LPS204818B-250TQLI
IS61LPS204818B-250B3LI
IS61LPS204818B-250B2LI
IS61LPS204818B-200TQI
IS61LPS204818B-200B3I
IS61LPS204818B-200B2I
IS61LPS204818B-200TQLI
IS61LPS204818B-200B3LI
IS61LPS204818B-200B2LI
IS61LPS204818B-166TQI
IS61LPS204818B-166B3I
IS61LPS204818B-166B2I
IS61LPS204818B-166TQLI
IS61LPS204818B-166B3LI
IS61LPS204818B-166B2LI
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
200MHz
166MHz
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Industrial Ranꢀe: -40°C to +85°C (VDD = 2.5V / VDDQ = 2.5V)
Speed
x36
x18
Package
250MHz
IS61VPS102436B-250TQI
IS61VPS102436B-250B3I
IS61VPS102436B-250B2I
IS61VPS102436B-250TQLI
IS61VPS102436B-250B3LI
IS61VPS102436B-250B2LI
IS61VPS102436B-200TQI
IS61VPS102436B-200B3I
IS61VPS102436B-200B2I
IS61VPS102436B-200TQLI
IS61VPS102436B-200B3LI
IS61VPS102436B-200B2LI
IS61VPS102436B-166TQI
IS61VPS102436B-166B3I
IS61VPS102436B-166B2I
IS61VPS102436B-166TQLI
IS61VPS102436B-166B3LI
IS61VPS102436B-166B2LI
IS61VPS204818B-250TQI
IS61VPS204818B-250B3I
IS61VPS204818B-250B2I
IS61VPS204818B-250TQLI
IS61VPS204818B-250B3LI
IS61VPS204818B-250B2LI
IS61VPS204818B-200TQI
IS61VPS204818B-200B3I
IS61VPS204818B-200B2I
IS61VPS204818B-200TQLI
IS61VPS204818B-200B3LI
IS61VPS204818B-200B2LI
IS61VPS204818B-166TQI
IS61VPS204818B-166B3I
IS61VPS204818B-166B2I
IS61VPS204818B-166TQLI
IS61VPS204818B-166B3LI
IS61VPS204818B-166B2LI
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
200MHz
166MHz
Industrial Ranꢀe: -40°C to +85°C (VDD = 1.8V / VDDQ = 1.8V)
Speed
x36
x18
Package
200MHz
IS61VVPS102436B-200TQLI
IS61VVPS102436B-200B3LI
IS61VVPS102436B-166TQI
IS61VVPS102436B-166B3I
IS61VVPS102436B-166B2I
IS61VVPS102436B-166TQLI
IS61VVPS102436B-166B3LI
IS61VVPS102436B-166B2LI
IS61VVPS204818B-200TQLI
IS61VVPS204818B-200B3LI
IS61VVPS204818B-166TQI
IS61VVPS204818B-166B3I
IS61VVPS204818B-166B2I
IS61VVPS204818B-166TQLI
IS61VVPS204818B-166B3LI
IS61VVPS204818B-166B2LI
100 QFP, Lead-free
165 BGA, Lead-free
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
166MHz
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
31
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Automotive(A3) Ranꢀe: -40°C to +125°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Speed
x36
x18
Package
200MHz
Please contact ISSI (SRAM@issi.com)
166MHz
IS64LPS102436B-166TQA3
IS64LPS102436B-166B3A3
IS64LPS102436B-166B2A3
IS64LPS102436B-166TQLA3
IS64LPS102436B-166B3LA3
IS64LPS102436B-166B2LA3
IS64LPS204818B-166TQA3
IS64LPS204818B-166B3A3
IS64LPS204818B-166B2A3
IS64LPS204818B-166TQLA3
IS64LPS204818B-166B3LA3
IS64LPS204818B-166B2LA3
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
Automotive(A3) Ranꢀe: -40°C to +125°C (VDD = 2.5V / VDDQ = 2.5V)
Speed
x36
x18
Package
200MHz
Please contact ISSI (SRAM@issi.com)
166MHz
IS64VPS102436B-166TQA3
IS64VPS102436B-166B3A3
IS64VPS102436B-166B2A3
IS64VPS102436B-166TQLA3
IS64VPS102436B-166B3LA3
IS64VPS102436B-166B2LA3
IS64VPS204818B-166TQA3
IS64VPS204818B-166B3A3
IS64VPS204818B-166B2A3
IS64VPS204818B-166TQLA3
IS64VPS204818B-166B3LA3
IS64VPS204818B-166B2LA3
100 QFP
165 BGA
119 BGA
100 QFP, Lead-free
165 BGA, Lead-free
119 BGA, Lead-free
Automotive(A3) Ranꢀe: -40°C to +125°C (VDD = 1.8V / VDDQ = 1.8V)
Speed
x36
x18
Package
Please contact ISSI MKT (SRAM@issi.com)
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
33
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
35
Rev. C
11/03/2017
相关型号：
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ISSI
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ISSI
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128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
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IS64LPS25618EC-200B3LA3
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IS64LPS25618EC-200TQA3
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
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128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
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128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
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128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
ISSI
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