IS66WV25616BLL-55TLI [ISSI]
Pseudo Static RAM, 256KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | IS66WV25616BLL-55TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Pseudo Static RAM, 256KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 光电二极管 |
| 文件： | 总16页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fabricatedusingISSI's
high-performance
CMOStechnology.ꢀ
IS66WV25616ALL
IS66WV25616BLL
4Mb LOW VOLTAGE,
ULTRA LOW POWER PSEUDO CMOS STATIC RAM
PRELIMINARY INFORMATION
JANUARY 2008
FEATURES
DESCRIPTION
•ꢀ High-speedꢀaccessꢀtime:ꢀꢀ55ns
•ꢀ CMOSꢀlowꢀpowerꢀoperation
– mW (typical) operating
Theꢀ ISSIꢀ IS66WV25616ALL/BLLꢀ isꢀ aꢀ high-speed,ꢀ 4Mꢀ
bitꢀstaticꢀRAMsꢀorganizedꢀasꢀ256Kꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀ
Thisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀinnovativeꢀcircuitꢀ
designꢀtechniques,ꢀyieldsꢀhigh-performanceꢀandꢀlowꢀpowerꢀ
consumption devices.
ꢀ –ꢀꢀµWꢀ(typical)ꢀCMOSꢀstandby
•ꢀ Singleꢀpowerꢀsupplyꢀꢀ
When CS1ꢀisꢀHIGHꢀ(deselected)ꢀorꢀwhenꢀCS2ꢀisꢀLOW
(deselected) or both LB and UBꢀareꢀHIGH,ꢀtheꢀdeviceꢀ
assumes a standby mode at which the power dissipation
canꢀbeꢀreducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.
ꢀ –ꢀ1.7V--1.95VꢀVd d (66WV25616ALL) (70ns)
ꢀ –ꢀ2.5V--3.6VꢀVd d (66WV25616BLL) (55ns)
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ Industrialꢀtemperatureꢀavailableꢀ
•ꢀ Lead-freeꢀavailableꢀ
Easy memory expansion is provided by using Chip Enable
andꢀOutputꢀEnableꢀinputs.ꢀTheꢀactiveꢀLOWꢀWriteꢀEnableꢀ
(WE) controls both writing and reading of the memory. A
dataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀByteꢀ(LB)
access.
TheꢀIS66WV25616ALL/BLLꢀisꢀpackagedꢀinꢀtheꢀJEDECꢀ
standardꢀ48-pinꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀandꢀ44-PinꢀTSOPꢀ
(TYPEꢀII).ꢀTheꢀdeviceꢀisꢀasloꢀavailableꢀforꢀdieꢀsales.
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1
OE
CONTROL
CIRCUIT
WE
UB
LB
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
PIN CONFIGURATIONS: 256K x 16
48-Pin mini BGA (6mm x 8mm)
44-Pin TSOP (Type II)
1
2
3
4
5
6
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
2
3
4
5
A0
A3
A1
A4
A2
LB
OE
UB
CS2
A
B
C
D
E
F
6
7
I/O
8
CS1
I/O
0
8
9
I/O
I/O
A5
A6
I/O
1
I/O
2
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
GND
A17
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
VDD`
11
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
VDD
GND
VDD
A16
A15
A13
A10
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
12
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A17ꢀ ꢀ
I/O0-I/O15ꢀ
CS1, CS2
AddressꢀInputs
DataꢀInputs/Outputs
Chip Enable Input
OutputꢀEnableꢀInput
Write Enable Input
OEꢀꢀ
WE
ꢀ
LBꢀ
ꢀ
ꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
No Connection
UBꢀ
NC
Vd d ꢀ
GNDꢀ
ꢀ
ꢀ
Power
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
TRUTH TABLE
I/O PIN
I/O0-I/O7 I/O8-I/O15 Vd d Current
Mode
WE CS1 CS2
OE
LB
UB
NotꢀSelectedꢀ
ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
Is B 1, Is B 2
Is B 1, Is B 2
Is B 1, Is B 2
ꢀ
ꢀ
OutputꢀDisabledꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
Ic c
Ic c
ꢀ
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
do u t ꢀ
High-Zꢀ
do u t
High-Z
do u t
do u t
Ic c
ꢀ
ꢀ
Writeꢀ
ꢀ
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
dInꢀ
High-Zꢀ
dIn
High-Z
dIn
dIn
Ic c
OPERATING RANGE (Vd d )
Range
Ambient Temperature
(70ns)
(55ns)
2.5Vꢀ-ꢀ3.6Vꢀ
ꢀ2.5Vꢀ-ꢀ3.6V
ꢀ
(70ns)
Commercialꢀ 0°Cꢀtoꢀ+70°Cꢀ
1.7Vꢀ-ꢀ1.95Vꢀ
Industrialꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+105°Cꢀ
1.7Vꢀ-ꢀ1.95Vꢀ
ꢀ
ꢀ Automotiveꢀ
2.5V-3.6Vꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
3
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vt e r m
tB IA s
Vd d
Parameter
Value
–0.2ꢀtoꢀVd d +0.3ꢀ
–40ꢀtoꢀ+85ꢀ
–0.2ꢀtoꢀ+3.8ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
TemperatureꢀUnderꢀBiasꢀ
Vd d RelatedꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
°C
V
ts t g
°C
W
Pt
Note:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀ
device.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀ
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Vd d
Min.
Max.
Unit
Vo H
Vo L
VIH
OutputꢀHIGHꢀVoltageꢀ
Io H = -0.1ꢀmAꢀ
Io H = -1ꢀmAꢀ
1.7-1.95Vꢀ
2.5-3.6Vꢀ
1.4ꢀ
2.2ꢀ
—ꢀ
—ꢀ
Vꢀ
V
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
Io L = 0.1ꢀmAꢀ
Io L = 2.1ꢀmAꢀ
1.7-1.95Vꢀ
2.5-3.6Vꢀ
—ꢀ
—ꢀ
0.2ꢀ
0.4ꢀ
Vꢀ
V
ꢀ
1.7-1.95Vꢀ
2.5-3.6Vꢀ
1.4ꢀ
2.2ꢀ
Vd d + 0.2
Vd d + 0.3
V
V
(1)
VIL
ꢀ
InputꢀLOWꢀVoltage
ꢀ
ꢀ
ꢀ
1.7-1.95Vꢀ
2.5-3.6Vꢀ
–0.2ꢀ
–0.2ꢀ
0.4ꢀ
0.6ꢀ
Vꢀ
V
ꢀ
IL I
InputꢀLeakageꢀ
OutputꢀLeakage
GNDꢀ≤ VIn ≤ Vd d
–1
1
µA
IL o
GNDꢀ≤ Vo u t ≤ Vd d , OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
CAPACITANCE(1)
Symbol
cIn
Parameter
Conditions
VIn = 0V
Max.
8
Unit
pF
Input Capacitance
Input/OutputꢀCapacitanceꢀ
co u t ꢀ
Vo u t = 0V
10
pF
Note:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
AC TEST CONDITIONS
Parameter
1.7V-1.95V
(Unit)
2.5V-3.6V
(Unit)
0.4VꢀtoꢀVd d -0.3V
5ns
InputꢀPulseꢀLevelꢀ
0.4VꢀtoꢀVd d -0.2ꢀ
5ꢀnsꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
Vr e f
Vr e f
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
1.7V - 1.95V
2.5V - 3.6V
1029
r1(Ω)
R2(Ω)ꢀ
Vr e f
3070ꢀ
3150ꢀ
0.9V
1728
ꢀ
1.4V
Vt m ꢀ
1.8Vꢀ
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
30 pF
R2
5 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
5
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
1.7V-1.95V POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Max.
70ns
Unit
I
c c
V
d d ꢀDynamicꢀOperatingꢀ
V
d d = Max.,ꢀ
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25ꢀ
30ꢀ
mA
ꢀ
ꢀ
Supply Current
ꢀ
I
o u t = 0 mA, f = fm A X
ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀ ꢀ
AllꢀInputsꢀꢀ0.4Vꢀꢀꢀ
or Vd d – 0.2V
Auto.ꢀ
typ.(1)
Ic c 1
OperatingꢀSupplyꢀ
Current
V
d d = Max., CS1 = 0.2Vꢀ
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
4
mA
WE = Vd d – 0.2V
CS2 = Vd d – 0.2V, f = 1m H z Auto.
10
I
ꢀ ꢀ
s B 1
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
V
d d = Max.,
Com.
Ind.
0.6
0.6
1
mA
V
In = VIH or VIL
CS1 = VIH , CS2 = VIL
,
Au t o
.
fꢀ=ꢀ1ꢀMH
z
OR
ꢀ ꢀ
ULBꢀControlꢀ
V
d d ꢀ=ꢀMax.,ꢀVIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
I
ꢀ ꢀ
s B 2ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CS1
V
d d = Max.,ꢀ
d d – 0.2V,
Com.
Ind.
100
120
150
µA
≥ V
CS2 ≤ꢀꢀ0.2V,ꢀ
V
V
Auto.ꢀ
ꢀ
ꢀ
In
In
≥
≤
V
d d – 0.2V, or
typ.(1)
0.2V, f = 0
OR
ꢀ ꢀ
ULBꢀControlꢀ
Vd d ꢀ=ꢀMax.,ꢀCS1 = VIL, cs2=VIH
0.2V, f = 0;
VIn
≥
V
d d – 0.2V, or VIn
≤
UB / LB = Vd d – 0.2V
Note:.
1.ꢀꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVd d ꢀ=ꢀ1.8V,ꢀTAꢀ=ꢀ25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
2.5V-3.6V POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Max.
55ns
Unit
I
c c
c c
V
d d DynamicꢀOperatingꢀ
V
d d = Max.,ꢀ
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
28ꢀ
35ꢀ
15
ꢀ
ꢀ
ꢀ
mA
ꢀ
ꢀ
Supply Current
I
o u t = 0 mA, f = fm A X
ꢀꢀ
ꢀꢀ
All Inputs 0.4Vꢀ
or Vd d –ꢀ0.3Vꢀ
Auto.ꢀ
typ.(2)
ꢀ
I
1
OperatingꢀSupplyꢀ
Current
Vd d = Max., CS1 = 0.2Vꢀ Com.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
5ꢀ
ꢀ
ꢀ
mA
WE = Vd d – 0.2V
Ind.ꢀ
CS2 = Vd d – 0.2V, f = 1m H z
A
u t o
.
10
I
ꢀ ꢀ
s B 1
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
V
d d = Max.,
Com.
Ind.
0.6
0.6
1
mA
VIn = VIH or VIL
CS1 = VIH , CS2 = VIL
,
Au t o
.
fꢀ=ꢀ1ꢀMH
z
OR
ꢀ ꢀ
ULBꢀControlꢀ
Vd d ꢀ=ꢀMax.,ꢀVIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
I
ꢀ ꢀ
s B 2ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CS1
V
d d = Max.,ꢀ
d d – 0.2V,
Com.
Ind.
100
130
200
75
µA
≥ V
CS2 ≤ 0.2V,
V
V
Auto.
In
In
≥
≤
V
d d – 0.2V, or
typ.(2)ꢀ
ꢀ
ꢀ
0.2V, f = 0
OR
ꢀ ꢀ
ULBꢀControlꢀ
Vd d ꢀ=ꢀMax.,ꢀCS1 = VIL, cs2=VIH
0.2V, f = 0;
VIn
≥
V
d d – 0.2V, or VIn
≤
UB / LB = Vd d – 0.2V
Note:
1. At f = fm A X , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.ꢀꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVd d ꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
55 ns
70 ns
Symbol
tr c ꢀ
Parameter
Min.
55ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
Max.
—ꢀ
Min.
Max.
—ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ReadꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
70ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
tA A ꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
55ꢀ
—ꢀ
70ꢀ
—ꢀ
to H A ꢀ
tA c s 1/tA c s 2
td o e
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
55ꢀ
25ꢀ
20ꢀ
—ꢀ
70ꢀ
35ꢀ
25ꢀ
—ꢀ
(2)
tH z o e
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
LB, UBꢀAccessꢀTimeꢀ
LB, UBꢀtoꢀHigh-ZꢀOutputꢀ
LB, UBꢀtoꢀLow-ZꢀOutputꢀ
(2)
tL z o e
(2)
tH z c s 1/tH z c s 2
0ꢀ
20ꢀ
—ꢀ
0ꢀ
25ꢀ
—ꢀ
(2)
tL z c s 1/tL z c s 2
10ꢀ
—ꢀ
0ꢀ
10ꢀ
—ꢀ
0ꢀ
tB A
55ꢀ
20ꢀ
—ꢀ
70ꢀ
25ꢀ
—ꢀ
tH z B
tL z B
0ꢀ
0ꢀ
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4ꢀtoꢀ
Vd d -0.2V/0.4VꢀtoꢀVd d -0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±100ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cs2 = WE = VIH, UB or LB = VIL)
tRC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DQ0-D15
PREVIOUS DATA VALID
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE,ꢀANDꢀUB/LB Controlled)
tRC
ADDRESS
OE
tAA
t
OHA
tHZOE
t
DOE
tLZOE
CS1
tACE1/tACE2
CS2
t
LZCE1/
t
LZCE2
t
t
HZCS1/
HZCS1
LB UB
,
tBA
tHZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE, CS1, UB, or LB = VIL. cs2=WE=VIH.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCS1ꢀLOWꢀtransition.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
9
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2)ꢀ(OverꢀOperatingꢀRange)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
—ꢀ
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW c ꢀ
WriteꢀCycleꢀTimeꢀ
ꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀ
55ꢀ
45ꢀ
45ꢀ
0ꢀ
ꢀꢀꢀ70ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀꢀ60ꢀ
ꢀꢀꢀ30ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ—ꢀ
ꢀꢀꢀꢀꢀ5ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
30ꢀ
—ꢀ
ts c s 1/ts c s 2 CS1/CS2ꢀtoꢀWriteꢀEndꢀ
tA W ꢀ
tH A ꢀ
ts A ꢀ
AddressꢀSetupꢀTimeꢀtoꢀWriteꢀEndꢀꢀ ꢀꢀꢀꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀ
0ꢀ
tP W B
tP W e
ts d ꢀ
tH d ꢀ
LB, UBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
WEꢀPulseꢀWidthꢀ
45ꢀ
45ꢀ
25ꢀ
0ꢀ
(4)
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
(3)
tH z W e
—ꢀ
5ꢀ
(3)
tL z W e
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀꢀ0.4ꢀtoꢀ
Vd d -0.2V/0.4VꢀtoꢀVd d -0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2. Theꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀof CS1 LOW,ꢀCS2ꢀHIGHꢀandꢀUB or LB, and WEꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀ
any one can go inactive to terminateꢀtheꢀWrite.ꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀ
write.
3.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±100ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
4.ꢀꢀꢀtP W e > tH z W e + ts d when OEꢀisꢀLOW.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OEꢀ=ꢀHIGHꢀorꢀLOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
t
PWB
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1.ꢀ WRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOWꢀstatesꢀonꢀtheꢀCS1 , CS2 and WE inputs and at
least one of the LB and UBꢀinputsꢀbeingꢀinꢀtheꢀLOWꢀstate.
2.ꢀ WRITEꢀ=ꢀ(CS1) [ (LB) = (UB) ] (WE).
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
WRITE CYCLE NO. 2 (WEꢀControlled:ꢀOEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WEꢀControlled:ꢀOEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
tHA
tSCS1
tSCS2
CS1
CS2
tAW
tPWE
WE
LB, UB
DOUT
DIN
tSA
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DATA-IN VALID
tHD
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESSꢀ1
ADDRESSꢀ2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORDꢀ1
WORDꢀ2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATAꢀUNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
Pleaseꢀavoidꢀaddressꢀchangeꢀforꢀlessꢀthanꢀtr c ꢀduringꢀtheꢀcycleꢀtimeꢀlongerꢀthanꢀ15ꢀmsꢀ(Figureꢀ1).ꢀFigureꢀ2ꢀ&ꢀ3ꢀprovideꢀ
work around solution for this issue.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
13
Rev. 00A
12/20/07
IS66WV25616ALL
IS66WV25616BLL
IS66WV25616ALL
Industrial Range: -40°C to +85°C
Voltage Range: 1.7V to 1.95V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
70ꢀ
ꢀ
IS66WV25616ALL-70TLIꢀ TSOP-II,ꢀLead-freeꢀ
IS66WV25616ALL-70BLIꢀ miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
IS66WV25616BLL
Commercial Range: 0°C to +70°C
Voltage Range: 2.5V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
55ꢀ
ꢀ
IS66WV25616BLL-55TLIꢀ TSOP-II,ꢀLead-freeꢀ
IS66WV25616BLL-55BLIꢀ miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
12/20/07
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
7.90
0.009
0.024
0.311
A1
A2
D
0.24
0.60
9.90
0.009
0.024
0.390
8.10
0.319
10.10
0.398
D1
E
5.25 BSC
—
0.207 BSC
D1
E
5.25 BSC
—
0.207 BSC
5.90
6.10
0.232
—
0.240
7.90
8.10
0.311
—
0.319
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
0.030 BSC
0.030 BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
PACKAGING INFORMATION
PlasticTSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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