IS66WVC2M16ALL-7010BLI [ISSI]
IC PSRAM 32M PARALLEL 54VFBGA;
| 型号： | IS66WVC2M16ALL-7010BLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC PSRAM 32M PARALLEL 54VFBGA 静态存储器 内存集成电路 |
| 文件： | 总67页 (文件大小：1234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS66WVC2M16ALL
32Mb Async/Page/Burst CellularRAM 1.5
Overview
The IS66WVC2M16ALL is an integrated memory device containing 32Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several
power saving modes : Reduced Array Refresh mode where data is retained in a portion of the array and
Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be
operated in a standard asynchronous mode and high performance burst mode. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Single device supports asynchronous , page,
and burst operation
Mixed Mode supports asynchronous write and
synchronous read operation
Low Power Consumption
Asynchronous Operation < 25 mA
Intrapage Read < 18mA
Burst operation < 35 mA (@104Mhz)
Standby < 150 uA(max.)
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Asynchronous mode read access : 70ns
Interpage Read access : 70ns
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Reduced Array Refresh
Temperature Controlled Refresh
Deep power-down (DPD) mode
Operation Frequency up to 104Mhz
Operating temperature Range
Industrial -40°C~85°C
Intrapage Read access : 20ns
Burst mode for Read and Write operation
4, 8, 16,32 or Continuous
Package: 54-ball VFBGA
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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General Description
CellularRAM™ (Trademark of MicronTechnology Inc.) products are high-speed, CMOS
pseudo-static random access memory developed for low-power, portable applications.
The 32Mb DRAM core device is organized as 2 Meg x 16 bits. This device is a variation of
the industry-standard Flash control interface that dramatically increase READ/WRITE
bandwidth compared with other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices.
The refresh configuration register (RCR) is used to control how refresh is performed on
the DRAM array. These registers are automatically loaded with default settings during
power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current. Partial
array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an
on-chip sensor to adjust the refresh rate to match the device temperature — the refresh
rate decreases at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system-configurable refresh
mechanisms are adjusted through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.5
feature set established by the CellularRAM Workgroup. It includes support for both
variable and fixed latency, with three drive strengths, a variety of wrap options, and a
device ID register (DIDR).
A0~A20
Address
Decode Logic
Input
/Output
Mux
2048K X 16
DRAM
Memory Array
Refresh
Configuration Register
(RCR)
And
Buffers
Device ID Register
(DIDR)
Bus
Configuration Register
(BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
LB#
UB#
WAIT
DQ0~DQ15
[ Functional Block Diagram]
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54Ball VFBGA Ball Assignment
[Top View]
(Ball Down)
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Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VDD
Type
Description
Core Power supply (1.7V~1.95V)
Power Supply
Power Supply
Power Supply
Power Supply
VDDQ
VSS
I/O Power supply (1.7V~1.95V)
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
VSSQ
DQ0~DQ15
A0~A20
LB#
Input / Output Data Inputs/Outputs (DQ0~DQ15)
Input
Input
Input
Input
Input
Input
Input
Address Input(A0~A20)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
UB#
CE#
OE#
WE#
Write Enable
CRE
Control Register Enable: When CRE is HIGH, READ and WRITE operations
access registers.
ADV#
Input
Address Valid signal
Indicates that a valid address is present on the address inputs. Address
can be latched on the rising edge of ADV# during asynchronous Read and
Write operations. ADV# can be held LOW during asynchronous Read and
Write operations.
CLK
Input
Clock
Latches addresses and commands on the first rising CLK edge when
ADV# is active in synchronous mode. CLK must be kept static Low during
asynchronous Read/Write operations and Page Read access operations.
WAIT
Output
WAIT
Data valid signal during burst Read/Write operation. WAIT is used to
arbitrate collisions between refresh and Read/Write operation. WAIT is
also asserted at the end of a row unless wrapping within the burst length.
WAIT is asserted and should be ignored during asynchronous and page
mode operation. WAIT is gated by CE# and is high-Z when CE# is high.
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Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
UB#/
LB#
DQ
CLK1
ADV#
CE#
OE#
WE#
CRE2
WAIT3
Note
Mode
Power
[15:0]4
Asynchronous Mode
Read
Write
Active
L
L
L
L
L
L
L
H
L
L
L
L
L
Low-Z
Low-Z
Data-out
Data-in
5
5
Active
X
Stand
by
Standby
L
L
L
X
X
L
H
L
X
X
H
X
X
L
L
L
X
X
X
High-Z
Low-Z
Low-Z
High-Z
X
6,7
5,7
No Operation
Idle
Configuration
Register Write
Active
L
H
High-Z
Configuration
Register Read
Config-Reg
Out
Active
DPD
L
L
L
L
L
H
X
H
X
L
Low-Z
High-Z
Deep Power-
Down
X
H
X
X
High-Z
10
Synchronous Mode (Burst Mode)
Async read
Async write
Active
Active
L
L
L
L
L
L
L
H
L
L
L
L
L
Low-Z
Low-Z
Data-Out
Data-In
5
5
X
Stand
by
Standby
L
L
X
X
L
H
L
X
X
X
X
X
H
L
L
L
X
X
L
High-Z
Low-Z
Low-Z
High-Z
6,7
5,8
5,8
No operation
Idle
X
X
Initial
burst read
Active
L
Initial
burst write
Active
L
L
H
L
L
X
Low-Z
X
5,8
Burst
continue
Data-In or
Data-Out
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
X
X
H
L
X
X
Low-Z
Low-Z
Low-Z
5,8
5,8
Burst suspend
X
High-Z
High-Z
Configuration
register write
8,11
Configuration
register read
Config-Reg
Out
Active
DPD
L
L
L
H
X
H
X
L
Low-Z
High-Z
8,11
10
Deep Power-
Down
L
X
H
X
X
High-Z
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Notes
1. CLK must be LOW during Async Read and Async Write modes. CLK must be LOW to achieve
low standby current during standby mode and DPD modes. CLK must be static (LOW or HIGH)
during burst suspend.
2. Configuration registers are accessed when CRE is HIGH during the address portion
of a READ or WRITE cycle.
3. WAIT polarity is configured through the bus configuration register (BCR[10]).
4. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8~DQ15 are affected as shown.
5. The device will consume active power in this mode whenever addresses are changed
6. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
7. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Byte operation can be supported Write & Read at asynchronous mode and Write at
synchronous mode.
10. DPD is initiated when CE# transition from LOW to HIGH after writing RCR[4] to 0. DPD is
maintained until CE# transitions from HIGH to LOW
11. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW
for the equivalent of a single word burst (as indicated by WAIT).
12. When the BCR is configured for sync mode, sync READ and sync WRITE and async WRITE
are supported.
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Functional Description
In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular
in low-power, portable applications.
The 32Mb device contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by
16 bits. This device implements the same high-speed bus interface found on burst mode Flash
products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization
process. Initialization will configure the BCR and the RCR with their default settings (see Table 3
and Table 8). VDD and VDDQ must be applied simultaneously.
When they reach a stable level at or above 1.7V, the device will require 150μs to complete
its self-initialization process. During the initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD=1.7V
tPU > 150us
Device ready for
normal operation
VDD
Device Initialization
VDDQ
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Bus Operating Modes
CellularRAM products incorporate a burst mode interface targeted at low-power,
wireless applications. This bus interface supports asynchronous, page mode, and burst
mode read and write transfers. The specific interface supported is defined by the value
loaded into the bus configuration register. Page mode is controlled by the refresh configuration
register (RCR[7]).
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multi-clock sequence that must be performed in an
ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge
of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates
whether the operation is going to be a READ (WE#=HIGH) or WRITE(WE#=LOW).
The size of a burst can be specified in the BCR either as a fixed length or continuous.
Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous
bursts have the ability to start at a specified address and burst to the end of the row.
(Row length of 128 words or 256 words is a manufacturer option.)
The latency count stored in the BCR defines the number of clock cycles that elapse
before the initial data value is transferred between the processor and CellularRAM
device. The initial latency for READ operations can be configured as fixed or variable.
(WRITE operations always use fixed latency). Variable latency allows the CellularRAM to
be configured for minimum latency at high clock frequencies, but the controller must
monitor WAIT to detect any conflict with refresh cycles.(see Figure 26).
Fixed latency outputs the first data word after the worst-case access delay, including
allowance for refresh collisions. The initial latency time and clock speed determine the
latency count setting. Fixed latency is used when the controller cannot monitor WAIT.
Fixed latency also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated and de-asserts to indicate when data
is to be transferred into (or out of) the memory. WAIT will again be asserted at the
boundary of the row unless wrapping within the burst length.
To access other devices on the same bus without the timing penalty of the initial latency
for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.
CLK must be stopped LOW. If another device will use the data bus while the burst is
suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,
OE# can remain LOW. Note that the WAIT output will continue to be active, and as a
result no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is
available on the bus.
CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than
tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE#
should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
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Burst Read Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a READ (WE# = HIGH, Figure 2)
Then the data needs to be output to data bus (DQ0~DQ15) according to set WAIT states.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of a row, unless wrapping within the burst length.
A full 4 word synchronous read access is shown in Figure 2 and the AC characteristics are specified
in Table 16.
Figure 2. Synchronous Read Access Timing
tCLK
tABA
CLK
VALID
ADDRESS
Address
tSP
tHD
tACLK
tKOH
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tSP
tHD
tHZ
ADV#
CE#
tHD
tCBPH
tCSP
tCEM
tSP
tHD
UB#/LB#
WE#
tSP tHD
tOLZ
tOHZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
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Burst Write Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a WRITE (WE# =LOW, Figure 3).
Data is placed to the data bus (DQ0~DQ15) with consecutive clock cycles when WAIT de-asserts.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of a row, unless wrapping within the burst length.
A full 4 word synchronous write access is shown in Figure 3 and the AC characteristics are specified in
Table 18.
Figure 3. Synchronous Write Access Timing
tCLK
CLK
VALID
ADDRESS
Address
tSP
tHD
tSP
tHD
DQ0-
DQ15
DATA IN
DATA IN
DATA IN
DATA IN
tAS
tAS
ADV#
tHD
tCSP
tCEM
CE#
tCBPH
tSP tHD
tHD
UB#/LB#
tHD
tSP
WE#
tCEW
tKHTL
HiZ
WAIT
Write Burst Identified (WE#=LOW)
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Asynchronous Mode
Asynchronous mode uses industry-standard SRAM control signals (CE#, OE#, WE#, UB#,
and LB#). READ operations (Figure 4) are initiated by bringing CE#, OE#, UB#/LB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed.
WRITE operations (Figure 5) occur when CE#, WE#, UB#/LB# are driven LOW. During
asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override
OE#. The data to be written is latched on the rising edge of CE#, WE#, UB#/LB#
(whichever occurs first). Asynchronous operations (page mode disabled) can either
use the ADV input to latch the address, or ADV can be driven LOW during the entire
READ/WRITE operations
During asynchronous operation, the CLK input must be held LOW. WAIT will be driven
during asynchronous READs, and its state should be ignored. WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing (ADV# LOW)
tRC = READ cycle Time
VALID
ADDRESS
Address
DQ0-
DQ15
VALID
OUTPUT
CE#
UB#/LB#
OE#
WE#
Notes:
1. ADV must remain LOW for PAGE MODE operation.
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Figure 5. Asynchronous Write Access Timing (ADV# LOW)
tWC = WRITE cycle Time
VALID
ADDRESS
Address
DQ0-
DQ15
VALID
OUTPUT
CE#
UB#/LB#
< tCEM
WE#
OE#
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Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
preformed, then adjacent addresses can be read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM
page. Any change in addresses A[4] or higher will initiate a new tAA access time.
Figure 6 shows the timing for a page mode access. Page mode takes advantage of the fact
that adjacent addresses can be read in a shorter period of time than random addresses.
WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW. CE# must
be driven HIGH upon completion of a page mode access. WAIT will be driven while the device
is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH.
ADV must be driven LOW during all page mode READ accesses.
Due to refresh considerations, CE# must not be LOW longer than tCEM.
Figure 6. Page Mode READ Operation (ADV# LOW)
Address
ADD0
ADD1
ADD2
ADD3
tAA
tAPA
tAPA
tAPA
DQ0-
DQ15
D0
D1
D2
D3
CE#
UB#/LB#
OE#
WE#
Notes:
1. ADV must remain LOW for PAGE MODE operation.
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Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous READ
and WRITE operations when the BCR is configured for synchronous operation. The
asynchronous READ and WRITE operations require that the clock (CLK) remain LOW
during the entire sequence. The ADV# signal can be used to latch the target address,
or it can remain LOW during the entire WRITE operation. CE# can remain LOW
when transitioning between mixed-mode operations with fixed latency enabled;
however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a
seamless interface to legacy burst mode Flash memory controllers. See Figure 45 for the
“Asynchronous WRITE Followed by Burst READ” timing diagram.
WAIT Operation
WAIT output on the CellularRAM device is typically connected to a shared, system-level
WAIT signal. The shared WAIT signal is used by the processor to coordinate transactions
with multiple memories on the synchronous bus.
When a synchronous READ or WRITE operation has been initiated, WAIT goes active to
indicate that the CellularRAM device requires additional time before data can be
transferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory controller
when data will be accepted into the CellularRAM device. When WAIT transitions to an
inactive state, the data burst will progress on successive rising clock edges.
During a burst cycle CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an
arbitration role for READ operations launched while an on-chip refresh is in progress. If
a collision occurs, the WAIT pin is asserted for additional clock cycles until the refresh
has completed (see Figure 26). When the refresh operation has completed, the
READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE and
page READ operations.
WAIT will be High-Z during asynchronous WRITE operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst
mode without monitoring the WAIT pin. However, WAIT can still be used to determine
when valid data is available at the start of the burst and at the end of the row. If wait is
not monitored, the controller must stop burst accesses at row boundaries on its own.
UB#/LB# Operation
The UB#/LB# enable signals support byte-wide data WRITEs. During WRITE operations,
any disabled bytes will not be transferred to the RAM array and the internal value will
remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, UB#, and LB# whichever occurs first.
UB#/LB# must be LOW during synchronous READ cycles.
When UB#/LB# are disabled (HIGH) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected,
it remains in an active mode as long as CE# remains LOW.
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Low-Power Feature
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operation, or when the address and control inputs remain static for an extended period
of time. This mode will continue until a change occurs to the address or control inputs.
Temperature-Compensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor that
automatically adjusts the refresh rate according to the operating temperature. The
device continually adjusts the refresh rate to match that temperature.
Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping
of these partitions can start at either the beginning or the end of the address map (see
Table 9). READ and WRITE operations to address ranges
receiving refresh will not be affected. Data stored in addresses not receiving refresh will
become corrupted. When re-enabling additional portions of the array, the new portions
are available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume. During this 150μs period, the current
consumption will be higher than the specified standby levels, but considerably lower
than the active current specification.
DPD can be enabled by writing to the RCR using CRE or the software access sequence;
DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays
LOW for at least 10us.
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Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash devices. The
refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during
power-up, and can be updated any time the devices are operating in a standby state.
A DIDR provides information on the device manufacturer, CellularRAM generation, and
the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation
when the configuration register enable (CRE) input is HIGH (see Figures 7 through 10). When CRE is
LOW, a READ or WRITE operation will access the memory array. The configuration register values are
written via A[20:0]. In an asynchronous WRITE, the values are latched into the configuration register
on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”
The BCR is accessed when A[19:18] is 10b; the RCR is accessed when A[19:18] is 00b; the
DIDR is accessed when A[19:18] is 01b. For READs, address inputs other than A[19:18]
are “Don’t Care,” and register bits 15:0 are output on DQ[15:0]. Immediately after performing
a configuration register READ or WRITE operation, reading the memory array is highly
recommended
Figure 7: Configuration Register WRITE
– Asynchronous Mode, Followed by READ ARRAY Operation
VALID
ADDRESS
OPCODE1
tAVH
Address
tAVS
tAVS tAVH
DQ0-
VALID
OUTPUT
DQ151
tVS
tAADV
tVP
tVP
tHZ
ADV#
CE#
tCVS
tCVS
tCW
tCO
tCPH
tBA
UB#/LB#
WE#
tWP
tOLZ
tOE
Write Address Bus
Value to Control
Register
OE#
tAVS
tAVH
CRE2
Notes:
1. A[19:18] = 00b to load RCR, and 10b to load BCR.
2. CRE must be HIGH to access registers.
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Figure 8: Configuration Register WRITE
– Synchronous Mode Followed by READ ARRAY Operation
tCLK
tABA
CLK
VALID
ADDRESS
OPCODE2
tSP tHD
Address
tACLK tKOH
tSP tHD
DQ0-
DQ15
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
tSP tHD
ADV#
3
tCBPH
tCSP
tCEM
tCEM
CE#
UB#/LB#
WE#
tHD
tHD
tSP
tOHZ
tBOE
OE#
tHZ
tCEW
tCEW
tKHTL
tKHTL
HiZ
WAIT
tHD
CRE4
tSP
Notes:
1. Non-default BCR settings for configuration register WRITE in synchronous mode, followed by READ ARRAY
operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored additional WAIT
cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
4. CRE must be HIGH to access registers.
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Figure 9: Configuration Register READ
– Asynchronous Mode Followed by DATA READ
tAA
Select
VALID
ADDRESS
Address
Control
Register1
tAVS tAVH
tAVS tAVH
DQ0-
DQ15
VALID
OUTPUT
CR Valid
tAADV
tAADV
tVP
tVP
tHZ
ADV#
tCPP
tCO
tCO
tCPH
CE#
tBLZ
tBA
tBA
UB#/LB#
WE#
tOLZ
tOE
tOE
OE#
tAVS
tAVH
CRE2
Notes:
1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR
2. CRE must be HIGH to access registers.
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Figure 10: Configuration Register READ
– Synchronous Mode Followed by Data READ
tCLK
tABA
CLK
Select
VALID
ADDRESS
Control
Address
Register2
tACLK tKOH
tACLK tKOH tSP tHD
tSP tHD
CR
valid
DQ0-
DQ15
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
tSP
tHD
ADV#
3
tCBPH
tCSP
tCEM
tABA
CE#
UB#/LB#
WE#
tHD
tSP
tSP
tHD
tOHZ
tBOE
OE#
tHZ
tCEW
tCEW
tKTHL
tKHTL
HiZ
WAIT
tHD
CRE4
tSP
Notes:
1. Non-default BCR settings for configuration register READ in synchronous mode, followed by READ ARRAY
operation: Latency code three (four clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, to 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored additional WAIT
cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
4. CRE must be HIGH to access registers.
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Software Access Sequence
Software access of the configuration registers uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the configuration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 11). The read sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 12). The address used during all
READ and WRITE operations is the highest address of the CellularRAM device being
accessed (1FFFFFh); the contents of this address are not changed by using this sequence.
The data value presented during the third operation (WRITE) in the sequence
defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence
will access the RCR; if the data is 0001h, the sequence will access the BCR;
if the data is 0002h, the sequence will access the DIDR. During the fourth operation,
DQ[15:0] transfer data in to or out of bits 15:0 of the control registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for the control register enable
(CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS.
The port line often used for CRE control purposes is no longer required.
Figure 11 : Configuration Register Write
Address
MAX
MAX
MAX
MAX
ADDRESS
ADDRESS
ADDRESS
ADDRESS
DQ0-
DQ15
OUTPUT
DATA
OUTPUT
DATA
CR
*Note1
VALUE IN
CE#
UB#/LB#
WE#
Read
Read
Write
Write
OE#
Notes :
1. RCR : 0000h , BCR : 0001h
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Figure 12 : Configuration Register Read
MAX
MAX
MAX
MAX
ADDRESS
Address
ADDRESS
ADDRESS
ADDRESS
DQ0-
DQ15
OUTPUT
DATA
OUTPUT
DATA
CR
*Note1
VALUE OUT
Read
Read
Write
Read
CE#
UB#/LB#
WE#
OE#
Notes :
1. RCR : 0000h , BCR : 0001h , DIDR : 0002h
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Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Table 3 describes the control bits in the BCR. At power-up, the BCR is set to 1D1Fh.
The BCR is accessed using CRE and A[19:18] = 10b, or through the configuration
register software sequence with DQ[15:0] = 0001h on the third cycle.
Table 3. Bus configuration Register
Remark
Bit Number
20
Definition
Reserved
Must be set to “0”
00 = Select RCR
01 = Select DIDR
10 = Select BCR
19 – 18
Register Select
17 – 16
15
Reserved
Must be set to “0”
0 = Synchronous burst access mode
1 = Asynchronous access mode (default)
Operating mode
Initial Latency
0 = Variable (default)
1 = Fixed
14
000 = 9 clock cycles
001 = reserved
010 = 3 clock cycles
011 = 4 clock cycles (default)
100 = 5 clock cycles
101 = 6 clock cycles
110 = 7 clock cycles
111 = reserved
13 – 11
Latency Count
0 = Active LOW : Data valid at WAIT HIGH
1 = Active HIGH : Data valid at WAIT LOW (default)
10
9
WAIT Polarity
Reserved
Must be set to “0”
0 = Asserted during delay
1 = Asserted one data cycle before delay (default)
8
WAIT Configuration
Reserved
7 – 6
Must be set to “0”
00 = Full drive
01 = ½ Drive (default)
10 = ¼ Drive
11 = Reserved
5 – 4
3
Output Impedance
Burst mode
0 = Burst wrap within the burst length
1 = Burst no wrap (default)
001 = 4 words
010 = 8 words
011 = 16 words
100 = 32 words
2 – 0
Burst Length
111 = continuous (default)
Others = Reserved
Notes :
1.Burst wrap and length apply to both READ and WRITE operations.
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Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and
WRITE operations. The device supports a burst length of four, eight, sixteen, or thirty-two
words. The device can also be set in continuous burst mode where data is accessed
sequentially up to the end of the row.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4-, 8-, 16, 32-word READ or WRITE burst wraps
within the burst length, or steps through sequential addresses. If the wrap option is not
enabled, the device accesses data from sequential addresses up to the end of the row.
Table 4. Sequence and Burst Length
Starting
Address
Wrap
BL4
BL8
BL16
BL32
Continuous
Linear
DEC
BCR[3]
Linear
Linear
Linear
Linear
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
•••
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
•••
0-1-2-3- ••• -12-13-14-15
1-2-3-4- ••• -13-14-15-0
2-3-4-5- ••• -14-15-0-1
3-4-5-6- ••• -15-0-1-2
•••
0-1-2-3- ••• -28-29-30-31
1-2-3-4- ••• -29-30-31-0
2-3-4-5- ••• -30-31-0-1
3-4-5-6- ••• -31-0-1-2
•••
0-1-2-3-4-5-6- •••
1-2-3-4-5-6-7- •••
2-3-4-5-6-7-8- •••
3-4-5-6-7-8-9- •••
•••
2
3
•••
6
6-7-4-5
7-4-5-6
•••
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
•••
6-7-8-9- ••• -2-3-4-5
7-8-9-10- ••• -3-4-5-6
•••
6-7-8-9- ••• -2-3-4-5
7-8-9-10- ••• -3-4-5-6
•••
6-7-8-9-10-11-12- •••
7-8-9-10-11-12-13- •••
•••
7
“0”
Wrap
•••
14-15-16-17-18-19-20-
•••
14
15
14-15-12-13
15-12-13-14
14-15-8-9-10-11-12-13
15-8-9-10-11-12-13-14
14-15-0-1- ••• -10-11-12-13
15-0-1-2-3- ••• -11-13-13-14
30-31-0-1- ••• -26-27-28-29
31-0-1-2-3- ••• -27-28-29-30
15-16-17-18-19-20-21-
•••
•••
254
255
0
•••
254-255-252-253
255-252-253-254
0-1-2-3
•••
254-255-248-••• -252-253
255-248-249- ••• -253-254
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
•••
•••
•••
•••
254-255-240-241- ••• -252-253
255-240-241-242- ••• -253-254
0-1-2-3-4- ••• -12-13-14-15
1-2-3-4- ••• -13-14-15-16
2-3-4-5- ••• -14-15-16-17
3-4-5-6- ••• -15-16-17-18
•••
254-255-224-225- ••• -252-253
255-224-225-226- ••• -253-254
0-1-2-3- ••• -28-29-30-31
1-2-3-4- ••• -29-30-31-32
2-3-4-5- ••• -30-31-32-33
3-4-5-6- ••• -31-32-33-34
•••
254-255-0-1-2-•••
255-0-1-2-•••
0-1-2-3-4-5-6- •••
1-2-3-4-5-6-7- •••
2-3-4-5-6-7-8- •••
3-4-5-6-7-8-9- •••
•••
1
1-2-3-4
2
2-3-4-5
3
3-4-5-6
•••
6
•••
6-7-8-9
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
•••
6-7-8-9- ••• -18-19-20-21
7-8-9-10- ••• -19-20-21-22
•••
6-7-8-9- ••• -34-35-36-37
7-8-9-10- ••• -35-36-37-38
•••
6-7-8-9-10-11-12- •••
7-8-9-10-11-12-13- •••
•••
“1”
No
Wrap
7
7-8-9-10
•••
•••
14-15-16-17-18-19-20-
•••
14
15
14-15-16-17
15-16-17-18
14-15-16-17-18-19-20-21
15-16-17-18-19-20-21-22
14-15-16-17- ••• - 26-27-28-29
15-16-17-18- ••• -27-28-29-30
14-15-16-17- ••• - 42-43-44-45
15-16-17-18- ••• -43-44-45-46
15-16-17-18-19-20-21-
•••
•••
254
255
•••
254-255
255
•••
254-255
255
•••
254-255
255
•••
254-255
255
•••
254-255
255
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Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to
adjust for different data bus loading scenarios. The reduced-strength options are intended
for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory
bus. The reduced-drive-strength option minimizes the noise generated on the data bus
during READ operations. Full output drive strength should be selected when using a
discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are
configured at half-drive strength during testing. See Table 5 for additional information.
Table 5. Drive Strength
Use Recommendation
CL = 30pF to 50pF
BCR[5]
0
BCR[4]
0
Drive Strength
Full
Impedance Typ (Ω)
25 ~ 30
CL = 15pF to 30pF
104MHz at light load
0
1
1/2(Default)
1/4
50
1
1
0
1
100
CL = 15pF or lower
Reserved
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the de-asserted or asserted state
respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data
bus going valid or invalid (see Figure 13).
Figure 13. WAIT Configuration During Burst Operation
CLK
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
BCR[8]=0
Data valid/invalid in current cycle
WAIT
BCR[8]=1
Data valid/invalid in next cycle
WAIT
Notes :
Non-default BCR setting : WAIT active LOW
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
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Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Latency codes from two
(three clocks) to six (seven clocks) are supported (see Tables 6 and 7, Figure 14, and
Figure 15).
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency
counter. However, WAIT must be monitored to detect delays caused by collisions with
refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for
worst-case refresh collisions. The latency counter must be configured to match the
initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed
initial latency. The burst begins after the number of clock cycles configured by the
latency counter. (See Table 7 and Figure 15)
Table 6. Variable Latency Configuration Codes (BCR[14] = 0)
Latency
Max Input CLK Frequency (MHz)
Latency
Configuration
Code
BCR
[13:11]
Refresh
Normal
-96
-12
Collision
2
3
4
-
4
010
011
2 (3 clocks)
66 (15.0ns)
52 (18.5ns)
3 (4 clocks)-default
4 (5 clocks)
6
8
-
104 (9.62ns)
-
80 (12.5ns)
-
100
others
Notes:
Reserved
1. Latency is the number of clock cycles from the initialization of a burst operation until data appears.
Data is transferred on the next clock cycle.
Figure 14. Latency Counter (Variable Latency, No Refresh Collision)
VALID
A[20:0]
ADDRESS
CLK
ADV#
Code 2 (3 clocks)
DQ0-
DQ15
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 3 (4 clocks) : Default
Code 4 (5 clocks)
DQ0-
DQ15
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ0-
DQ15
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
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Table 7. Fixed Latency Configuration Codes (BCR[14] = 1)
Latency
Configuration
Code
Max Input CLK Frequency (MHz)
BCR
[13:11]
Latency
Count (N)
-96
-12
2
3
4
5
6
-
010
011
2 (3 clocks)
33 (30ns)
52 (19.2ns)
66 (15.0ns)
75 (13.3ns)
104 (9.62ns)
-
25 (40ns)
40 (25ns)
3 (4 clocks)-default
4 (5 clocks)
5 (6 clocks)
6 (7 clocks)
Reserved
100
52 (19.2ns)
66 (15.0ns)
80 (12.5ns)
-
101
110
others
Figure 15. Latency Counter (Fixed Latency)
Cycle N
CLK
ADV#
tAADV
tCO
CE#
tAA
VALID
ADDRESS
A[20:0]
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
(READ)
DQ0-
DQ15
VALID
INPUT
VALID
INPUT
VALID
INPUT
(WRITE)
Burst Identified
(ADV#=LOW)
Operating Mode (BCR[15]) Default = Synchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous
mode of operation
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Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce
current consumption during standby mode. Table 8 describes the control bits used in
the RCR. At power-up, the RCR is set to 0010h
The RCR is accessed using CRE and A[19:18] = 00b, or through the configuration
register software access sequence with DQ = 0000h on the third cycle (see “Registers”)
Table 8. Refresh Configuration Register
Bit Number
20
Definition
Reserved
Remark
Must be set to “0”
00 = Select RCR
01 = Select DIDR
10 = Select BCR
19 – 18
Register Select
17 – 8
Reserved
Page
Must be set to “0”
0 = Page Mode disabled (default)
1 = Page Mode enable
7
6 – 5
4
Reserved
DPD
Setting is ignored (Default 00b)
0 = DPD enable
1 = DPD disable (default)
3
Reserved
Must be set to “0”
000 = Full array (default)
001 = Bottom 1/2 array
010 = Bottom 1/4 array
011 = Bottom 1/8 array
100 = None of array
101 = Top 1/2 array
110 = Top 1/4 array
111 = Top 1/8 array
2 – 0
Partial Refresh
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Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Table 9)
Table 9. 32Mb Address Patterns for PAR (RCR[4]=1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Full
Address Space
000000h ~ 1FFFFFh
000000h ~ 0FFFFFh
000000h ~ 07FFFFh
000000h ~ 03FFFFh
0
Size
Density
32Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2MX16
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
1MX16
512KX16
256KX16
4Mb
0Mb
100000h ~ 1FFFFFh
180000h ~ 1FFFFFh
1C0000h ~ 1FFFFFh
1MX16
512KX16
256KX16
16Mb
8Mb
4Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. Taking CE# LOW
disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. DPD
can be enabled using CRE or the software sequence to access the RCR. BCR and RCR
values (other than BCR[4]) are preserved during DPD.
Page Mode Operation (RCR[7]) Default = Disabled
The Page mode operation bit determines whether page mode is enabled for asynchronous
READ operations. In the power-up default state, page mode is disabled
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation,
and the specific device configuration. Table 10 describes the bit fields in the DIDR. This
register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the software access
sequence with DQ = 0002h on the third cycle.
Table 10. Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
Vendor ID
CellularRAM
Generation
Field Name
Row Length
Device Version
Device Density
Length
- words
Bit
Setting
Bit
Bit
Bit
Setting
Bit
Setting
Genera
Version
Density
Vendor
ISSI
tion
Setting
0000b
0001b
Setting
000b
128
0b
1b
1st
16Mb
32Mb
CR1.5
CR2.0
010b
011b
00101b
256
2nd
001b
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Electrical Characteristics
Table 11. Absolute Maximum Ratings
Parameter
Rating
Voltage to Any Ball Except VDD, VDDQ Relative to VSS
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Storage Temperature (plastic)
-0.3V to VDDQ + 0.3V
-0.2V to +2.45V
-0.2V to +2.45V
-55°C to +150°C
-40°C to +85°C
Operating Temperature (case)
Soldering Temperature and Time
10s (solder ball only)
+260°C
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Table 12. Electrical Characteristics and Operating Conditions
Industrial Temperature (–40ºC < TC < +85ºC)
Description
Supply Voltage
Conditions
Symbol
VDD
MIN
1.7
MAX
1.95
Unit
V
Note
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VDDQ
VIH
VIL
1.7
1.95
V
VDDQ-0.4
-0.20
VDDQ+0.2
0.4
V
1
2
3
3
V
IOH = -0.2mA
IOL = +0.2mA
VIN = 0 to VDDQ
VOH
VOL
ILI
0.80 VDDQ
V
0.20 VDDQ
1
V
uA
OE#=VIH or
Chip Disabled
Output Leakage Current
ILO
1
uA
Unit
mA
Operating Current
Conditions
Symbol
TYP
MAX
25
Note
Asynchronous Random
READ/WRITE
IDD1
-70
-70
4
Asynchronous
PAGE READ
IDD1P
18
mA
mA
4
4
104Mhz
80Mhz
104Mhz
80Mhz
104Mhz
80Mhz
35
30
30
25
35
30
Initial Access, Burst
READ/WRITE
VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
IDD2
Continuous Burst READ
IDD3R
mA
4
Continuous Burst WRITE
Standby Current
IDD3W
ISB
mA
uA
4
5
VIN=VDDQ or 0V
CE#=VDDQ
150
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Notes:
1. Input signals may overshoot to VDDQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to Vss – 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b (default setting of one-half drive strength).
4. This parameter is specified with the outputs disabled to avoid external loading effects.
User must add required current to drive output capacitance expected in the actual system.
5. ISB (MAX) values measured with PAR set to FULL ARRAY at +85°C. In order to achieve low
standby current, all inputs must be driven to either VDDQ or VSS. ISB might be set slightly
higher for up to 500ms after power-up, or when entering standby mode.
Table 13. Deep Power-Down Specifications
Description Conditions
Symbol
TYP
MAX
Unit
VIN=VDDQ or 0V
VDD,VDDQ=1.95V, +85°C
Deep Power-Down
IDPD
3
10
uA
Notes:
Typical (TYP) IDPD value applies across all operating temperatures and voltages.
Table 14. Capacitance
Description
Conditions
Symbol
MIN
MAX
Unit
Note
TC=+25°C;
f=1Mhz;
VIN=0V
Input Capacitance
CIN
2.0
3.5
6.0
6
pF
1
Input/Output Capacitance (DQ)
CIO
pF
1
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
Figure 16. AC Input/Output Reference Waveform
VDDQ
∫∫
Test Points
∫∫
VDDQ/22 Output
VDDQ/23 Output
VSS
Notes:
1. AC test inputs are driven at VDDQ for a logic 1 and VSS for a logic 0. Input rise and fall times
(10% to 90%) < 1.6ns.
2. Input timing begins at VDDQ/2.
3. Output timing ends at VDDQ/2.
Figure 17. Output Load Circuit
Test Point
50Ω
DUT
VDDQ/2
30pF
Notes:
All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
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AC Characteristics
Table15 . Asynchronous READ Cycle Timing Requirements
70ns
Symbol
Parameter
Address Acess Time
Unit
Notes
Min
Max
70
tAA
tAADV
tAPA
tAVH
tAVS
tBA
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# Access Time
70
Page Access Time
20
Address hold from ADV# HIGH
Address setup to ADV# HIGH
UB#, LB# Access Time
2
5
70
8
tBHZ
tBLZ
tCEM
tCEW
tCO
UB#, LB# Disable to High-Z Output
UB#, LB# Enable to Low-Z Output
Maximum CE# pulse width
CE# low to WAIT Valid
1
2
3
10
1
4
7.5
70
Chip Select Access Time
tCVS
tHZ
CE# low to ADV# HIGH
7
Chip Disable to DQ and WAIT High-Z Output
Chip enable to Low-Z output
OE# low to Valid Output
8
20
8
1
2
tLZ
10
5
tOE
tOH
Output hold from address change
Output disable to DQ High-Z output
Output enable to Low-Z output
Page READ cycle time
tOHZ
tOLZ
tPC
1
2
3
20
70
5
tRC
READ cycle time
tVP
ADV# Low pulse width
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 17. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 17. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or
VOL.
3. Page mode enable only
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Table16 . Burst READ Cycle Timing Requirements
-7010
-7008
Symbol
Parameter
Unit
Note
Min
Max
Min
Max
70
70
70
70
tAA
Address Acess Time (Fixed Latency)
ADV# Access Time (Fixed Latency)
ns
ns
tAADV
Burst to READ Access Time
(Variable Latency)
35.9
7
46.5
9
tABA
tACLK
tAVH
ns
ns
ns
ns
ns
CLK to Output Delay
Address hold from ADV# HIGH
(Fixed Latency)
2
5
2
6
20
20
tBOE
Burst OE# LOW to Output Valid
CE# High between Subsequent
Burst or Mixed-Mode Operations
tCBPH
1
1
4
4
tCEM
tCEW
tCLK
Maximum CE# Pulse width
CE# low to WAIT Valid
CLK Period
us
ns
ns
1
7.5
1
7.5
9.62
12.5
Chip Select Access Time (Fixed
Latency)
70
70
tCO
ns
3
2
4
2
tCSP
tHD
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
ns
ns
Chip Disable to DQ and WAIT
High-Z Output
8
8
tHZ
ns
2
1.6
7
1.8
9
tKHKL
tKHTL
tKOH
tKP
CLK rise or fall Time
ns
ns
CLK to WAIT Valid
2
3
2
4
Output HOLD from CLK
CLK HIGH or LOW time
8
8
tOHZ
tOLZ
tSP
Output disable to DQ High-Z Output
Output enable to DQ Low-Z output
Setup time to Active CLK Edge
ns
ns
ns
2
3
3
3
3
3
Notes:
1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by
either of the following two conditions : a) clocked CE#, or b) CE# HIGH for longer than 15ns
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 17.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 17. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
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Table17 . Asynchronous WRITE Cycle Timing Requirements
70ns
Symbol
Parameter
Unit
Notes
Min
0
Max
tAS
tAVH
tAVS
tAW
Address and ADV# LOW Setup Time
Address hold from ADV# HIGH
Address setup to ADV# HIGH
Address Valid to End of Write
UB#, LB# Select to End of Write
CE# low to WAIT Valid
ns
ns
ns
ns
ns
ns
2
5
70
70
1
tBW
tCEW
7.5
CE# HIGH between Subsequent
Asynchronous cycles
tCPH
5
ns
tCVS
tCW
tDH
tDW
tHZ
CE# low to ADV# HIGH
7
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Data Hold from Write Time
Data Write Setup Time
20
Chip Disable to DQ and WAIT High-Z Output
Chip enable to Low-Z output
End WRITE to Low-Z output
ADV# Low pulse width
8
1
2
2
tLZ
10
5
tOW
tVP
5
tVS
ADV# Setup to End of Write
WRITE cycle time
70
70
tWC
tWHZ
tWP
tWPH
tWR
WRITE to DQ High-Z Output
WRITE Pulse Width
8
1
3
45
10
0
WRITE pulse width HIGH
WRITE Recovery Time
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 17. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 17.
The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. WE# must be limited to tCEM (4us)
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Table18 . Burst WRITE Cycle Timing Requirements
-7010
-7008
Symbol
Parameter
Unit
Note
1
Min
Max
Min
Max
Address and ADV# LOW Setup
Time
0
0
2
6
tAS
ns
ns
ns
Address hold from ADV# HIGH
(Fixed Latency)
2
5
tAVH
tCBPH
CE# High between Subsequent
Burst or Mixed-Mode Operations
2
2
4
4
tCEM
tCEW
tCLK
Maximum CE# Pulse width
CE# low to WAIT Valid
CLK Period
us
ns
ns
1
7.5
1
7.5
9.62
12.5
CE# Setup Time to Active CLK
Edge
3
2
4
2
tCSP
tHD
tHZ
ns
ns
ns
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT
High-Z Output
8
8
3
1.6
7
1.8
9
tKHKL
tKHTL
tKP
CLK rise or fall Time
ns
ns
ns
ns
CLK to WAIT Valid
3
3
4
3
CLK HIGH or LOW time
Setup time to Active CLK Edge
tSP
Notes:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by
either of the following two conditions : a) clocked CE#, or b) CE# HIGH for longer than 15ns
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 17.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
Table19 . Initialization and DPD Timing Requirements
-70
Symbol
Parameter
Unit
Notes
Min
150
10
Max
150
tDPD
tDPDX
tPU
Time from DPD entry to DPD exit
us
us
us
CE# LOW time to exit DPD
Initialization Period (required before normal operations)
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Timing Diagrams
Figure 18: Power-Up Initialization Timing
VDD, VDDQ=1.7V
VDD(MIN)
tPU > 150us
Device ready for
normal operation
Device Initialization
Figure 19: DPD Entry and Exit Timing Parameters
tDPD
tDPDX
tPU
CE#
Write
RCR[4]=0
DPD Enabled
DPD Exit
Device Initialization Device ready for
normal operation
Figure 20: Asynchronous READ
tRC
VALID
ADDRESS
Address
tAA
DQ0-
DQ15
VALID
OUTPUT
ADV#
CE#
tCO
tHZ
tLZ
tBA
tBHZ
UB#/LB#
OE#
tOHZ
tOLZ
tOE
tCEW
WE#
HiZ
tHZ
HiZ
WAIT
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Figure 21: Asynchronous READ Using ADV#
tAA
VALID
ADDRESS
Address
tAVS
tAVH
DQ0-
DQ15
VALID
OUTPUT
tAADV
tVP
tCVS
ADV#
CE#
tCO
tHZ
tLZ
tBA
tBHZ
UB#/LB#
OE#
tOHZ
tOLZ
tOE
WE#
tCEW
HiZ
tHZ
HiZ
WAIT
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Figure 22: PAGE MODE READ
tRC
VALID
ADDRESS
A4-A20
A0-A3
tPC
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
tAA
tAPA
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tOH
ADV#
CE#
tCO
tHZ
tLZ
tBHZ
tBA
UB#/LB#
OE#
tOHZ
tOLZ
tOE
tCEW
WE#
tHZ
HiZ
HiZ
WAIT
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Figure 23: CLK Timings for Burst Operations
tCLK
tKHKL
tCLK
tKP
tKP
Notes :
1. For Burst timing diagrams, non-default BCR settings are shown
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Figure 24: Single Access Burst READ Operation – Variable Latency without refresh collision
tABA
tCLK
CLK
VALID
ADDRESS
Address
tACLK
tKOH
tSP
tHD
DQ0-
DQ15
VALID
OUTPUT
tSP
tHD
ADV#
CE#
tCSP
tHD
tCEM
tSP
tHD
UB#/LB#
WE#
tOLZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default variable latency BCR settings for single-access burst READ operation: Latency
code two (three clocks); WAIT active LOW; WAIT asserted during delay.
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Figure 25: Four-Word Burst READ Operation – Variable Latency without refresh collision
tCLK
tABA
CLK
VALID
ADDRESS
Address
tACLK
tKOH
tSP
tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tSP
tHD
tHZ
ADV#
CE#
tHD
tCBPH
tCSP
tCEM
tSP
tHD
UB#/LB#
WE#
tSP tHD
tOLZ
tOHZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default variable latency BCR settings for 4-word burst READ operation: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
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Figure 26: Four-Word Burst READ Operation – Variable Latency with refresh collision
tCLK
CLK
VALID
ADDRESS
Address
tACLK
tKOH
tSP
tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tSP
tHD
tHZ
ADV#
CE#
tHD
tCBPH
tCSP
tCEM
tSP
tHD
UB#/LB#
WE#
tHZ
tSP tHD
tOLZ
tBOE
OE#
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default variable latency BCR settings for 4-word burst READ operation: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. If refresh collision happened, WAIT will be asserted between the latency count number of clock cycles
and 2x the latency count
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Figure 27: Single Access Burst READ Operation – Fixed Latency
tCLK
CLK
tAA
VALID
ADDRESS
Address
tKOH
tSP
tAVH
DQ0-
DQ15
VALID
OUTPUT
tAADV
tSP
tHD
ADV#
CE#
tHD tHZ
tCO
tCSP
tCEM
tSP
tHD
UB#/LB#
WE#
tSP tHD
tOHZ
tOLZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default fixed latency BCR settings for single-access burst READ operation: Fixed Latency;
Latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
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Figure 28: Four-Word Burst READ Operation – Fixed Latency
tCLK
CLK
tAA
VALID
ADDRESS
Address
tKOH
tSP
tAVH
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tHZ
tAADV
tSP tHD
ADV#
tCO
tHD
tCBPH
tCSP
tCEM
CE#
UB#/LB#
WE#
tSP
tHD
tSP tHD
tOLZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default fixed latency BCR settings for 4-word burst READ operation: Fixed latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
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Figure 29: READ Burst Suspend
CLK
Note2
VALID
ADDRESS
Address
tKOH
tSP tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
O
VALID
OUTPUT
VALID
OUTPUT
tHZ
tAADV
tSP tHD
ADV#
tCO
tHD tCBPH
tCSP
tCEM
CE#
tSP
tHD
UB#/LB#
tSP tHD
WE#
tOLZ
tBOE
OE#
Note3
tHZ
tCEW
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions
during burst suspend.
3. OE# can stay LOW during BURST SUSPEND. If OE# is LOW, DQ[15:0] will continue to
output valid data.
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Figure 30: Burst READ at End of Row (Wrap Off)
tCLK
CLK
Address
DQ0-
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ15
ADV#
CE#
End of Row (A[7:0]=FFh)
VIH
NOTE2
VIH
VIL
tHZ
VIL
UB#/LB#
WE#
VIL
OE#
tKHTL
tHZ
WAIT
Notes:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT
active LOW; WAIT asserted during delay.
2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins
(before the second CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after
WAIT asserts with BCR[8] = 1).
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Figure 31: CE#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID
INPUT
tAS tLZ
tDW
tDH
tWHZ
ADV#
tCW
tHZ
CE#
tBW
UB#/LB#
OE#
tWPH
tWP
WE#
tCEW
tHZ
HiZ
HiZ
WAIT
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Figure 32: LB#/UB#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID
INPUT
tLZ
tDW
tDH
tWHZ
ADV#
tCW
tHZ
CE#
tAS
tBW
UB#/LB#
OE#
tWPH
tWP
WE#
tCEW
tHZ
HiZ
HiZ
WAIT
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Figure 33: WE#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID
INPUT
tAS tLZ
tDW
tDH
tWHZ
ADV#
tCW
tHZ
CE#
tBW
UB#/LB#
tAS
OE#
tWPH
tWP
WE#
tCEW
tHZ
HiZ
HiZ
WAIT
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Figure 34: Asynchronous WRITE Using ADV#
tAW
tAS
VALID
ADDRESS
Address
tAVS
tAVH
tDW
tDH
DQ0-
DQ15
VALID
DATA
tVS
tVP
ADV#
CE#
tAS
tCVS
tCW
tBW
UB#/LB#
WE#
tWP
tCEW
tHZ
HiZ
HiZ
WAIT
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Figure 35: Four-Word Burst WRITE Operation – Variable Latency
tCLK
CLK
VALID
ADDRESS
Address
tSP
tHD
tSP
tHD
DQ0-
DQ15
DATA IN
DATA IN
DATA IN
DATA IN
tAS
tAS
NOTE3
ADV#
CE#
tHD
tCSP
tCEM
tCBPH
tSP tHD
tHD
UB#/LB#
WE#
tHD
tSP
tCEW
tKHTL
HiZ
WAIT
NOTE2
Write Burst Identified (WE#=LOW)
Notes:
1. Non-default BCR settings for burst WRITE operation, with fixed-length burst of 4, burst wrap enabled:
Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
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Figure 36: Four-Word Burst WRITE Operation – Fixed Latency
tCLK
CLK
VALID
ADDRESS
Address
tSP
tHD
tSP
tHD
DQ0-
DQ15
DATA IN
DATA IN
DATA IN
DATA IN
tAS
tAS
NOTE3
tAVH
ADV#
CE#
tHD
tCSP
tCEM
tCBPH
tSP tHD
tHD
UB#/LB#
WE#
tHD
tSP
tCEW
tKHTL
HiZ
WAIT
NOTE2
Write Burst Identified (WE#=LOW)
Notes:
1. Non-default BCR settings for burst WRITE operation, with fixed-length burst of 4, burst wrap enabled:
Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
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Figure 37: Burst WRITE at End-of-Row (Wrap Off)
tCLK
CLK
Address
VIH
ADV#
UB#/LB#
WE#
VIH
OE#
tKHTL
tHZ
tHZ
WAIT
NOTE2
VIH
VIL
CE#
tHZ
VALID
INPUT
VALID
INPUT
VALID
INPUT
DQ0-
DQ15
End of Row (A[7:0]=FFh)
Notes:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT
active LOW; WAIT asserted during delay.
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins
(before the second CLK after WAIT asserts with BCR[8] = 0, or before the third CLK after
WAIT asserts with BCR[8] = 1).
52
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Figure 38: Burst WRITE followed by Burst READ
tCLK
tABA
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tSP tHD
tACLK tKOH
tSP tHD
tSP tHD
DQ0-
DQ15
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
DATA INDATA INDATA INDATA IN
tAS
tAS
ADV#
tCBPH
tCSP
tCEM
tCEM
CE#
UB#/LB#
WE#
tSPtHD
tHD
tHD
tSP
tOLZ
tBOE
tOHZ
OE#
tHZ
tCEW
tCEW
HiZ
tKHTL
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst WRITE followed by burst READ; latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay
LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than
tCEM. See burst interrupt diagram (Figure 39 through 44) for cases where
CE# stay LOW between bursts.
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Figure 39: Burst READ interrupted by Burst READ
WRITE burst interrupted with new READ
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tACLK
tKOH
tACLK tKOH
VALID
tSP tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
VALID
VALID
OUTPUT OUTPUT OUTPUT OUTPUT
tOHZ
tSP tHD
ADV#
tCSP
t
CEM (Note3)
CE#
UB#/LB#
WE#
tSP tHD
tOLZ
tBOE
tOHZ
tBOE
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst READ interrupted by burst READ : fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown
for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after the first data received by the controller).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM
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Figure 40: Burst READ interrupted by Burst WRITE
WRITE burst interrupted with new WRITE
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tACLK
tKOH
tSP tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
tOHZ
ADV#
tCSP
t
CEM (Note3)
tHD
CE#
UB#/LB#
WE#
tSP tHD
tBOE
OE#
tCEW
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst READ interrupted by burst WRITE: fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown
for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after the first data received by the controller).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM
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Figure 41: Burst WRITE interrupted by Burst READ – Variable Latency Mode
WRITE burst interrupted with new READ
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tACLK tKOH
VALID
tSP tHD
DQ0-
DQ15
VALID
INPUT
VALID
VALID
VALID
OUTPUT OUTPUT OUTPUT OUTPUT
tSP tHD
ADV#
tCSP
tCEM (Note 3)
CE#
UB#/LB#
WE#
tSP tHD
tOLZ
tBOE
tOHZ
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst READ in variable latency mode:
fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
All bursts shown for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
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Figure 42: Burst WRITE interrupted by Burst WRITE – Variable Latency Mode
WRITE burst interrupted with new WRITE
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tSP tHD
DQ0-
DQ15
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
tSP tHD
ADV#
tHD
tCSP
tCEM (Note 3)
CE#
UB#/LB#
WE#
tSP tHD
OE#
tCEW
tKHTL
WAIT
Notes:
1. Non-default BCR settings for burst WRITE interrupted by WRITE: fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown
for variable latency; no refresh collision.
2. Burst interrupt shown on first allowable clock (such as after the first data received by the controller).
57
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Figure 43: Burst WRITE interrupted by Burst READ – Fixed Latency Mode
WRITE burst interrupted with new READ
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tACLK tKOH
VALID
tSP
tAVH
DQ0-
DQ15
VALID
INPUT
VALID
VALID
VALID
OUTPUT OUTPUT OUTPUT OUTPUT
tSP tHD
ADV#
tCSP
tCEM (Note 3)
CE#
UB#/LB#
WE#
tSP tHD
tOLZ
tBOE
tOHZ
OE#
tHZ
tCEW
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst READ in fixed latency mode:
fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
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Figure 44: Burst WRITE interrupted by Burst WRITE – Fixed Latency Mode
CLK
VALID
ADDRESS
VALID
ADDRESS
Address
tSP
tAVH
DQ0-
DQ15
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
tHD
tSP
ADV#
tHD
tCSP
tCEM (Note 3)
CE#
UB#/LB#
WE#
tSP tHD
OE#
tCEW
tKHTL
WAIT
Notes:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE in fixed latency mode:
fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.
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Figure 45: Asynchronous WRITE followed by Burst READ
tCLK
CLK
tAW
tWR
VALID
ADDRESS
VALID
ADDRESS
Address
tACLK
tKOH
tSP tHD
tDS tDH
DQ0-
DQ15
VALID
DATA
VALID
OUTPUT
tVS
tSP tHD
tVP
ADV#
CE#
tCVS
NOTE2
tCBPH
tCSP
tHD
tCW
tSP
tHD
tBW
UB#/LB#
WE#
tWP
tOLZ
tBOE
OE#
tHZ
tKHTL
HiZ
WAIT
Notes:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: fixed or variable
latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh
opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
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Figure 46: Asynchronous WRITE (ADV# LOW) followed by Burst READ
tCLK
tWC
CLK
tWR
tAW
VALID
ADDRESS
VALID
ADDRESS
Address
tLZ
tWHZ
tAS
tACLK
tKOH
tDW
tDH
tSP tHD
DQ0-
DQ15
VALID
OUTPUT
VALID
DATA
tSP tHD
ADV#
CE#
NOTE2
tCBPH
tCSP
tHD
tCW
tSP
tHD
tBW
UB#/LB#
WE#
tWPH
tWP
tOLZ
tBOE
OE#
tHZ
tHZ
tCEW
tKHTL
HiZ
HiZ
WAIT
Notes:
1. Non-default BCR settings for asynchronous WRITE followed by burst READ: fixed or variable
latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh
opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
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Figure 47: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
tABA
tCLK
tWC
tAW
CLK
tWR
VALID
ADDRESS
VALID
ADDRESS
Address
tWHZ
tAS
tACLK
tKOH
tSP tHD
tDW
tDH
DQ0-
DQ15
VALID
OUTPUT
VALID
DATA
tLZ
tSP tHD
ADV#
CE#
tCSP
tHD
tCEM
tCW
tSP
tHD
tBW
UB#/LB#
WE#
tWP
tOLZ
tBOE
OE#
tHZ
tHZ
tCEW
tCEW
tKHTL
HiZ
HiZ
WAIT
Notes:
1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE:
fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh
opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
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Figure 48: Burst READ Followed by Asynchronous WRITE Using ADV#
tABA
tCLK
tWC
tAW
CLK
tWR
VALID
ADDRESS
VALID
ADDRESS
Address
tWHZ
tAS
tACLK
tKOH
tSP tHD
tDW tDH
DQ0-
DQ15
VALID
OUTPUT
VALID
DATA
tLZ
tSP tHD
ADV#
CE#
tCSP
tHD
tCVS
tCEM
tCW
tSP
tHD
tBW
UB#/LB#
WE#
tWP
tOLZ
tBOE
OE#
tHZ
tHZ
tCEW
tCEW
tKHTL
HiZ
HiZ
WAIT
HiZ
Notes:
1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed
or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must
go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh
opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the
following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns.
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Figure 49: Asynchronous WRITE followed by Asynchronous READ – ADV# LOW
tWC
tAW
tWR
tRC
VALID
ADDRESS
VALID
ADDRESS
Address
tLZ
tWHZ
tAS
tDW
tDH
tAA
DQ0-
DQ15
VALID
DATA
VALID
OUTPUT
ADV#
CE#
tHZ
tHZ
tCPH
tCW
tCO
Note1
tBHZ
tBLZ
tBA
tBW
UB#/LB#
WE#
tOHZ
tOLZ
tOE
tWPH
tWP
OE#
tHZ
tCEW
tCEW
HiZ
HiZ
HiZ
WAIT
Notes:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required
after CE#-controlled WRITEs.
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Figure 50: Asynchronous WRITE followed by Asynchronous READ
tWC
tAW
tWR
tRC
VALID
ADDRESS
VALID
ADDRESS
Address
tWHZ
tAS
tDW
tDH
tAA
DQ0-
DQ15
VALID
OUTPUT
VALID
DATA
tLZ
ADV#
CE#
tCVS
tCO
tHZ
tCW
tBHZ
tBLZ
tBA
tBW
UB#/LB#
tOHZ
tOLZ
tOE
tWPH
tWP
OE#
WE#
tHZ
tCEW
tCEW
tHZ
HiZ
HiZ
HiZ
WAIT
Notes:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required
after CE#-controlled WRITEs.
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Ordering Information – VDD = 1.8V
Industrial Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Frequency
(MHz)
Order Part No.
Package
2Mx16
70
104
80
IS66WVC2M16ALL-7010BLI
IS66WVC2M16ALL-7008BLI
54-ball VFBGA
54-ball VFBGA
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