IS66WVE2M16BLL [ISSI]
Asynchronous and page mode interface;
| 型号： | IS66WVE2M16BLL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Asynchronous and page mode interface |
| 文件： | 总31页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS66/67WVE2M16EALL/BLL/CLL
32Mb Async/Page PSRAM
PRELIMINARY INFORMATION
Overview
The IS66/67WVE2M16EALL/BLL/CLL is an integrated memory device containing 32Mbit Pseudo Static
Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device
includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of
the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has
separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device
core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 55ns, 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 23mA
Standby < 180 µA (max.)
Deep power-down (DPD)
ALL/CLL: < 3µA (Typ)
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Package:
48-ball TFBGA
BLL: < 10µA (Typ)
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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General Description
PSRAM products are high-speed, CMOS pseudo-static random access memory developed
for low-power, portable applications. The 32Mb DRAM core device is organized
as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory
interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus, PSRAM products incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
A user-accessible configuration registers (CR) defines how the PSRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special attention has been focused on current consumption during self-refresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the CR.
A0~A20
Address
Decode Logic
Input
/Output
Mux
2M X 16
DRAM
Memory Array
And
Buffers
Configuration Register
(CR)
CE#
WE#
OE#
LB#
UB#
ZZ#
Control
Logic
DQ0~DQ15
[ Functional Block Diagram]
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48Ball TFBGA Ball Assignment
1
2
3
4
5
6
LB#
A
OE#
UB#
DQ10
DQ11
DQ12
DQ13
A19
A0
A3
A1
A4
A2
ZZ#
DQ0
DQ2
VDD
VSS
DQ6
DQ7
A20
DQ8
B
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
DQ9
C
A5
A6
VSSQ
D
A17
NC
A7
VDDQ
E
A16
A15
A13
A10
DQ14
F
A14
A12
A9
DQ15
G
A18
A8
H
[Top View]
(Ball Down)
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Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VSS
Type
Description
Power Supply
Power Supply
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
VSSQ
DQ0~DQ15 Input / Output Data Inputs/Outputs (DQ0~DQ15)
A0~A20
LB#
Input
Input
Input
Input
Input
Input
Input
Address Input(A0~A20)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
UB#
CE#
OE#
WE#
ZZ#
Write Enable
Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device
can enter one of two low-power modes ( DPD or PAR).
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
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Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
DQ
Note
Mode
Power
CE#
WE#
OE#
UB#/LB#
ZZ#
[15:0]4
High-Z
Data-Out
Data-In
X
Standby
Read
Standby
Active
Active
Idle
H
L
X
H
L
X
L
X
L
H
H
H
H
L
2,5
1,4
1,3,4
4,5
6
Write
L
X
X
X
X
L
No operation
PAR
L
X
X
X
X
X
X
PAR
H
H
High-Z
High-Z
DPD
DPD
L
6
Load
Configuration
register
Active
L
L
X
X
L
High-Z
Notes
1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8~DQ15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
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Functional Description
In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular
in low-power, portable applications.
The 32Mb device contains a 32Mb DRAM core organized as 2,097,152 addresses by
16 bits. This device include the industry-standard, asynchronous memory interface found on
other low-power SRAM or PSRAM offerings
Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
PSRAM products include an on-chip voltage sensor that is used to launch the power-up
initialization process. Initialization will load the CR with its default settings (see Table 3).
VDD and VDDQ must be applied simultaneously. When they reach a stable level above
VDD, the device will require 150μs to complete its self-initialization process ( see Figure 1).
During the initialization period, CE# should remain HIGH. When initialization is complete,
the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD
tPU > 150us
Device ready for
normal operation
VDD
Device Initialization
VDDQ
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Bus Operating Modes
PSRAM products incorporates the industry-standard, asynchronous interface. This bus interface
supports asynchronous Read and WRITE operations as well as page mode READ operation for
enhanced bandwidth. The supported interface is defined by the value loaded into the CR.
Asynchronous Mode Operation
PSRAM products power up in the asynchronous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#).
READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH
(see Figure 2). Valid data will be driven out of the I/Os after the specified access time has elapsed.
WRITE operations occur when CE#,WE#, and LB#/UB# are driven LOW (see Figure 3). During
WRITE operations, the level of OE# is a “Don’t Care”; WE# overrides OE#. The data to be written is
latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. CE# or WE# LOW time
must be limited to tCEM.
Figure 2. Asynchronous Read Operation
tRC = READ cycle Time
VALID
ADDRESS
Address
DQ0-
DQ15
VALID
DATA
CE#
< tCEM
UB#/LB#
OE#
WE#
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Figure 3. Asynchronous WRITE operation
tWC = WRITE cycle Time
VALID
ADDRESS
Address
DQ0-
DQ15
VALID
DATA
CE#
< tCEM
UB#/LB#
WE#
< tCEM
OE#
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Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
preformed, then adjacent addresses can be read quickly by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
PSRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time.
Figure 4 shows the timing for a page mode access.
Page mode takes advantage of the fact that adjacent addresses can be read faster than
random addresses. WRITE operations do not include comparable page mode functionality.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than tCEM.
Figure 4. Page Mode READ Operation
Address
ADD0
ADD1
ADD2
ADD3
tAA
tAPA
tAPA
tAPA
DQ0-
DQ15
D0
D1
D2
D3
CE#
< tCEM
UB#/LB#
OE#
WE#
UB#/LB# Operation
The UB#/LB# enable signals accommodate byte-wide data transfers. During READ operations,
enabled bytes are driven onto the DQ. The DQ signals associated with a disabled byte are
put into a High-Z state during a READ operation. During WRITE operations, disabled bytes
are not transferred to the memory array. and the internal value remains unchanged. During
a WRITE cycle the data to be written is latched on the rising edge of CE#, WE#, LB# or UB#,
whichever occurs first.
When both the UB#/LB# are disabled (HIGH) during an operation, the device prevents the
data bus from receiving or transmitting data. Although the device may appear to be deselected,
it remains in active mode as long as CE# remains LOW.
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Low-Power Feature
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# and ZZ# are HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operations when the address and control inputs remain static for an extended period of time.
This mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the
device operating temperature. DRAM technology requires more frequent refresh operations to
maintain data integrity as temperatures increase. More frequent refresh is required due to the
increased leakage of the DRAM's capacitive storage elements as temperatures rise. A decreased
refresh rate at lower temperatures will result in a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C, +45°C, +70°C,
and +85°C. The setting selected must be for a temperature higher than the case temperature of
the device. If the case temperature is +50°C, the system can minimize self refresh current
consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in
inadequate refreshing and cause data corruption.
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Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array that is absolutely necessary. The refresh options are full array,
and none of the array. Data stored in addresses not receiving refresh will become
corrupted. Read and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1).
PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10us.
Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immediately
available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software-access sequence (see “Software
Access to the Configuration Register”). Using this method, PAR is enabled
immediately upon setting CR[4] to “1” However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, even though ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the PSRAM device. Any
stored data will become corrupted upon entering DPD. When refresh activity has been
re-enabled, the PSRAM device will require 150μs to perform an initialization procedure
before normal operations can resume. READ and WRITE operations are ignored during
DPD operation.
The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] =0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10us. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150us initialization process. During
this time, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set
HIGH (CR[4] = 1).
The device should not be put into DPD using the CR software-access sequence.
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Configuration Registers Operation
The configuration register (CR) defines how the PSRAM device performs a transparent self refresh.
Altering the refresh parameters can dramatically reduce current consumption during standby mode.
Page mode controls is embedded in the CR. This register can be updated any time the device is
operating in a standby state. The control bits used in the CR are shown in Table 3. At power-up,
the CR is set to 0070h.
Access Using ZZ#
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-to-LOW
transition (see Figure 5). The values placed on addresses A[20:0] are latched into the CR on the
rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ#
is WRITE only.
Figure 5: Load Configuration Register Operation Using ZZ#
VALID
ADDRESS
Address
CE#
WE#
t < 500ns
ZZ#
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Software Access Sequence
The contents of the CR can be read or modified using a software access sequence. The
nature of this access mechanism can potentially eliminate the need for the ZZ# ball.
If the software-access mechanism is used, ZZ# can simply be tied to VDDQ; the port line
typically used for ZZ# control purposes will no longer be required. However, ZZ# should
not be tied to VDDQ if the system will use DPD; DPD cannot be enabled or disabled using
the software-access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed
by two WRITE operations (see Figure 6). The READ sequence is virtually identical
except that an asynchronous READ is performed during the fourth operation (see
Figure 7).
The address used during all READ and WRITE operations is the highest address of the
PSRAM device being accessed (1FFFFFh); the content of this address is not changed by
using the software-access sequence. The data bus is used to transfer data into or out of
bit[15:0] of the CR.
Writing to the CR using the software-access sequence modifies the function of the ZZ#
ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables
PAR operation. PAR operation is updated whenever the software-access sequence loads
a new value into the CR. This ZZ# functionality will remain active until the next time the
device is powered up. The operation of the ZZ# ball is not affected if the software-access
sequence is only used to read the contents of the CR. Use of the software-access sequence
does not affect the performance of standard (ZZ#-controlled) CR loading.
Figure 6 : Configuration Register Write
MAX
MAX
MAX
MAX
Address
ADDRESS
ADDRESS
ADDRESS
ADDRESS
DQ0-
DQ15
OUTPUT
DATA
OUTPUT
DATA
CR
*Note1
VALUE IN
Read
Read
Write
Write
CE#
UB#/LB#
WE#
OE#
Notes :
1. CR : 0000h
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Figure 7 : Configuration Register Read
MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
MAX
ADDRESS
Address
DQ0-
OUTPUT
DATA
OUTPUT
DATA
CR
VALUE OUT
*Note1
DQ15
Read
Read
Write
Read
CE#
UB#/LB#
WE#
OE#
Notes :
1. CR : 0000h
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Table 3. Configuration Register
Remark
Bit Number
Definition
Reserved
20 – 8
All Must be set to “0”
0 = Page mode disabled (default)
1 = Page mode enabled
7
Page
TCR
1 1 = +85°C (default)
0 0 = +70°C
0 1 = +45°C
6 – 5
1 0 = +15°C
0 = DPD enabled
1 = PAR enabled (default)
4
3
Sleep
Reserved
Must be set to “0”
000 = Full array (default)
100 = None of array
2 – 0
PAR1
Notes :
1. Use of other setting will result in full-array refresh coverage.
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Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
The PAR bits restrict REFRESH operation to a portion of the total memory array. The
refresh options are “full array” and “ none of the array.”
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit defines the low-power mode to be entered when ZZ# is driven LOW.
If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can
also be enabled directly by writing to the CR using the software-access sequence. Note
that this disables ZZ# initiation of PAR. DPD cannot properly be enabled or disabled
using the software-access sequence; DPD should only be enabled or disabled using ZZ#
to access the CR.
DPD operation disables all refresh-related activity. This mode is used when the system
does not require the storage provided by the PSRAM device. When DPD is enabled, any
stored data will become corrupted. When refresh activity has been re-enabled. The
PSRAM device will require 150us to perform an initialization procedure before normal
operation can resume. DPD should not be enabled using CR software access.
Temperature Compensated Refresh (CR[6:5]) Default = +85oC Operation
Temperature compensated refresh register bits can be programmed using the CR [5, 6]
configuration registers and has four different temperature levels: +15°C, +45°C, +70°C, and
+85°C. The temperature selected must be equal to or higher than the case temperature of
the device. Setting a lower temperature level would cause data to be corrupted due to
insufficient refresh rate.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are enabled
In the power-up default state, page mode is disabled.
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Electrical Characteristics (ALL)
Table 4. Absolute Maximum Ratings
Parameter
Rating
-0.5V to (4.0V or VDDQ + 0.3V, whichever is less)
-0.2V to + 2.45V
Voltage to Any Ball Except VDD, VDDQ Relative to VSS
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Storage Temperature (plastic)
-0.2V to + 2.45V
-55°Cto + 150°C
Operating Temperature
-40°C to + 85°C
Soldering Temperature and Time
10s (solder ball only)
+ 260°C
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Table 5. Electrical Characteristics and Operating Conditions
Operating Temperature (–40ºC < TC < +85ºC)
Description
Conditions
Symbol
MIN
1.7
MAX
1.95
Unit
Note
Supply Voltage
VDD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VDDQ
VIH
VIL
1.7
1.95
VDDQ-0.4
-0.2
VDDQ+0.2
0.4
V
1
2
V
IOH = -0.2mA
IOL = +0.2mA
VIN = 0 to VDDQ
VOH
VOL
ILI
0.8 VDDQ
V
0.2 VDDQ
1
V
uA
OE#=VIH or
Chip Disabled
Output Leakage Current
ILO
1
uA
Unit
mA
Operating Current
Conditions
Symbol
Typ
MAX
30
Note
Asynchronous Random
READ/WRITE
IDD1
IDD1P
ISB
-70
-70
3
VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
Asynchronous
PAGE READ
20
mA
uA
3
4
VIN=VDDQ or 0V
CE# = VDDQ
Standby Current
180
Notes:
1. Input signals may overshoot to VDDQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS – 1.0V for periods less than 2ns during transitions.
3. This parameter is specified with the outputs disabled to avoid external loading effects.
User must add required current to drive output capacitance expected in the actual system.
4. ISB (MAX) values measured with PAR set to FULL ARRAY at +85°C. In order to achieve low
standby current, all inputs must be driven to either VDDQ or VSS. ISB might be set slightly
higher for up to 500ms after power-up, or when entering standby mode.
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Electrical Characteristics (BLL)
Table 6. Absolute Maximum Ratings
Parameter
Rating
-0.5V to (4.0V or VDDQ + 0.3V, whichever is less)
-0.2V to + 4.0V
Voltage to Any Ball Except VDD, VDDQ Relative to VSS
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Storage Temperature (plastic)
-0.2V to + 4.0V
-55°Cto + 150°C
Operating Temperature
-40°C to + 85°C
Soldering Temperature and Time
10s (solder ball only)
+ 260°C
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Table 7. Electrical Characteristics and Operating Conditions
Operating Temperature (–40ºC < TC < +85ºC)
Description
Conditions
Symbol
MIN
2.7
MAX
3.6
Unit
Note
Supply Voltage
VDD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VDDQ
VIH
VIL
2.7
3.6
VDDQ-0.4
-0.2
VDDQ+0.2
0.4
V
1
2
V
IOH = -0.2mA
IOL = +0.2mA
VIN = 0 to VDDQ
VOH
VOL
ILI
0.8 VDDQ
V
0.2 VDDQ
1
V
uA
OE#=VIH or
Chip Disabled
Output Leakage Current
ILO
1
uA
Unit
mA
Operating Current
Conditions
Symbol
Typ
MAX
30
Note
Asynchronous Random
READ/WRITE
IDD1
IDD1P
ISB
-70
-70
3
VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
Asynchronous
PAGE READ
23
mA
uA
3
4
VIN=VDDQ or 0V
CE# = VDDQ
Standby Current
180
Notes:
1. Input signals may overshoot to VDDQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS – 1.0V for periods less than 2ns during transitions.
3. This parameter is specified with the outputs disabled to avoid external loading effects.
User must add required current to drive output capacitance expected in the actual system.
4. ISB (MAX) values measured with PAR set to FULL ARRAY at +85°C. In order to achieve low
standby current, all inputs must be driven to either VDDQ or VSS. ISB might be set slightly
higher for up to 500ms after power-up, or when entering standby mode.
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IS66/67WVE2M16EALL/BLL/CLL
Electrical Characteristics (CLL)
Table 8. Absolute Maximum Ratings
Parameter
Rating
-0.5V to (4.0V or VDDQ + 0.3V, whichever is less)
-0.2V to + 2.45V
Voltage to Any Ball Except VDD, VDDQ Relative to VSS
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Storage Temperature (plastic)
-0.2V to + 4.0V
-55°Cto + 150°C
Operating Temperature
-40°C to + 85°C
Soldering Temperature and Time
10s (solder ball only)
+ 260°C
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other
conditions above those indicated in this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Table 9. Electrical Characteristics and Operating Conditions
Operating Temperature (–40ºC < TC < +85ºC)
Description
Conditions
Symbol
MIN
1.7
MAX
1.95
Unit
Note
Supply Voltage
VDD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VDDQ
VIH
VIL
2.7
3.6
VDDQ-0.4
-0.2
VDDQ+0.2
0.4
V
1
2
V
IOH = -0.2mA
IOL = +0.2mA
VIN = 0 to VDDQ
VOH
VOL
ILI
0.8 VDDQ
V
0.2 VDDQ
1
V
uA
OE#=VIH or
Chip Disabled
Output Leakage Current
ILO
1
uA
Unit
mA
Operating Current
Conditions
Symbol
Typ
MAX
30
Note
Asynchronous Random
READ/WRITE
IDD1
IDD1P
ISB
-70
-70
3
VIN = VDDQ or 0V
Chip enabled,
IOUT = 0
Asynchronous
PAGE READ
20
mA
uA
3
4
VIN=VDDQ or 0V
CE# = VDDQ
Standby Current
180
Notes:
1. Input signals may overshoot to VDDQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS – 1.0V for periods less than 2ns during transitions.
3. This parameter is specified with the outputs disabled to avoid external loading effects.
User must add required current to drive output capacitance expected in the actual system.
4. ISB (MAX) values measured with PAR set to FULL ARRAY at +85°C. In order to achieve low
standby current, all inputs must be driven to either VDDQ or VSS. ISB might be set slightly
higher for up to 500ms after power-up, or when entering standby mode.
19
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IS66/67WVE2M16EALL/BLL/CLL
Table 10. Deep Power-Down Specifications
Description
Conditions
Symbol
TYP
MAX
Unit
VIN=VDDQ or 0V; +25°C
ZZ# = 0V, CR[4] = 0
Deep Power-Down
(ALL/CLL)
Izz
3
10
uA
VIN=VDDQ or 0V; +25°C
ZZ# = 0V, CR[4] = 0
Deep Power-Down
(BLL)
Izz
10
20
uA
Table 11. Capacitance
Description
Conditions
Symbol
MIN
MAX
Unit
Note
TC=+25°C;
f=1Mhz;
VIN=0V
Input Capacitance
CIN
2.0
3.5
6.5
pF
pF
1
Input/Output Capacitance (DQ)
CIO
6.5
1
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
Figure 8. AC Input/Output Reference Waveform
VDDQ
∫∫
Test Points
∫∫
VDDQ/22 Input1
VDDQ/23 Output
VSS
Notes:
1. AC test inputs are driven at VDDQ for a logic 1 and VSS for a logic 0. Input rise and fall times
(10% to 90%) < 1.6ns.
2. Input timing begins at VDDQ/2.
3. Output timing ends at VDDQ/2.
Figure 9. Output Load Circuit
Test Point
50Ω
DUT
VDDQ/2
30pF
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IS66/67WVE2M16EALL/BLL/CLL
AC Characteristics
Table 12. Asynchronous READ Cycle Timing Requirements
-55
-70
Symbol
Parameter
Unit
Notes
Min
Max
55
Min
Max
70
tAA
tAPA
tBA
Address Acess Time
Page access Time
ns
ns
ns
20
20
LB# /UB# access Time
55
70
LB#/UB# disable to High-Z
output
tBHZ
tBLZ
8
8
ns
ns
1
2
LB#/UB# enable to Low-Z
output
10
10
tCEM
tCO
tHZ
tLZ
Maximum CE# pulse width
Chip select access time
8
55
8
8
70
8
us
ns
ns
ns
ns
Chip disable to High-Z output
Chip enable to Low-Z output
Output enable to valid output
1
2
10
5
10
5
tOE
20
8
20
8
Output hold from address
change
tOH
tOHZ
tOLZ
ns
ns
ns
Output disable to High-Z
output
1
2
Output enable to Low-Z
output
3
3
tPC
tRC
Page cycle time
20
55
5
20
70
5
ns
ns
ns
Read cycle time
3
tCPH
CE# HIGH time Read
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with CE#
HIGH transition.
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IS66/67WVE2M16EALL/BLL/CLL
Table 13 . Asynchronous WRITE Cycle Timing Requirements
-55
-70
Symbol
Parameter
Unit
Notes
Min
0
Max
Min
0
Max
tAS
tAW
Address setup Time
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Byte select to end of write
Maximum CE# pulse width
CE# HIGH time during write
Chip enable to end of Write
Data hold from write time
Data write setup time
55
55
70
70
tBW
tCEM
tCPH
tCW
8
8
5
55
0
5
70
0
tDH
tDW
23
10
5
23
10
5
tLZ
Chip enable to Low-Z output
End write to Low-Z output
Write cycle time
1
1
tOW
tWC
tWHZ
tWP
tWPH
tWR
55
70
Write to High-Z output
Write pulse width
8
8
2
3
46
10
0
46
10
0
Write pulse width HIGH
Write recovery time
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. Write address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with
CE# HIGH transition.
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IS66/67WVE2M16EALL/BLL/CLL
Table14 . Load Configuration Register Timing Requirements
-55
-70
Symbol
Parameter
Unit
Note
Min
0
Max
Min
0
Max
tAS
tAW
tCDZZ
tCEM
tCW
tWC
tWP
Address setup time
ns
ns
ns
us
ns
ns
ns
ns
ns
Address valid to end of write
Chip deselect to ZZ# LOW
Maximum CE# pulse width
Chip enable to end of write
Write cycle time
55
5
70
5
8
8
55
55
46
0
70
70
46
0
Write pulse width
tWR
Write recovery time
1
tZZWE
ZZ# LOW to WE# LOW
10
500
10
500
Notes:
1. Write address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with
CE# HIGH transition.
Table15 . DPD Timing Requirements
-55
-70
Symbol
Parameter
Unit
Notes
Min
5
Max
Min
5
Max
tCDZZ
tR
Chip deselect to ZZ# LOW
Deep Power-down recovery
Minimum ZZ# pulse width
ns
us
us
150
10
150
10
tZZ(MIN)
Table16 . Initialization Timing Requirements
-55
-70
Symbol
tPU
Parameter
Unit
Notes
Min
Max
150
Min
Max
150
Initialization Period (required
before normal operations)
us
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IS66/67WVE2M16EALL/BLL/CLL
Timing Diagrams
Figure 10: Power-Up Initialization Timing
VDD, VDDQ
VDD(MIN)
tPU > 150us
Device Initialization
Device ready for
normal operation
Figure 11: Load Configuration Register
tWC
Address
CE#
OPCODE
tAW
tWR
tCW
UB#/LB#
WE#
tWP
tAS
OE#
ZZ#
tCDZZ
tZZWE
Figure 12: DPD Entry and Exit Timing
tCDZZ
tZZ (MIN)
ZZ#
CE#
tR
Device ready for
normal operation
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IS66/67WVE2M16EALL/BLL/CLL
Figure 13: Single Read Operation
tRC
VALID
ADDRESS
Address
tAA
DQ0-
DQ15
VALID
OUTPUT
tCO
tHZ
CE#
tLZ (tBLZ
)
tBHZ
tBA
UB#/LB#
tOHZ
tOLZ
tOE
OE#
WE#
Figure 14: PAGE MODE READ
tRC
VALID
ADDRESS
A4-A20
A0-A3
tPC
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
tAA
tAPA
DQ0-
DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tOH
tCO
tHZ
CE#
tLZ
tBHZ
tBA
UB#/LB#
OE#
tOHZ
tOLZ
tOE
WE#
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IS66/67WVE2M16EALL/BLL/CLL
Figure 15: CE#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID or INVALID
OUTPUT
VALID
INPUT
tAS tLZ
tDW
tDH
tWHZ
tCW
tCPH
CE#
tBW
UB#/LB#
OE#
1
tOW
tWP
WE#
Note:
1. tDH shouldn’t be longer than tOW when End of Write changes operating mode into READ.
26
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IS66/67WVE2M16EALL/BLL/CLL
Figure 16: LB#/UB#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID
INPUT
VALID or INVALID
OUTPUT
tAS
tLZ
tDW
tDH
tWHZ
tCW
tHZ
CE#
tAS
tBW
UB#/LB#
OE#
1
tOW
tWP
WE#
Note:
1. tDH shouldn’t be longer than tOW when End of Write changes operating mode into READ.
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IS66/67WVE2M16EALL/BLL/CLL
Figure 17: WE#-Controlled Asynchronous WRITE
tWC
VALID
ADDRESS
Address
tAW
tWR
DQ0-
DQ15
VALID
INPUT
VALID or INVALID
OUTPUT
tLZ
tDW
tDH
tWHZ
tAS
tCW
tHZ
CE#
tBW
UB#/LB#
tAS
OE#
1
tOW
tWPH
tWP
WE#
Note:
1. tDH shouldn’t be longer than tOW when End of Write changes operating mode into READ.
28
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IS66/67WVE2M16EALL/BLL/CLL
Ordering Information
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Industrial Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
70
IS66WVE2M16EALL-70BLI
IS66WVE2M16EALL-70BI
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
Ordering Information
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Industrial Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
55
IS66WVE2M16EBLL-55BLI
IS66WVE2M16EBLL-55BI
IS66WVE2M16EBLL-70BLI
IS66WVE2M16EBLL-70BI
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
70
Ordering Information
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Industrial Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
70
IS66WVE2M16ECLL-70BLI
IS66WVE2M16ECLL-70BI
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
29
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IS66/67WVE2M16EALL/BLL/CLL
Ordering Information
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Automotive (A1) Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
70
IS67WVE2M16EALL-70BLA1
IS67WVE2M16EALL-70BA1
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
Ordering Information
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Automotive (A1) Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
70
IS67WVE2M16EBLL-70BLA1
IS67WVE2M16EBLL-70BA1
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
Ordering Information
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Automotive (A1) Temperature Range: (-40oC to +85oC)
Config.
Speed
(ns)
Orderable Part No.
Package
2Mx16
70
IS67WVE2M16ECLL-70BLA1
IS67WVE2M16ECLL-70BA1
48-ball TFBGA, Lead-free
48-ball TFBGA, Leaded
30
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IS66/67WVE2M16EALL/BLL/CLL
31
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Rev. 0D | November 2014
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