IS75V16F64GS16-7080DI [ISSI]
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP); 64兆位闪存16兆位伪SRAM堆叠式多芯片封装（ MCP ）
| 型号： | IS75V16F64GS16-7080DI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP) |
| 文件： | 总50页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
75V16F64GS16
ISSI
64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM
STACKED MULTI-CHIP PACKAGE (MCP)
PRELIMINARY INFORMATION
AUGUST 2002
MCP FEATURES
• Power supply voltage of 2.7 to 3.1 volt
• High performance:
- Flash access time as fast as 70 ns
- PSRAM access time as fast as 80 ns
• Package: 65-Ball FBGA
• WP/ACC Input Pin
- At VIL, allows protection of “outermost” 2 × 8 Kbytes
on both ends of boot sectors, regardless of sector
protection/unprotection status
- At VIH, allows removal of boot sector protection
- At VACC, program time will be reduced by 40 %
• Operating Temperature: –30°C to +85°C
• Embedded EraseTM Algorithms
- Automatically preprograms and erases the chip
or any sector
• Embedded ProgramTM Algorithms
- Automatically writes and verifies data at specified
address
• Data Polling and Toggle Bit Feature for Detection of
Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
- Hardware method for detection of program or
erase cycle completion
FLASH MEMORY FEATURES
• 0.16 µm Process Technology
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBankTM architecture
- Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Bank B : 24 Mbit (64 KB x 48)
- Bank C : 24 Mbit (64 KB x 48)
- Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
- Two virtual Banks are chosen from the combination
of four physical banks (Refer to "Example of Virtual
Banks Combination Table" and Simultaneous
Operation Table" in FLEXIBLE SECTOR-ERASE
ARCHITECTURE on FLASH MEMORY)
- Host system can program or erase in one bank, and
then read immediately and simultaneously from the
other bank with zero latency between read and write
operations.
• Automatic Sleep Mode
- When addresses remain stable, the device
automatically switches itself to low power mode.
• Low VCCf Write Inhibit ≤ 2.5 V
• Program Suspend/Resume
- Suspends the program operation to allow a read
in another byte
- Read-while-erase
- Read-while-program
• Erase Suspend/Resume
- Suspends the erase operation to allow a read
data and/or program in another sector within the
same device
• Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
- Sixteen 4 Kword and one hundred twenty-six 32
Kword sectors in word
PSRAM FEATURES
• Power Dissipation:
- Any combination of sectors can be concurrently
erased
- Operating
- Standby
: 20 mA Max
: 70 µA Max
- Supports full chip erase
- Power Down : 10 µA Max
• Hidden ROM (Hi-ROM) Region
• Power down Control by CE2r
• Byte Write Control : LB (DQ7-DQ0), UB (DQ15-DQ8)
• 4 words Address Access Capability
- 256 byte of Hi-ROM, accessible through a new "HI-
ROM Enable" command sequence
- Factory serialized and protected to provide a secure
electronic serial number (ESN)
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
1
08/01/02
®
75V16F64GS16
ISSI
PIN CONFIGURATION (64 Mb Flash and 16 Mb PSRAM)
PACKAGE CODE: D 65 BALL FBGA (Top View) (9.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
A
B
C
D
E
F
G
H
J
K
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
A16
NC
A15
NC
A14
A10
A21
A13
A9
Vccf
GND
A11
A12
A19
DQ15 DQ7 DQ14
DQ13 DQ12 DQ5
A8
WE
DQ6
CE2r
A20
DQ4
DQ3
Vccr
NC
WP/ACC
LB
RESET RY/BY
Vccf DQ11
UB
A6
A3
A18
A5
A17
A4
DQ1
GND
A0
DQ9 DQ10 DQ2
Common
A7
OE
DQ0 DQ8
Flash Only
PSRAM Only
A1
NC
NC
NC
NC
A2
CEf
CE1r
NC
PIN DESCRIPTIONS
A0-A19
Address Inputs, Common
Address Inputs, Flash
LB
Lower-byte Control, PSRAM
Upper-byte Control, PSRAM
A20-A21
UB
DQ0-DQ15 Data Inputs/Outputs, Common
RESET
CE1r,CE2r Chip Enable, PSRAM
WP/ACC Write Protect/Acceleration, Flash
Hardware Reset Pin/Acceleration, Flash
RY/BY
NC
Ready/Busy Output
No Internal Connection
Device Power Supply, Flash
Device Ground, Common
Device Power, PSRAM
RY/BY
CEf
Ready/Busy Output, Flash Open Drain Output
Chip Enable, Flash
Vccf
GND
Vccr
OE
Output Enable, Common
Write Enable, Common
WE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
MCP BLOCK DIAGRAM
Vcc
f
GND
A21-A0
RY/BY
A21-A0
WP/ACC
RESET
CEf
64-MBIT
Flash Memory
DQ15-DQ0
DQ15-DQ0
V
CCr GND
A19-A0
LB
UB
DQ15-DQ0
WE
16-MBIT
Static PSRAM
OE
CE1r
CE2r
LOGIC SYMBOL
22
A21-A0
CEf
CE1r
CE2r
OE
RY/BY
WE
x16
WP/ACC
RESET
UB
DQ15-DQ0
LB
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
3
08/01/02
®
75V16F64GS16
ISSI
FLASH MEMORY BLOCK DIAGRAM
OE
V
CC
GND
A21-A0
Upper Bank Address
Upper Bank
X-Decoder
DQ15-DQ0
A21-A0
A21-A0
RESET
WE
STATE
CONTROL
&
DQ15-DQ0
Status
CE
COMMAND
REGISTER
WP/ACC
Control
DQ15-DQ0
X-Decoder
Lower Bank
A21-A0
DQ15-DQ0
A21-A0
Lower Bank Address
OE
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
DEVICE BUS OPERATIONS
OPERATION(1,2)
CEf CE1r CE2r OE
WE
LBs
UBs
DQ7-DQ0 DQ15-DQ8 RESET WP/ACC(7)
Full Standby
H
H
L
L
L
H
L
H
H
H
L
H
X
X
X
X
H
X
H
H
L
H
L
X
H
H
H
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
H
H
X
X
X
X
X
X
Output Disable(3)
Read from Flash(4)
Write to Flash
Read from PSRAM(5)
Write to PSRAM
DOUT
DIN
DOUT
DIN
H
H
DOUT
DIN
DOUT
DIN
H
L
H
H
L
H
L
L
H
High-Z
DIN
DIN
High-Z
H
X
Temporary
Sector
X
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
VID
X
X
Group Unprotection(6)
Flash Hardware
Reset
High-Z High-Z
L
Boot Block
Sector Write
Protection
PSRAM Power Down(8)
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations not indicated in this table are prohibited.
2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1 ms.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. PSRAM Byte control at Read operation is not supported.
6. Also used for the extended sector group protections.
7. Protects “outermost” 2 ´ 8 Kbytes (4 words) on both ends of the boot block sectors.
8. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
5
08/01/02
®
75V16F64GS16
ISSI
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY
Bank
Type
Sector
Bank
Type
Sector
Address K-Word Address
Address K-Word Address
BankA SA0
BankA SA1
BankA SA2
BankA SA3
BankA SA4
BankA SA5
BankA SA6
BankA SA7
BankA SA8
BankA SA9
BankA SA10
BankA SA11
BankA SA12
BankA SA13
BankA SA14
BankA SA15
BankA SA16
BankA SA17
BankA SA18
BankA SA19
BankA SA20
BankA SA21
BankA SA22
BankB SA23
BankB SA24
BankB SA25
BankB SA26
BankB SA27
BankB SA28
BankB SA29
BankB SA30
BankB SA31
BankB SA32
BankB SA33
BankB SA34
BankB SA35
4
4
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
BankB
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
200000h
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
BankC SA71
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH MEMORY (Continued)
Bank
Type
Sector
Bank
Type
Sector
Address K-Word Address
Address K-Word Address
BankC SA72
BankC SA73
BankC SA74
BankC SA75
BankC SA76
BankC SA77
BankC SA78
BankC SA79
BankC SA80
BankC SA81
BankC SA82
BankC SA83
BankC SA84
BankC SA85
BankC SA86
BankC SA87
BankC SA88
BankC SA89
BankC SA90
BankC SA91
BankC SA92
BankC SA93
BankC SA94
BankC SA95
BankC SA96
BankC SA97
BankC SA98
BankC SA99
BankC SA100
BankC SA101
BankC SA102
BankC SA103
BankC SA104
BankC SA105
BankC SA106
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
BankC SA107
BankC SA108
BankC SA109
BankC SA110
BankC SA111
BankC SA112
BankC SA113
BankC SA114
BankC SA115
BankC SA116
BankC SA117
BankC SA118
BankD SA119
BankD SA120
BankD SA121
BankD SA122
BankD SA123
BankD SA124
BankD SA125
BankD SA126
BankD SA127
BankD SA128
BankD SA129
BankD SA130
BankD SA131
BankD SA132
BankD SA133
BankD SA134
BankD SA135
BankD SA136
BankD SA137
BankD SA138
BankD SA139
BankD SA140
BankD SA141
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3F9000h
3FA000h
3FB000h
3FC000h
3FD000h
3FE000h
3FF000h
4
4
4
4
4
4
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
7
08/01/02
®
75V16F64GS16
ISSI
FLEXBANK TM ARCHITECTURE TABLE
Bank 1
Bank 2
Bank Split
1
Volume
Combination
Volume
Combination
8 Mbit
Bank A
56 Mbit
Bank B, C, D
Bank A, C, D
Bank A, B, D
Bank A, B, C
2
3
4
24 Mbit
24 Mbit
8 Mbit
Bank B
Bank C
Bank D
40 Mbit
40 Mbit
56 Mbit
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE
Bank 1
Bank 2
Bank Split Volume
Combination
Sector Size
8x4 Kword
15x32 Kword
Volume
Combination
Sector Size
1
2
3
8 Mbit
Bank A
56 Mbit Bank B, C, D 8x4 Kword
111x32 Kword
48 Mbit Bank B,C 96x32 Kword
16 Mbit
24 Mbit
32 Mbit
Bank A,D
Bank B
16x4 Kword
30x32 Kword
48x32 Kword
40 Mbit Bank A, C, D 16x4 Kword
78x32 Kword
4
Bank A,B
8x4 Kword
32 Mbit Bank C,D
8x4 Kword
63x32 Kword
63x32 Kword
Notes:
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being
erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They
would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
SIMULTANEOUS OPERATION TABLE
Case
1
Bank 1 Status
Bank 2 Status
Read Mode
Read Mode
2
3
4
5
6
7
Read Mode
Autoselect Mode
Program Mode
Erase Mode (1)
Read Mode
Read Mode
Read Mode
Autoselect Mode
Program Mode
Erase Mode (1)
Read Mode
Read Mode
Note:
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it
enables reading from or programming the remaining sectors.
2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks,
Bank A, Bank B, Bank C and Bank D. Bank Address (BA) means to specify each of the Banks.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
9
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS TABLE
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
SA8
SA9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS TABLE (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
11
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS TABLE (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS TABLE (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
13
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS GROUP TABLE
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
1
SGA8
0
0
0
0
0
1
0
X
X
X
SA8 to SA10
1
1
SGA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
SECTOR ADDRESS GROUP TABLE (Continued)
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
SGA39
1
1
1
1
1
X
X
X
SA131 to SA133
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
FLASH MEMORY AUTOSELECT CODES TABLE
Type
A21 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacture's Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
227Eh
Extended Device
Code(2)
BA
BA
L
L
L
H
H
L
H
H
L
H
H
H
L
H
L
2202h
2201h
01h(1)
Sector Group
Protection
Sector Group
Address
Legend: L = VIL, H = VIH. See “n DC CHARACTERISTICS” for voltage levels.
Notes:
1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two
additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes
at the address of (BA) 0Eh, as well as at (BA) 0Fh.
.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
15
08/01/02
®
75V16F64GS16
ISSI
FLASH MEMORY COMMAND DEFINITIONS
First Bus
Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Fifth Bus
Cycle
Sixth Bus
Cycle
Bus
Command
Sequence
Write
Cycle
Req'd
Data Addr. Data
Data
—
Addr. Data
Addr. Data
Addr. Data
Addr.
—
Addr.
Read / Reset (1)
—
—
—
—
—
—
—
—
—
—
—
—
—
F0h
AAh
AAh
1
3
3
4
1
1
XXXh
555h
555h
(1)
555h F0h
(BA)
—
—
—
—
—
—
—
—
—
—
Read / Reset
55h
55h
—
—
2AAh
2AAh
RA
—
RD
—
90h
Autoselect
555h
—
—
—
A0h
PA
—
—
PD
—
B0h
30h
2AAh 55h
555h
BA
555h
Program
Program Suspend
—
—
—
—
—
—
BA
Program Resume
Chip Erase
—
—
—
AAh
AAh
55h
—
2AAh
6
6
555h
555h
AAh 2AAh
555h
555h
80h
—
55h
—
10h
—
555h
—
555h
SA
—
—
80h
55h
2AAh
555h
Sector Erase
Erase Suspend
2AAh
B0h
B0h
30h
60h
30h
AAh
55h
—
—
—
1
1
4
—
—
—
—
—
—
—
—
—
—
—
—
BA
BA
—
—
—
—
—
—
—
—
Erase Resume
—
Extended Sector
Group Protection
60h
SPA
SPA
40h
XXXh
SPA
SD
(3)
Set to Fast
Mode (2)
20h
—
—
—
—
—
—
2AAh
PA
555h
XXXh
BA
AAh
A0h
90h
98h
55h
PD
555h
3
2
Flash Program (2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reset from Flash
Mode (2)
(6)
F0H
2
1
3
4
4
XXXh
—
(BA)
55h
Query (4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hi-ROM
Entry
88h
555h
2AAh
AAh
AAh
AAh
55h
55h
55h
555h
555h
Hi-ROM
Program (5)
(HRA)
PA
—
—
—
—
—
—
—
—
2AAh
2AAh
A0h
90h
555h
555h
PD
Hi-ROM
Exit (5)
(HRBA)
555h
XXXh
00h
Notes:
1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
2. This command is valid during Fast Mode.
3. This command is valid while RESET = VID
4. The valid address is A6 to A0.
5. This command is valid during Hi-ROM mode.
6. The data “00h” is also acceptable.
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH MEMORY COMMAND DEFINITIONS (Continued)
PD = Data to be programmed at location PA. Data is
latched on the rising edge of write pulse.
SPA = Sector group address to be protected.
Set sector group address and (A6, A3, A2, A1, A0) =
(0, 0, 0, 1, 0).
Notes:
Address bits A21 to A11 = X = “H” or “L” for all
address commands except or Program Address (PA),
Sector Address (SA) , and Bank Address (BA) , and
Sector Group Address (SPA) .
SD = Sector group protection verify data. Output 01h at
protected sector group addresses and output 00h at
unprotected sector group addresses.
Bus operations are defined in "DEVICE BUS
OPERATIONS”.
RA = Address of the memory location to be read
PA = Address of the memory location to be
programmed
HRA = Address of the Hi-ROM area : 000000h to
00007Fh
HRBA = Bank Address of the Hi-ROM area (A21 = A20
= A19 = VIL)
Addresses are latched on the falling edge of the write
pulse.
The system should generate the following address
patterns : 555h or 2AAh to addresses A10 to A0
Both Read/Reset commands are functionally
equivalent, resetting the device to the read mode.
Command combinations not described in “Flash
Memory Command Definitions” are illegal.
SA = Address of the sector to be erased. The
combination of A21, A20, A19, A18, A17, A16, A15,
A14, A13, and A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
RD = Data read from location RA during read
operation.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
17
08/01/02
®
75V16F64GS16
ISSI
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol Parameter
Min.
–55
–30
Max.
+125
+85
Unit
°C
Tstg
Storage Temperature
TA
Ambient Temperature with Power Applied
°C
VIN
Voltage with Respect to Ground All Pins(1,2)
Voltage with Respect to Ground All Pins(1,2)
VCCf Supply(1)
VCCr Supply(1,3)
RESET(1,3)
–0.3
–0.3
–0.2
-0.2
-0.5
–0.5
VCCf + 0.3
VCCr + 0.3
+3.6
V
V
V
V
V
V
VOUT
VCCf
VCCr
+3.6
VIN
+13.0
VACC
WP/ACC(1,4)
+10.5
Notes:
1. Voltage is defined on the basis of GND = GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot
GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3 V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCr + 1.0 V for periods of up to 5 ns.
3. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot GND
to -2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCr) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot
GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied.
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol Parameter
Min.
–30
Max.
+85
Unit
°C
V
TA
Ambient Temperature
VCCf
VCCr
VCCf Supply Voltages
VCCr Supply Voltages
–2.7
–2.7
+3.1
+3.1
V
Note:
Voltage is defined on the basis of GND = GND = 0 V.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
DC CHARACTERISTICS
Symbol Parameter
Test Conditions
Min.
-1.0
-1.0
—
Typ. Max.
Unit
µA
ILI
Input Leakage
VIN=GND to VCCf, VCCr
VOUT=GND to VCCf, VCCr
—
—
—
+1.0
+1.0
35
ILO
ILIT
Output Leakage
µA
RESET Inputs
VCCf=VCCf max.,
µA
Leakage Current
RESET = 12.5V
ICC1f
FLASH Vcc (1)
Active Current (Read)
CEf=VIL, OE=VIH
tCycle = 5Mhz
tCycle = 1Mhz
—
—
18
mA
—
—
—
—
4
mA
mA
ICC2f
ICC3f
FLASH Vcc Active(2)
Current(Program/Erase) OE=VIH
FLASH Vcc Active(5)
Current
(Read-While-Program)
FLASH Vcc Active(5)
Current
(Read-While-Erase)
CEf=VIL,
35
CEf=VIL,
OE=VIH
—
—
—
—
—
—
—
—
53
53
40
20
mA
mA
mA
mA
ICC4f
ICC5f
CEf=VIL,
OE=VIH
FLASH Vcc Active
Current
(Erase-Suspend-Program)
CEf=VIL,
OE=VIH
IACC
WP/ACC Acceleration
VCCf = Vcc max,
Program Current
WP/ACC = VACC max
ICC1r
PSRAM Vcc Active
Current
VCCr = Vccr max,
CE1r=VIL, CE2r=VIH,
VIN=VIH or VIL,
trc / twc = min
trc / twc = 1 µs
—
—
15
20
mA
mA
2.5
3.0
IOUT=0 mA
ISB1f
ISB2f
ISB3f
FLASH Vcc
Standby Current
VCCf = Vccf max, CEf= VCCf + 0.3V,
RESET = VCCf + 0.3V,
WP/ACC = VCCf + 0.3V
—
—
—
1
1
1
5
5
5
µA
µA
µA
FLASH Vcc
Standby Current
(RESET)
FLASH Vcc(3)
Current
VCCf = Vccf max, RESET= GND + 0.3V,
WP/ACC = VCCf + 0.3V
VCCf = Vcc max., CEf, = GND + 0.3V,
RESET = VCCf + 0.3V,
(Automatic Sleep Mode) WP/ACC = VCCf + 0.3V,
VIN = VCCf + 0.3V OR GND + 0.3V
ISBr
PSRAM Vcc Standby
Current
VCCr = Vccr max, CE1r = CE2R = VIN,
VIN=VIH or VIL,
IOUT=0 mA
—
—
0.5
—
1
mA
µA
ISB1r
PSRAM Vcc Standby
Current
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
CE2r ≥ VCCr -0.2V,
70
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2V
IOUT=0 mA
ISB2r
PSRAM Vcc Standby
Current(6)
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
CE2r ≥ VCCr -0.2V,
—
—
5
mA
VIN Cycle time = tRC min, IOUT = 0 mA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
19
08/01/02
®
75V16F64GS16
ISSI
DC CHARACTERISTICS (Continued)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
IPDr
PSRAM VCC Power
Down Current
VCCr = VCCr max.,
VIN ≥ VCCf - 0.2 V OR VIN ≤ 0.2 V
CE2r ≤ 0.2 V, IOUT = 0 mA
—
10
µA
VIL
VIH
VIH
VID
Input Low Level
-0.3
2.0
0.5
V
Input High Level (Flash)
VCCf + 0.3
VCCr + 0.3
12.5
V
V
V
Input High Level (PSRAM)
2.2
Voltage for Autoselect
and Sector Protection
(RESET)(4)
11.5
VACC
Voltage for WP/ACC
8.5
9.5
V
Sector Protection/Unprotection
(4)
and Program Acceleration
VOL
VOH
VOL
VOH
VLKO
Output Low Level
(PSRAM)
VCCr = VCCr min., VCCS=VCCS min.
IOL = 1.0 mA
—
2.2
0.4
—
V
V
V
V
V
Output High Level
(PSRAM)
VCCr = VCCr min., VCCS=VCCS min.
IOH = -0.5 mA
Output Low Level
(Flash)
VCCf = VCCf min., VCCS=VCCS min.
IOL = 4.0 mA
—
0.45
—
Output High Level
(Flash)
VCCf = VCCf min., VCCS=VCCS min.
IOH = -0.1 mA
VCCf - 0.4
2.3
Flash Low Vccf
2.5
Lock-Out Voltage
Notes:
1. ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
4. Applicable for only VCCf applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.
.
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
AC CHARACTERISTICS - CE TIMING
Parameter
Symbol
Condition
Min Max
Unit
ns
CEf Recover Time
CEf Hold Time
t
CCR
CHOLD
CHWX
—
—
—
0
3
—
—
—
t
ns
CE1r High to WE Invalid time for
t
20
ns
Standby Entry
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH
CEf
tCCR
tCCR
CE1r
WE
t
CHOLD
t
CHWX
CCR
t
CCR
t
CE2r
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
21
08/01/02
®
75V16F64GS16
ISSI
FLASH READ ONLY OPERATIONS CHARACTERISTICS
JEDEC
Symbol
Standard
Symbol
Parameter
Condition
Min Max
Unit
ns
Read Cycle Time
t
AVAV
AVQV
ELQV
tRC
70
—
—
—
—
—
0
—
70
70
30
25
25
—
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
t
tACC
CEf = VIL, OE = VIL
OE = VIL
ns
t
t
CE
OE
ns
t
t
GLQV
t
ns
EHQZ
t
t
DF
DF
ns
t
GHQZ
ns
Output Hold Time From Addresses,
tAXQX
tOH
ns
CEf or OE, Whichever Occures First
RESET Pin Low to Read Mode
—
t
READY
—
20
µs
Test Conditions:
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCf
Timing measurement reference level
Input : VCCf/2
Output : VCCf/2
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH READ CYCLE
tRC
Address Stable
Address
tACC
CEf
t
DF
t
OE
OE
tOEH
WE
tCE
High-Z
High-Z
DQ
Output valid
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
23
08/01/02
®
75V16F64GS16
ISSI
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM
tRC
Address Stable
Address
t
ACC
CEf
tRH
tRH
t
CE
t
RP
RESET
t
OH
High-Z
DQ
Output valid
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
WRITE/ERASE/PROGRAM OPERATIONS
JEDEC
Symbol
Standard
Symbol
Parameter
Min
70
0
Typ
—
—
—
Max
—
Unit
ns
Write Cycle Time
Address Setup Time
t
AVAV
t
WC
AS
ASO
t
AVWL
t
—
ns
Address Setup Time to OE Low
During Toggle Bit Polling
—
t
12
—
ns
Address Hold Time
t
WLAX
t
AH
45
0
—
—
—
—
ns
ns
Address Hold Time from CE or
OE High During Toggle Bit Polling
—
t
AHT
Data Setup Time
t
t
DVWH
WHDX
—
t
DS
30
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Data Hold Time
t
DH
Output Enable Hold Time Read
t
t
OEH
OEH
0
Output Enable Hold Time
Toggle and Data Polling
—
10
CE High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write (OE to CE)
Read Recover Time Before Write (OE to WE)
WE Setup Time (CEf to WE)
CE Setup Time (WE to CE)
WE Hold Time (CE to WE)
CE Hold Time (WE to CE)
Write Pulse Width
—
—
t
CEPH
OEPH
GHWL
GHEL
WS
CS
WH
CH
WPH
CP
WPH
CPH
20
20
0
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
t
t
GHWL
t
t
GHEL
ELWL
WLEL
t
0
t
t
0
t
t
0
t
t
WHEH
EHWH
t
0
t
0
t
WLWH
t
35
35
25
25
—
—
50
500
500
4
CEf Pulse Width
t
ELEH
t
Write Pulse Width High
t
WHWL
t
CE Pulse Width High
t
EHEL
t
Programming Operation
t
t
WHWH
WHWH
—
1
t
t
WHWH
1
2
Sector Erase Operation (1)
2
WHWH
0.2
—
—
—
—
—
VCC Setup Time
t
VCS
VIDR
VACCR
VLHT
WPP
µs
ns
ns
µs
µs
(2)
(3)
Rise Time to VID
—
t
Rise Time to VID
—
t
Voltage Transition Time (2)
Write Pulse width (2)
—
t
—
t
100
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
25
08/01/02
®
75V16F64GS16
ISSI
WRITE/ERASE/PROGRAM OPERATIONS (Continued)
JEDEC
Standard
Symbol
Parameter
Symbol
—
Min
4
Typ
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
90
Unit
µs
µs
ns
ns
ns
ns
ns
µs
µs
OE Setup Time to WE Active (2)
CE Setup Time to WE Active (2)
Recover Time from RY/BY
t
OESP
—
t
CSP
4
—
t
RB
RP
0
RESET Pulse Width
—
t
500
200
—
—
50
—
RESET High Level Period Before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-Out Time
—
t
RH
BUSY
EOE
TOW
SPD
—
t
—
t
70
—
t
—
20
Erase Suspend Transition Time
—
t
Notes:
1. Does not include preprogramming time.
2. For Sector Group Protection operation.
3. For Accelerated Program operation.
26
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH WRITE CYCLE
(WE CONTROL)
Data Polling
3rd Bus Cycle
555h
PA
PA
Address
t
RC
t
AS
t
AH
tWC
CEf
t
CH
tCE
t
CS
OE
tWP
tWPH
t
WHWH1
tGHWL
t
OE
WE
t
DF
tDS
t
OH
t
DH
A0h
PD
DQ
7
Dout
Dout
DQ
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
27
08/01/02
®
75V16F64GS16
ISSI
FLASH WRITE CYCLE
(CEf CONTROL)
Data Polling
3rd Bus Cycle
555h
PA
PA
Address
tAS
tAH
tWC
WE
OE
t
WS
t
WH
t
CPH
tCP
tWHWH1
t
GHEL
CEf
tDS
tDH
AOh
PD
DQ7
Dout
DQ
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
555h
2AAh
555h
555h
2AAh
SA(1)
Address
tAH
t
AS
tWC
CEf
OE
WE
t
CH
t
SC
t
WP
t
WPH
t
GHWL
t
DS
tDH
30h for Sector Erase
10h/
30h
AAh
AAh
80h
55h
55h
DQ
tVCS
Vccf
Notes:
1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
29
08/01/02
®
75V16F64GS16
ISSI
FLASH AC WAVEFORMS
FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
CEf
t
DF
t
CH
t
OE
OE
t
OEH
WE
t
CE
(1)
High - Z
High - Z
DQ
7 =
Data In
Data In
DQ
7
Valid Data
DQ
tWHWH1 or 2
DQ0 to DQ6
Valid Data
DQ
0
to DQ
6
= Output Flag
DQ
0/DQ6
t
BUSY
t
EOE
RY/BY
Notes:
1. DQ7 = Valid Data (the device has completed the Embedded operation.)
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH AC WAVEFORMS
FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS
ADDRESS
tASO
t
AHT
t
AHT
t
AS
t
CEPH
CEf
WE
OE
tOEH
t
OEPH
t
OEH
(1)
tOE
tDH
tCE
Toggle
Data
Toggle
Data
Toggle
Data
Toggle
Data
Output
Valid
Data
DQ
6/DQ2
t
BUSY
RY/BY
Notes:
1. DQ6 stops toggling (the device has completed the Embedded operation).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
31
08/01/02
®
75V16F64GS16
ISSI
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM
Read
Command
Read
Command
Read
t
Read
t
RC
t
WC
t
RC
tWC
t
RC
RC
BA2
(555h)
BA2
(PA)
BA2
(PA)
BA1
BA1
BA1
ADDRESS
t
ACC
t
AS
t
AH
tAS
tCE
tAHT
CEf
t
CEPH
t
OE
OE
tDF
tGHWL
tOEH
t
WP
WE
tDS
t
DF
tDH
Valid
Output
Valid
Input
Valid
Output
Valid
Input
Valid
Output
DQ
Status
(A0h)
(PD)
Note:
1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1;
BA2: Address of Bank 2.
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
FLASH RY/BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS
CEf
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
FLASH RESET, RY/BY TIMING DIAGRAM
WE
RESET
t
RB
tRP
RY/BY
tREADY
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
33
08/01/02
®
75V16F64GS16
ISSI
FLASH EXTENDED SECTOR GROUP PROTECTION
t
VCS
Vccf
t
VLHT
t
WC
t
WC
RESET
Address
t
VIDR
SPAX
SPAX
SPAY
A
6
, A
3
0
A
2
, A
A1
CEf
OE
t
WP
TIME-OUT
WE
60h
Data
60h
40h
01h
60h
t
OE
Notes:
1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected,
TIME-OUT: Time-Out window = 250 µs (Min)
34
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM READ OPERATIONS
Value
Parameter
Symbol
Min.
Max.
Unit
Read Cycle Time
t
RC
CE
OE
AA
OH
90
—
—
—
5
—
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Access Time(1,3)
Output Enable Access Time(1)
Chip Enable Access Time(1,4)
Output Data Hold Time(1)
CE1r Low to Output Low-Z(2)
OE Low to Output Low-Z(2)
CE1r High to Output High-Z(2)
OE High to Output High-Z(2)
Address Setup Time to CE1r Low(5)
Address Setup Time to OE(3,6)
Address Setup Time to OE(7)
Address Invalid Time(4)
CE1r Low to Address Hold Time(4)
OE Low to Address Hold Time(4,8)
CE1r High to Address Hold Time
OE High to Address Hold Time
CE1r Low to OE Low DelayTime(4,6,8,9)
OE Low to CE1r High DelayTime(8)
CE1r High Pulse Width
t
t
45
t
80
t
—
—
—
30
t
CLZ
OLZ
5
t
0
t
CHZ
—
—
-5
tOHZ
25
t
ASC
ASO
—
—
—
5
t
45
10
—
90
45
-5
t
ASO
(
ABS
)
t
AX
t
CLAH
OLAH
—
—
—
—
1000
—
—
1000
—
t
t
CHAH
t
OHAH
-5
t
CLOL
45
45
20
45
20
t
OLCH
t
CP
OP
ABS
OE High Pulse Width(6,8,9)
OE High Pulse Width(7)
t
t
OP
(
)
Notes:
1. The output load is 30 pF.
2. The output load is 5 pF.
3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access.
5. Applicable if OE is brought to Low before CE1r goes Low.
6. The tASO, tCLOL (Min) and top (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) .
7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
- tCLOL (actual) or tRC (Min) - tOP (actual) .
9. Maximum value is applicable if CE1r is kept at Low.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
35
08/01/02
®
75V16F64GS16
ISSI
PSRAM WRTE OPERATIONS
Value
Parameter
Symbol
Min.
Max.
Unit
Write Cycle Time(1)
t
WC
90
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time(2)
Address Setup Timev
CE1r Write Setup Time
CE1r Write Hold Time
WE Setup Time
t
AS
AH
CS
t
45
0
—
t
1000
1000
—
t
CH
0
t
WS
WH
0
WE Hold Time
t
0
—
LB adnd UB Setup Time
LB adnd UB Hold Time
OE Setup Time(3)
t
BS
0
—
t
BH
-5
0
—
t
OES
OEH
OEH ABS
OHCL
OHAH
1000
1000
—
OE Hold Time(3,4)
t
45
20
-3
-5
60
60
15
15
20
0
OE Hold Time(5)
t
(
)
OE High to CE1r Low Setup Time(6)
OE High to Address Hold Time(7)
CE1r Write Pulse Width(1,8)
WE Write Pulse Width(1,8)
CE1r Write Recovery Time(1,9)
WE Write Recovery Time(1,3,9)
Data Setup Time
t
—
t
—
t
CW
WP
—
t
—
t
WRC
WR
—
t
1000
—
t
DS
DH
CD
Data Hold Time
t
—
CE1r High Pulse Width(9)
t
20
—
Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
2. New write address is valid from either CE1r or WE that is brought to High.
3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High.
4. The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low.
6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
7. Applicable if CE1r stays Low after read operation.
8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively.
9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively.
The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
36
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM POWER DOWN PARAMETER
Value
Parameter
Symbol
Min.
Max.
Unit
CE2r Low Setup Time for Power down Entry
t
CSP
LP
CHH
CHS
10
100
350
10
—
—
—
—
ns
ns
µs
ns
CE2r Low Setup Time after Power down Entry
tC
2
CE1r High Hold Time Following CE2r High after Power down Exit
CE1r High Setup Time Following CE2r High after Power down Exit
t
t
PSRAM OTHER TIMING PARAMETERS
Value
Parameter
Symbol
Min.
Max.
Unit
CE1r High to OE Invalid for Standby Entry
CE1r High to WE Invalid for Standby Entry(1)
CE2r Low Hold Time after Power-up(2)
t
CHOX
20
20
50
50
350
1
—
—
—
—
—
25
ns
ns
µs
µs
µs
ns
t
t
t
CHWX
C
2
LH
HL
CE2r High Hold Time after Power-up(3)
CE1r High Hold Time Following CE2r High after Power-up(2)
Input Transition Time(4)
C2
t
CHH
t
T
Notes:
1. Unintended data may be written into any address location if tCHWX is not satisfied.
2. Must satisfy tCHH (Min) after tC2LH (Min) .
3. Requires Power Down mode entry and exit after tC2HL.
4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns,
it may violate some timing parameters of AC specification.
PSRAM AC TEST CONDITIONS
Parameter
Symbol
Conditon
Value
Unit
Input HIgh Level
V
IH
IL
REF
VCCr = 2.7V to 3.1V
VCCr = 2.7V to 3.1V
VCCr = 2.7V to 3.1V
Between VIL and VIH
2.3
0.4
1.3
5
V
V
Input Low Level
V
Input Timing Measurement Level
Input Transition Time
V
V
t
T
ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
37
08/01/02
®
75V16F64GS16
ISSI
PSRAM READ TIMING
(OE Control Access)
tRC
tRC
Address
Address Valid
tCE
Address Valid
tASO
tOHAH
tOHAH
CE1r
tOLCH
tOE
tCLOL
tOP
tOE
OE
tOHZ
tOH
tASO
tOHZ
tOH
tOLZ
DQ
(Input)
tOLZ
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
PSRAM READ TIMING
(CE1r Control Access)
tRC
tRC
Address
Address Valid
tCE
Address Valid
tCE
tASC
tASC
tcHAH
tCHZ
tOHAH
CE1r
tCP
tCHZ
OE
tOH
tCLZ
tCLZ
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
38
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM READ TIMING
(Address Access after OE Control Access)
tRC
tRC
Address
(A19-A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tOLAH
Address Valid
tAA
tASO
tOHAH
tAX
CE1r
tOE
tOHZ
OE
tOH
tOLZ
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
PSRAM READ TIMING
(Address Access after CE1r Control Access)
tRC
tRC
Address
(A19-A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
tCLAH
Address Valid
tAA
tASC
tCHAH
tCHZ
tAX
CE1r
tCE
OE
tOH
tCLZ
tOH
DQ
(Input)
Valid Data Input
Valid Data Input
Note: CE2r and WE must be High during read cycle.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
39
08/01/02
®
75V16F64GS16
ISSI
PSRAM WRITE TIMING
(CE1r Control)
tWC
Address
Address Valid
tAH
tAS
tAS
tWS
tBS
tWRC
CE1r
tCW
tWH
tBH
tWS
WE
tBS
UB, LB
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r must be High during write cycle.
PSRAM WRITE TIMING
(WE Control, Single Write Operation)
tWC
Address
Address Valid
tAH
tAS
tCP
tOHAH
tAS
tCH
CE1r
tWP
tOHCL tCS
tWR
WE
tBS
tBH
UB, LB
tOES
tOHz
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r must be High during write cycle.
40
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM WRITE TIMING
(WE Control, Continuous Write Operation)
tWC
Address
Address Valid
tAH
tAS
tOHAH
tAS
CE1r
tWP
tOHCL tCS
tWR
WE
tBS
tBS
tBH
UB, LB
tOES
tOHz
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(CE1r Control)
tWC
Address
Read Address
Write Address
tAH
tCHAH
tASC
tAS
CE1r
tCP
tWRC
tWH
tWS
tCW
tWH
tWS
WE
tBS
tBH
UB, LB
tCLOL
tOLz
tOHCL
OE
tCHZ
tOLz
tOH
tDS
tDH
DQ
(Input)
Read Data Output
Valid Data Input
Note: Write address is valid from either CE1r or WE of last falling edge.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
41
08/01/02
®
75V16F64GS16
ISSI
PSRAM READ / WRITE TIMING
(CE1r Control)
tRC
Address
Write Address
Read Address
tAS
tASC
tWRC
tCHAH
tWH
CE1r
tWRC (Min)
tCP
tWH
tWS
tBS
tWS
WE
tBH
tCE
UB, LB
tOEH
tOHCL
OE
tCHZ
tOH
tCLz
tOH
DQ
Read Data Output
Write Data Input
Note: CE2r must be High during write cycle.
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
tWC
Address
Read Address
Write Address
tAH
tASO
tAS
tOHAH
CE1r
Low
tWR
tBH
tWP
WE
tBS
UB, LB
tOEH
tOES
OE
tOHZ
tOH
tDS
tDH
tOLz
DQ
Read Data Output
Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled by OE.
42
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM READ / WRITE TIMING
(READ = OE Control, WRITE = WE Control)
tRC
Address
Read Address
Write Address
tASO
tOHAH
tAS
Low
CE1r
tWR
WE
tBH
tBS
UB, LB
tOEH
tOE
tOES
OE
tOHZ
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output
is exclusively controlled OE.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
43
08/01/02
®
75V16F64GS16
ISSI
PSRAM POWER DOWN TIMING
CE1r
tCHS
CE2r
tCHH
tCSP
tC2LP
High - Z
DQ
Power Down Mode
Power Down Entry
Power Down Exit
PSRAM STANDBY ENTRY TIMING AFTER READ WRITE
CE1r
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satis-
fied, it takes tRC (min) period from either last address transition of A0 and A1, or CE1r Low to High transition.
44
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM POWER UP TIMING 1
CE1r
tCHS
tCHH
tC2LH
CE2r
Vccr Min
Vccr
0V
Note: It is recommended CE2r to be kept at Low during Vccr power-up. The tC2LH specifies after Vccr reaches
specified minimum level.
PSRAM POWER UP TIMING 2
CE1r
tCSP
tCHS
tC2HL
tC2LP
tCHH
CE2r
Vccr
tC2HL
Vccr Min
0 V
Note: The tC2LH specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must
be brought to High prior to or together with CE2r Low to High transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
45
08/01/02
®
75V16F64GS16
ISSI
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Max.
Typ.(1)
Unit
Remarks
Sector Erase Time
—
0.2
1.0
s
Excludes programming time
prior to erasure
Word Programming Time
Chip Programming Time
Erase/Program Cycle
—
—
6.0
—
60
200
—
µs
s
Excludes system-level
overhead
Excludes system-level
overhead
100,00
—
cycle
Note:
1. Test conditions TA = +25 °C, VCC = 2.9V, Data = Checker
46
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min. Max.
Unit
VDR
Vccr Data Retention Supply Voltage
CE1r = CE2r ≥ VCCr -0.2V OR,
CE1r = CE2r = VIH
2.1
3.1
V
IDR
Vccr Data Retention Supply Current
Vccr Data Retention Supply Current
2.3 V ≤ VCCr ≤ 2.7 V,≥
—
1
mA
VIN = VIH (1) or VIL
(1)
CE1r = CE2r = VIH
,
IOUT = 0 MA
IDR1
2.3 V ≤VCCr ≤ 2.7 V,≥
VIN ≤ 0.2 V or VIN ≥ VCCr -2.0 V,
CE1r = CE2r ≥ VCCr -0.2 V
IOUT = 0 MA
—
70
µA
tDRS
Data Retention SetupTime
Data Retention RecoveryTime
VCCR Voltage Transition Time
2.7 V ≤ VCCr ≤ 3.1 V,≥
At Data Retention Entry
0
—
—
—
ns
ns
tDRR
2.7 V ≤ VCCr ≤ 3.1 V,≥
After Data Retention
90
0.5
∆V/∆t
—
V/µs
Note:
1. 2.0 V ≤ VIN ≤ VCCr + 0.3
PSRAM DATA RETENTION TIMING
t
DRS
t
DRR
3.1V
2.7V
∆V/∆t
∆V/∆t
Vccr
2.3V
CE2r
CE1r = CE2r >Vccr - 0.2V or
CE1r
V
IH(1) Min
4.0V
GND
Data Retention Mode
Data bus must be in High-Z at data retention entry
Note:
1. 2.0 V ≤ VIH ≤ VCCr + 0.3 V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
47
08/01/02
®
75V16F64GS16
ISSI
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
VIN = 0 V
VOUT = 0 V
VIN = 0 V
VIN = 0 V
Min. Max.
Unit
C
C
C
C
IN
Input Capacitance
Output Capacitance
Control Pin Capacitance
WP/ACC Pin Capacitance
11
12
14
14
16
16
pF
pF
pF
pF
OUT
IN
2
3
IN
21.5 26
Notes:
1. Test conditions T
A
= +25 °C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully since the sides of package created with acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when
autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET.
2) Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
ISB2r VS VIN Cycle Time
I
SB2r vs. VIN Cycle Time (VCCr = 3.0 V)
2.5
2.0
1.5
1.0
: RT = 25 °C
: LT = -30 °C
: HT = 85 °C
0.5
0.0
1000
0
400
600
800
200
VIN Cycle Time(ns)
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
®
75V16F64GS16
ISSI
BALL GRID ARRAY – 65-Ball FBGA
PACKAGE CODE: D
- 9.0 mm x 9.0 mm Body, 0.8 mm Ball Pitch
ø 0.45 + 0.10/−0.05 (65X)
A B C D E F G H J K
K J H G F E D C B A
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
e
D
D1
e
E1
E
A1
A
SEATING PLANE
Symbol
Min.
1.09
0.29
8.90
—
Typ.
1.19
0.39
9.00
7.20
9.00
7.20
0.80
Max.
1.34
0.49
9.10
—
Units
mm
mm
mm
mm
mm
mm
mm
A
A1
D
D1
E
8.90
—
9.10
—
E1
e
—
—
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
49
08/01/02
®
75V16F64GS16
ISSI
ORDERING INFORMATION
Industrial Range: -30ºC to +85ºC
SRAM
Data
Bus Section
Boot
Flash Bank
Flash
PSRAM
Order Part No.
Organization Speed(ns) Speed(ns) Package
IS75V16F64GS16-7080DI
16
PC
PC
70
80
65-ball FBGA
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
08/01/02
相关型号：
IS75V16F64GS32-7070DI
Memory Circuit, Flash+SRAM, 4MX16, CMOS, PBGA65, 9 X 9 MM, 0.80 MM PITCH, FBGA-65
ISSI
©2020 ICPDF网 联系我们和版权申明