N16D1633LPAT2-60I [ISSI]
Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, GREEN, TSOP2-50;
| 型号： | N16D1633LPAT2-60I |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, GREEN, TSOP2-50 动态存储器 光电二极管 |
| 文件： | 总29页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N16D1633LPA
512K x 16Bits x 2Banks Low Power Synchronous DRAM
Description
These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These
products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.0V/3.3V power supply.
• Auto refresh and self refresh.
• All inputs and outputs referenced to the positive edge of the
system clock.
• All pins are compatible with LVCMOS interface.
• 4K refresh cycle / 64ms.
• Data mask function by DQM.
• Internal dual banks operation.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode.
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Table1: Ordering Information
Part No.
Clock Freq.
166 MHz
133 MHz
100 MHz
166 MHz
133 MHz
100 MHz
Temperature
VDD/VDDQ
Interface
Package
N16D1633LPAC2-60I
N16D1633LPAC2-75I
N16D1633LPAC2-10I
N16D1633LPAT2-60I
N16D1633LPAT2-75I
N16D1633LPAT2-10I
60-Ball Green
FBGA
3.0V/3.0V
or
3.3V/3.3V
-25°C to 85°C
LVCMOS
50-Pin Green
TSOPII
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Figure1: 60Ball FBGA Ball Assignment
1
2
3
4
5
6
7
VSS
DQ15
DQ0
VDD
A
DQ14
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
B
DQ13
C
DQ12
D
DQ10
E
DQ9
F
DQ8
G
NC
NC
NC
NC
H
J
UDQM
CLK
NC
LDQM
/RAS
NC
/WE
/CAS
/CS
K
L
NC
CKE
A11
A8
M
N
P
R
A9
NC
NC
A7
A0
A10
A1
A6
A5
A2
VSS
A4
A3
VDD
[Top View]
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Figure2: 50Pin TSOPII Pin Assignment
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
2
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 Pin
TSOP II
UDQM
CLK
CKE
N.C
BA
A9
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
[Top View]
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Table2: Pin Descriptions
Pin
Pin Name
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CLK
System Clock
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
CKE
Clock Enable
Chip Select
/CS
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
A11
Bank Address
Address
Row Address
: RA0~RA10
: CA0~CA7
: A10
A0~A10
Column Address
Auto Precharge
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
/RAS, /CAS, /WE
LDQM/UDQM
Controls output buffers in read mode and masks input data in
write mode.
Data Input/Output Mask
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output
Multiplexed data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
Power Supply/Ground
Data Output Power/Ground
No Connection
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Figure3: Functional Block Diagram
EXTENDED
MODE
REGISTER
CLK
CKE
CLOCK
GENERATOR
TCSR
PASR
ADDRESS
BANK B
ROW
BANK A
ADDRESS
BUFFER &
REFRESH
COUNTER
MODE
REGISTER
SENSE AMPLIFIER
COLUMN DECODER
/CS
/RAS
/CAS
/WE
&
LATCH CIRCUIT
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
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Figure4: Simplified State Diagram
EXTENDED
MODE
SELF
REGISTER
SET
REFRESH
MRS
MODE
REGISTER
SET
CBR
REF
IDLE
REFRESH
DEEP
POWER
DOWN
POWER
DOWN
CKE ↓
ACTIVE
POWER
DOWN
ROW
CKE
ACTIVE
READ
WRITE
CKE ↓
CKE ↓
READ
WRITE
WRITE
SUSPEND
CKE
READ
READ
SUSPEND
WRITE
CKE
CKE ↓
CKE ↓
WRITE A
WRITE A
SUSPEND
CKE
READ A
READ A
SUSPEND
CKE
PRECHARGE
POWER
ON
PRE-
CHARGE
Automatic Sequence
Manual Input
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Figure5: Mode Register Definition
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0
WB
CAS Latency
BT
Burst Length
0
0
0
M9
0
Write Burst Mode
M6 M5 M4 CAS Latency
M3 Burst Type
Burst Length
M3 = 0 M3 = 1
M2 M1 M0
Burst Read and Burst Write
Burst Read and Single Write
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
0
1
Sequential
Interleave
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
2
3
4
4
Reserved
Reserved
Reserved
Reserved
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Note: M11(A11) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table3.
Table 3: Burst Definition
Starting Column Order of Access Within a Burst
Burst
Length
Address
Note :
Sequential
Interleaved
A2
A1 A0
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column within the
block.
0
1
0-1
1-0
0-1
1-0
2
0
0
1
1
0
1
0
1
0-1-2-3
0-1-2-3
3. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column within
the block.
1-2-3-0
2-3-0-1
3-0-1-2
1-0-3-2
2-3-0-1
4
3-2-1-0
4. For
a burst length of eight, A3-A7 select the
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn, Cn+1. Cn+2,
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
8
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Full
n=A0-7
Cn+3, Cn+4…
…Cn-1, Cn...
Not Supported
Page
(Location 0-256)
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Figure6: Extended Mode Register
A11
A10
A9
A8
A7
A6
DS
A5
A4
A3
A2
A1
A0
Address Bus
11
10
9
8
7
6
5
4
3
2
1
0
Extended Mode Register (Ex)
0
1
0
0
0
TCSR
PASR
E6
0
E5
0
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
Reserved
Maximum Case
Temp.
E4
E3
0
0
1
1
0
1
0
1
85°
70°
0
1
1
0
45°
1
1
Auto
E2
0
E1
0
E0
Self Refresh Coverage
0
1
0
1
0
1
0
1
All Banks
0
0
One Bank (A11=0)
0
1
Reserved
0
1
Reserved
1
0
Reserved
1
0
Half of One Bank (A11=0, Row Address MSB=0)
Quarter of One Bank (A11=0, Row Address 2 MSB=0)
Reserved
1
1
1
1
Note: E11(A11) must be set to “1” to select Extend Mode Register (vs. the base Mode Register)
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Functional Description
In general, this 16Mb SDRAM (512K x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 8,388,608-bit banks is organized as
2,048 rows by 256 columns by 16-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (A11 select the bank, A0-A10 select the row). The address bits (A11 select the bank, A0-A7 select the column)
registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying any operational command. And a extended mode register set command will be issued to program specific mode of self
refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set
to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self
Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command (A11=1) and retains the stored information until it is
programmed again or the device loses power.
The Extended Mode Register must be programmed with M7 through M10 set to “0”. The Extended Mode Register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation.
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Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when
the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and
deasserting CAS, WE at the positive edge of the clock. The value on the A11 selects the bank, and the value on the A0-A10 selects the row.
This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be
initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at
the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of
the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS
latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at
the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of
the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
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CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m
clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m -
1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Figure7: CAS Latency
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
NOP
tOH
Dout
tLZ
DQ
tAC
CAS Latency=2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
tOH
tLZ
DQ
Dout
tAC
CAS Latency=3
DON’T CARE
UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
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Table4: Command Truth Table
Function
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
Addr
A10
Note
Command Inhinit (NOP)
No Operation (NOP)
Mode Register Set
H
H
H
H
X
X
X
X
H
L
L
L
X
H
L
X
H
L
X
H
L
X
X
X
X
X
X
OP CODE
OP CODE
4
4
Extended Mode Register Set
L
L
L
Active (select bank and
activate row)
H
X
L
L
H
H
X
Bank/Row
Read
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
H
H
L
L/H
L/H
L/H
L/H
X
Bank/Col
L
H
L
5
5
5
5
Read with Autoprecharge
Write
Bank/Col
Bank/Col
Bank/Col
X
L
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
L
L
H
H
L
H
H
H
L
L
L
L
X
Bank
H
L
L
X
X
Auto Refresh
H
H
X
H
X
H
X
H
X
V
X
X
X
3
3
Self Refresh Entry
L
L
X
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
Self Refresh Exit
L
H
L
H
L
X
X
X
X
X
X
X
X
2
Precharge Power Down Entry
Precharge Down Exit
Clock Suspend Entry
H
L
H
Clock Suspend Exit
L
H
L
H
L
X
X
X
X
X
X
X
Deep Power Down Entry
Deep Power Down Exit
L
H
H
L
6
H
X
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A10 define OP CODE written to the mode register, and A11 must be issued 0 in the mode register set, and 1 in the extended
mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
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Table5: Function Truth Table
Command
A11
Current
State
Action
Note
/CS
/RAS
/CAS
/WE
A0-A10
Description
L
L
L
L
OP CODE
Mode Register Set
Set the Mode Register
14
5
Start Auto or Self
Refresh
L
L
L
L
L
L
L
H
H
H
L
X
X
X
Auto or Self Refresh
Precharge
BA
BA
No Operation
Activate the Specified
Bank and Row
H
Row Add.
Bank Activate
Idle
L
L
L
H
H
H
L
L
L
H
H
BA
BA
X
Col Add./ A10
Col Add./ A10
X
Write/WriteAP
Read/ReadAP
No Operation
ILLEGAL
4
4
3
ILLEGAL
H
No Operation
No Operation or Power
Down
H
X
X
X
X
X
Device Deselect
3
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
13,14
X
X
X
13
7
H
H
BA
BA
H
Row Add.
Bank Activate
4
Row
Active
Start Write : Optional
AP(A10=H)
L
L
H
H
L
L
L
BA
BA
Col Add./A10
Col Add./A10
Write/Write AP
Read/Read AP
6
6
Start Read : Optional
AP(A10=H)
H
L
H
L
H
X
L
H
X
L
H
X
L
X
X
X
X
No Operation
No Operation
No Operation
ILLEGAL
Device Deselect
Mode Register Set
Auto or Self Refresh
OP CODE
13,14
13
L
L
L
H
X
X
X
ILLEGAL
Termination Burst :
Start the Precharge
L
L
L
L
L
H
H
L
L
H
L
BA
BA
BA
Precharge
Row Add.
Col Add./A10
Bank Activate
Write/WriteAP
ILLEGAL
4
Read
Termination Burst :
Start Write(AP)
H
8,9
Terimination Burst :
Start Read(AP)
L
H
L
H
BA
Col Add./A10
Read/Read AP
8
L
H
X
H
X
H
X
X
X
X
X
No Operation
Continue the Burst
Continue the Burst
H
Device Deselect
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Table5: Function Truth Table
Command
A11
Current
State
Action
Note
/CS
/RAS
/CAS
/WE
A0-A10
Description
L
L
L
L
L
L
L
OP CODE
Mode Register Set
Auto or Self Refresh
ILLEGAL
ILLEGAL
13,14
13
H
X
X
X
Termination Burst :
Start the Precharge
L
L
L
L
L
H
H
L
L
H
L
BA
BA
BA
Precharge
10
4
Row Add.
Col Add./A10
Bank Activate
Write/WriteAP
ILLEGAL
Write
Termination Burst :
Start Write(AP)
H
8
Terimination Burst :
Start READ(AP)
L
H
L
H
BA
Col Add./A10
Read/ReadAP
8,9
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
X
L
H
X
L
H
X
L
X
X
X
X
No Operation
Continue the Burst
Continue the Burst
ILLEGAL
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
OP CODE
13,14
13
L
L
H
L
X
BA
BA
BA
BA
X
X
ILLEGAL
L
H
H
L
X
Row Add.
Col Add./A10
Col Add./A10
X
ILLEGAL
4,12
4,12
12
Read
with
Auto
L
H
L
Bank Activate
Write/WriteAP
Read/ReadAP
No Operation
ILLEGAL
H
H
H
X
L
ILLEGAL
Precharge
L
H
H
X
L
ILLEGAL
12
H
X
L
Continue the Burst
Continue the Burst
ILLEGAL
X
X
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
OP CODE
13,14
13
L
L
H
L
X
BA
BA
BA
BA
X
X
ILLEGAL
L
H
H
L
X
Row Add.
Col Add./A10
Col Add./A10
X
ILLEGAL
4,12
4,12
12
Write
with
Auto
L
H
L
Bank Activate
Write/WriteAP
Read/ReadAP
No Operation
ILLEGAL
H
H
H
X
ILLEGAL
Precharge
L
H
H
X
ILLEGAL
12
H
X
Continue the Burst
Continue the Burst
X
X
Device Deselect
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Table5: Function Truth Table
Command
A11
Current
State
Action
Note
/CS
/RAS
/CAS
/WE
A0-A10
Description
L
L
L
L
L
L
L
OP CODE
Mode Register Set
Auto or Self Refresh
ILLEGAL
ILLEGAL
13,14
13
H
X
X
X
No Operation :
Bank(s) Idle after tRP
L
L
H
L
BA
Precharge
L
L
L
L
H
H
H
L
H
L
BA
BA
BA
Row Add.
Bank Activate
Write/WriteAP
Read/ReadAP
ILLEGAL
ILLEGAL
ILLEGAL
4,12
4,12
4,12
Precharging
Col Add./ A10
Col Add./ A10
L
H
No Operation :
Bank(s) Idle after tRP
L
H
X
H
X
H
X
X
X
X
X
No Operation
No Operation :
Bank(s) Idle after tRP
H
Device Deselect
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
X
L
H
H
L
BA
BA
BA
BA
X
4,12
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
4,11,12
4,12
Row
Activating
H
H
Write/Write AP
Read/Read AP
L
H
4,12
No Operation : ROw
Active after tRCD
L
H
X
H
X
H
X
X
X
X
X
No Operation
No Operation : ROw
Active after tRCD
H
Device Deselect
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
X
X
H
H
BA
BA
4,13
4,12
H
Row Add.
Bank Activate
Start Write : Optional
AP(A10=H)
L
L
H
H
H
X
L
L
L
H
H
X
BA
BA
X
Col Add./A10
Write/WriteAP
Read/Read AP
No Operation
Device Deselect
Write
Recovering
Start Write : Optional
AP(A10=H)
Col Add./A10
9
No Operation : Row
Active after tDPL
L
H
X
X
X
No Operation : Row
Active after tDPL
H
X
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Table5: Function Truth Table
Command
A11
Current
State
Action
Note
/CS
/RAS
/CAS
/WE
A0-A10
Description
Mode Register Set
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
X
L
H
H
L
BA
BA
BA
BA
X
4,13
4,12
4,12
4,9,12
Write
Recovering
with
Auto
Precharge
L
H
L
Row Add.
Col Add./ A10
Col Add./ A10
Bank Activate
H
H
Write/WriteAP
Read/ReadAP
L
H
No Operation :
Precharge after tDPL
L
H
X
H
X
H
X
X
X
X
X
No Operation
No Operation :
Precharge after tDPL
H
Device Deselect
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
X
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
L
H
H
L
BA
BA
BA
BA
X
13
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
13
H
H
Write/Write AP
Read/Read AP
13
Refreshing
L
H
13
No Operation : Idle
after tRC
L
H
X
H
X
H
X
X
X
X
X
No Operation
No Operation : Idle
after tRC
H
Device Deselect
L
L
L
L
L
L
L
L
L
L
L
H
L
OP CODE
X
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
13,14
13
X
L
H
H
L
BA
BA
BA
BA
X
13
L
H
L
Row Add.
Col Add./A10
Col Add./A10
Bank Activate
13
Mode
Register
Accessing
H
H
Write/WriteAP
Read/Read AP
13
L
H
13
No Operation : Idle
after 2 Clock Cycle
L
H
X
H
X
H
X
X
X
X
X
No Operation
No Operation : Idle
after 2 Clock Cycle
H
Device Deselect
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Note :
1. H: Logic High, L: Logic Low, X: Don't care, A11: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except A11.
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Table6: CKE Truth Table
CKE
Command
Current
State
Action
Note
Prev
Cycle
Current
Cycle
/CS
X
/RAS
/CAS
/WE
A11
X
A0-A10
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
2
Exit Self Refresh with
Device Deselect
H
H
X
3
3
Exit Self Refresh with No
Operation
L
H
L
H
H
H
X
Self
Refresh
L
L
H
H
H
L
L
L
H
H
L
H
L
L
X
X
X
X
X
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
3
3
3
ILLEGAL
L
L
X
X
X
X
H
X
L
ILLEGAL
L
X
X
H
L
X
X
X
H
L
Maintain Self Refresh
INVALID
H
X
2
3
Power Down Mode Exit, All
Banks Idle
L
L
H
H
Power
Down
ILLEGAL
L
X
X
X
X
X
3
X
X
X
X
L
H
L
L
X
H
X
X
X
X
X
X
Maintain Power Down Mode
INVALID
2
6
Deep
Power
Down
Deep Power Down Mode
Set
L
L
X
X
X
X
X
X
Maintain Deep Power Down
Mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
L
L
L
H
L
L
L
L
X
X
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State
section of the Current State
Truth Table
4
4
4
L
X
X
Auto Refresh
L
L
OP CODE
Mode Register Set
5
4
4
4
5
All
Banks
Idle
X
H
L
X
X
H
L
X
X
X
H
L
Refer to the Idle State
section of the Current State
Truth Table
L
L
L
L
X
X
Entry Self Refresh
Mode Register Set
Power Down
L
L
L
OP CODE
X
H
X
X
X
X
X
X
X
X
X
X
5
H
Refer to Operations of the
Current State Truth Table
Any
State
other
than
listed
above
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next
cycle
Exit Clock Suspend next
cycle
L
Maintain Clock Suspend
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Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes
high and is maintained for a minimum 100usec.
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Table7: Absolute Maximum Rating
Parameter
Ambient Temperature (Industrial)
Ambient Temperature (Commercial)
Storage Temperature
Symbol
Rating
-25 ~ 85
0 ~ 70
-55 ~ 150
-1.0 ~ 4.6
-1.0 ~ 4.6
50
Unit
TA
°C
TSTG
VIN, VOUT
VDD, VDDQ
IOS
°C
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
V
mA
W
PD
1
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8: Capacitance (TA=25 °C, f=1MHz, VDD=3.0V or 3.3V)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
Input Capacitance
A0~A11, CKE, /CS, /RAS, /CAS, /WE,
L(U)DQM
CI2
CIO
2
3
4
5
pF
pF
Data Input/Output Capacitance
DQ0~DQ15
Table9: DC Operating Condition (Voltage referenced to VSS=0V, TA= -25 ~ 85 °C)
Parameter
Power Supply Voltage
Input High Voltage
Symbol
VDD
Min
2.7
Typ
3.0
3.0
-
Max
3.6
Unit
Note
V
V
V
VDDQ
VIH
2.7
3.6
1
2
3
2.2
VDDQ+0.3
Input Low Voltage
VIL
VOH
VOL
ILI
-0.3
2.4
-
0
-
0.5
-
V
V
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
IOH= -0.1mA
-
0.4
1
V
IOL= +0.1mA
-1
-
uA
uA
4
5
ILO
-1.5
1.5
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns.
3. VIL(min) = -2.0V AC. The overshoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. DOUT is disabled, 0V ≤ VOUT ≤ VDDQ.
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Table10: AC Operating Condition (TA= -25 ~ 85 °C, VDD = 3.0V or 3.3V ± 0.3V, VSS=0V)
Parameter
Symbol
VIH / VIL
VTRIP
Typ
2.4 / 0.4
0.5 x VDDQ
1 / 1
Unit
V
AC Input High/Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
V
tR / tF
VOUTREF
CL
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
0.5 x VDDQ
30
pF
VDDQ
VTT=0.5 x VDDQ
1200Ω
50Ω
Output
Output
Z0=50Ω
870Ω
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
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Table11: DC Characteristic (DC operating conditions unless otherwise noted)
Speed
Parameter
Sym
Test Condition
Unit Note
-60 -75 -10
Burst Length=1, One Bank Active,
tRC ≥ tRC(min) IOL = 0 mA
Operating Current
ICC1
35
mA
uA
1
ICC2P
CKE ≤ VIL(max), tCK = 10ns
60
60
Precharge Standby Current
in Power Down Mode
ICC2PS
CKE & CLK ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
ICC2N
6
1
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
ICC2NS
ICC3P
CKE ≤ VIL(max), tCK = 10ns
1.0
0.5
Active Standby Current
in Power Down Mode
ICC3PS
CKE & CLK ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
ICC3N
12
6
Active Standby Current
in Non Power Down Mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
ICC3NS
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
Burst Mode Operating Current
Auto Refresh Current (4K Cycle)
ICC4
ICC5
55
45
30
35
mA
mA
1
2
tRC ≥ tRFC(min), All Banks Active
PASR
TCSR
45~85°C
-25~45°C
45~85°C
-25~45°C
70
55
65
50
10
Self
Refresh
Current
2 Banks
ICC6
ICC7
CKE ≤ 0.2V
uA
uA
1 Bank
Deep Power Down Mode Current
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
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Table12: AC Characteristic (AC operation conditions unless otherwise noted)
-60
-75
-10
Parameter
Sym
Unit
Note
Min
6.0
10
Max
Min
7.5
10
Max
Min
10
Max
CL = 3
CL = 2
tCK3
tCK2
CLK Cycle Time
1000
1000
1000
1
10
CL = 3
CL = 2
tAC3
5.5
8
6
8
8
8
Access time from CLK (pos. edge)
2
tAC2
tCH
CLK High-Level Width
CLK Low-Level Width
CKE Setup Time
2.5
2.5
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
2.5
2.5
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.5
2.5
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
3
3
tCL
tCKS
tCKH
tCMS
tCMH
tAS
CKE Hold Time
/CS, /RAS, /CAS, /WE, DQM Setup Time
/CS, /RAS, /CAS, /WE, DQM Hold Time
Address Setup Time
Address Hold Time
tAH
ns
Data-In Setup Time
tDS
Data-In Hold Time
tDH
CL = 3
CL = 2
tHZ3
tHZ2
tLZ
5.5
8
6
8
8
8
Data-Out High-Impedance Time
from CLK (pos.edge)
4
Data-Out Low-Impedance Time
Data-Out Hold Time (load)
1.0
2.5
1.8
42
1.0
2.5
1.0
2.5
1.8
40
tOH
Data-Out Hold Time (no load)
ACTIVE to PRECHARGE command
PRECHARGE command period
tOHN
tRAS
tRP
1.8
100K
45
100K
100K
18
22.5
67.5
15
20
ACTIVE bank a to ACTIVE bank a command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
tRC
60
64
5
6
tRRD
tRCD
12
20
18
22.5
20
READ/WRITE command to READ/WRITE
command
tCCD
1
1
1
CLK
ns
WRITE command to input data delay
Data-in to PRECHARGE command
Data-in to ACTIVE command
tDWD
tDPL
0
12
30
2
0
15
37.5
2
0
20
40
2
6
7
7
6
6
tDAL
tDQZ
tDQM
DQM to data high-impedance during READs
DQM to data mask during WRITEs
0
0
0
LOAD MODE REGISTER command to ACTIVE
or REFRESH command
tMRD
2
2
2
8
6
CLK
CL = 3
CL = 2
tROH3
tROH2
tBDL
3
2
1
1
3
2
1
1
3
2
1
1
Data-out to high-impedance from
PRECHARGE command
Last data-in to burst STOP command
6
6
Last data-in to new READ/WRITE command
tCDL
CKE to clock disable or power-down entry
mode
tCKED
tPED
1
1
1
1
1
1
9
9
CLK
CKE to clock enable or power-down exit
setup mode
Refresh period (4,096 rows)
AUTO REFRESH period
tREF
tRFC
tXSR
tT
64
64
64
ms
ns
66
66
67.5
67.5
0.5
70
70
5
5
Exit SELF REFRESH to ACTIVE command
Transition time
0.5
1.2
1.2
0.5
1.2
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Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
A. Target values listed with alternative values in parentheses.
B. tRFC must be less than or equal to tRC+1CLK
tXSR must be less than or equal to tRC+1CLK
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
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Special Operation for Low Power Consumption
Temperature Compensated Self Refresh
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures. Setting M4 and M3, allow the DRAM to accommodate more specific temperature regions during
SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature.
This selectable refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One Bank;bank 0. WRITE and READ commands can
still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are
disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
while CKE is low. This mode is exited by asserting CKE high.
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Figure8: Deep Power Down Mode Entry
CLK
CKE
/CS
/RAS
tRP
Deep Power Down Entry
Precharge if needed
Figure9: Deep Power Down Mode Exit
CLK
CKE
/CS
/RAS
/CAS
/WE
100 µ s
tRP
tRFC
Deep Power Down Exit
Auto Refresh
Auto Refresh
Mode Register Set
New Command
All Banks Precharge
Extended Mode Register Set
26
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Ver. A
N16D1633LPA
Enable Semiconductor Corp.
Figure10: 60Ball FBGA Configuration
6.4±0.1
1.25
3.9
0.65
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
0.3±0.05
7
6
5
4
3
2
1
1.0max
0.23±0.05
[Bottom View]
Note: All Dimensions in millimeters
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Figure11: 50Pin TSOPII Configuration
#50
#26
0°~8 °
0.17 NOM
#1
#25
1.20Max
20.95 ± 0.10
1.00 ± 0.05
0.49
1.03MAX
0.27
0.80 TYP
0.05 Min
Note: All Dimensions in millimeters
28
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Ver. A
N16D1633LPA
Enable Semiconductor Corp.
Ordering Information
N
16
D
16 33 LP
A
X - XX X
Enable Semiconductor Corp.
Temperature
Density
16 = 16Mb
C = Commercial (0°C to 70°C)
I = Industrial (-25°C to 85°C)
Product Type
Speed
D = SDRAM
60 = 6.0ns (166MHz)
75 = 7.5ns (133MHz)
10 = 10ns (100MHz)
Data I/O Width
Package
C2 = FBGA Green (60Ball)
T2 = TSOPII Green (50Pin)
16 = 16 I/O
Generation
A = 1st Generation
Power Supply
Features
33 = 3.0V or 3.3V
LP = Low Power SDRAM
Revision History
Version
Date
Change Description
A
August 1st , 2006
Initial Release
© 2005 - 2006 Enable Semiconductor Corp. All rights reserved.
Enable Semiconductor Corp. (“Enable") reserves the right to change or modify the information contained in this data sheet and the products described therein,
without prior notice. Enable does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data
sheet are provided for illustration purposes only and they vary depending upon specific applications.
Enable makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does Enable assume any liability arising out of the
application or use of any product or circuit described herein. Enable does not authorize use of its products as critical components in any application in which the
failure of the Enable product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
29
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Ver. A
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