PM25LV512A-100SC [ISSI]
Flash, 64KX8, PDSO8,;
| 型号： | PM25LV512A-100SC |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Flash, 64KX8, PDSO8, 时钟 光电二极管 内存集成电路 |
| 文件： | 总33页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pm25LV512A / 010A / 020 / 040
512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 100 MHz SPI Bus Interface
FEATURES
Page Program (up to 256 Bytes) Operation
Single Power Supply Operation
- Typical 2 ms per page program
- Low voltage range: 2.7 V - 3.6 V
Sector, Block or Chip Erase Operation
• Memory Organization
- Typical 40 ms sector, block or chip erase
- Pm25LV512A: 64K x 8 (512 Kbit)
- Pm25LV010A: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only
- Pm25LV040: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4Kbyte sectors / Two uniform
32Kbyte blocks
- 1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors (except Pm25LV512A)
Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
High Product Endurance
- Guarantee 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-contact WSON
GENERAL DESCRIPTION
The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI)
Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read
mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except
Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform
read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.
The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010.
The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of
Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of
eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte
sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an
innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional
serial EEPROM needed for storing data. This is a further cost reduction for overall system.
The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices
are offered in 8-pin SOIC and 8-contact WSON packages with operation frequency up to 100 MHz in fast read and
33 MHz in normal read mode.
Chingis Technology Corporation
1
Issue Date: June, 2006, Rev: 2.9
Pm25LV512A/010A/020/040
CONNECTION DIAGRAMS
CE#
SO
1
2
3
4
8
7
6
5
Vcc
CE#
SO
1
2
3
4
8
7
6
5
Vcc
HOLD#
SCK
SI
HOLD#
SCK
SI
WP#
GND
WP#
GND
8-Pin SOIC
8-Contact WSON
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: CE# goes low activates the devices internal circuitries for
device operation. CE# goes high deselects the devices and switches into
standby mode to reduce the power consumption. When the devices are not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
CE#
INPUT
SCK
SI
INPUT
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
INPUT
SO
OUTPUT
GND
Vcc
Device Power Supply
Write Protect: A hardware program/erase protection for all or partial of
memory array. When the WP# pin is pulled to low, whole or partial of
memory array is write protected depends on the setting of BP2, BP1 and
BP0 bits in the Status Register. When the WP# is pulled high, the devices
are not write protected.
WP#
INPUT
INPUT
Hold: Pause serial communication with the master device without resetting
the serial sequence.
HOLD#
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
PRODUCT ORDERING INFORMATION
Pm25LVxxxA -100 S
C
E
Environmental Attribute
E = RoHS compliance package
Blank = Standard package
Temperature Range
C = Commercial (-40°C to +105°C)
Package Type
S = 8-pin SOIC 150 mil (8S)
B = 8-pin SOIC 208 mil (8B)
Q = 8-contact WSON (8Q)
Operating Frequency
-100 : 33MHz normal read, 100MHz fast read
Device Number
Pm25LV512A/010A/020/040
Part Number
Operating Frequency (MHz)
Package
Temperature Range
Pm25LV512A-100SCE
Pm25LV010A-100SCE
Pm25LV020-100SCE
Pm25LV040-100SCE
Pm25LV512A-100QCE
Pm25LV010A-100QCE
Pm25LV020-100QCE
Pm25LV040-100QCE
Pm25LV040-100BCE
8S
100
150mil SOIC
Commercial
(-40oC to +105oC)
8Q
WSON
100
100
8B 208mil SOIC
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
BLOCK DIAGRAM
Control Logic
High Voltage Generator
I/O Buffers and
Data Latches
Status
Register
256 Bytes
Page Buffer
CE#
SCK
W P #
SI
Y-DECODER
SO
HOLD#
Address Latch
& Counter
Chingis Technology Corporation
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Pm25LV512A/010A/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV512A/010A/020/040 devices can be se- The difference between these two modes is the clock
rially connected onto the SPI serial bus controlled by a polarity when the SPI master is in Stand-by mode: the
SPI Master i.e. microcontroller as shown in Figure 1. serial clock remains at “0” (SCK = 0) for Mode 0 and the
The devices support either of the two SPI modes:
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.
Mode 0 (0, 0)
Mode 3 (1, 1)
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI Interface with
(0, 0) or (1, 1)
SDI
SCK
SCK SO
SI
SCK SO
SI
SCK SO
SI
SPI Master
(i.e. Microcontroller)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
CE#
WP# HOLD# CE#
WP# HOLD# CE#
WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
Mode 0 (0, 0)
Mode 3 (1, 1)
SCK
SCK
SI
MSB
SO
MSB
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
REGISTERS
The Pm25LV512A/010A/020/040 are designed to inter-
face directly with the synchronous Serial Peripheral In-
terface (SPI) of Motorola MC68HCxx series of
microcontrollers or all the SPI interface equipped sys-
tem controllers.
2. The Pm25LV010A/020/040 have an option to config-
ure the 4 Kbyte bottom sector (Sector 0) into four 1
Kbyte smaller sectors (Sector 0_0, Sector 0_1, Sec-
tor 0_2 and Sector 0_3). The finer granularity sector
size architecture allows user to update data more
efficiently. This feature allows user to eliminate the
need of addtional serial EEPROM.
The devices have two superset features can be enabled
through the specific software instructions and Configu-
ration Register:
Refer to Table 1 for Configuration Register and Table 2
for Configuration Register Bit Definition.
1. Configurable sector size: The memory array of
Pm25LV512A/010A are divided into uniform 4 Kbyte
sectors or uniform 32 Kbyte blocks (sector group -
consists of eight adjacent sectors). The memory ar-
ray of Pm25LV020/040 are divided into uniform 4
Kbyte sectors or uniform 64 Kbyte blocks (sector
group - consists of sixteen adjacent sectors).
Table 1. Configuration Register Format - Pm25LV010A/020/040
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
SP0_3
SP0_2
SP0_1
SP0_0
SCFG
Table 2. Configuration Register Bit Definition
Bit
Name
Definition
Read/Write
Sector Configuration:
"0" indicates the bottom sector is one 4 Kbyte sector (default)
"1" indicates the bottom sector is broken down to four 1 Kbyte sectors
This feature can be implemented only when BP0,BP1&BP2 of status
register were enabled to "1" which is in protection mode.
Bit 0
SCFG
R/W
1 Kbyte Sector 0_0 Protection:
Bit 1
Bit 2
Bit 3
Bit 4
SP0_0
SP0_1
SP0_2
SP0_3
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled
R/W
R/W
R/W
R/W
1 Kbyte Sector 0_1Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled
1 Kbyte Sector 0_2 Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled
1 Kbyte Sector 0_3 Protection:
"0" indicates sector protection is disabled (default)
"1" indicates sector protection is enabled
Bit 5 - 6 RES
Bit 7 RES
Reserved for future (don't care)
Reserved for future (don't use)
N/A
N/A
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)
CONFIGURATIONREGISTER(Pm25LV010A/020/040)
The BP0, BP1, BP2, and SRWD are non-volatile memory
cells that can be written by Write Status Register (WRSR)
instruction. The default value of BP0, BP1, BP2, and
SRWD bits were set as “0” at factory. Once those bits
are written as “0” or “1”, it will not be changed by devices
power-up or power-down until next WRSR instruction al-
ters its value. The Status Register can be read by Read
Status Register (RDSR) instruction for its value and sta-
tus. Refer to Table 8 for Instruction Set.
The Configuration Register is built by latchs need to be
set each time after power-up before enabling the 1 Kbyte
smaller sector size and 1 Kbyte sector write protection.
The Bit 0 - Bit 7 of Configuration Register are set as “0”s
after power-up reset. Therefore, the devices will be al-
ways set as normal mode - the bottom sector set as 4
Kbyte by default after power-up to maintain the back-
ward-compatibility.
The function of Configuration Register is described as
following:
The function of Status Register is described as following:
WIP bit: The Write In Progress (WIP) bit can be used to
detact the progress or completion of program or erase
operation. When WIP bit is “0”, the devices are ready for
write status register, program or erase operation. When
WIP bit is “1”, the devices are busy.
SCFG bit: The 1 Kbyte smaller sector mode is enabled
by writing “1” to SCFG bit, then Sector 0 is configured
as Sector 0_0, Sector 0_1, Sector 0_2 and Sector 0_3.
A Sector Erase (SECTOR_ER) instruction can be used
to erase any one of those four 1 Kbyte sectors. The
SCFG bit will be reset “0” state automatically at power
on stage. Thus, the 1 Kbyte smaller sector mode is
disabled at power on till SCFG bit was set.
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of internal write enable latch. When WEL bit
is “0”, the write enable latch is disabled, all write opera-
tions include write status register, write configuration reg-
ister, page program, sector erase, block and chip erase
operations are inhibited. When WEL bit is “1”, the write
enablelatchisenabled. Thenwriteoperationsareallowed.
The WEL bit is enabled by Write Enable (WREN) instruc-
tion. All write register, program and erase instructions
must be preceded by a WREN instruction every time.
The WEL bit can be disabled by Write Disable (WRDI)
instruction or automatically return to reset state after the
completion of a write instruction.
The SCFG bit only can be enabled to “1” when BP0,
BP1&BP2 of status register were “1” state which in pro-
tection mode. On the other word, SCFG bit will be cleared
to “0” state when BPx were “0” to disable the protection
mode.
SP0_x bits: The write protection to those four 1 Kbyte
sectors can be activated by writing “1”s to the SP0_0,
SP0_1, SP0_2 and SP0_3 bits. The 1 Kbyte sector write
protection function can only be enabled when the SCFG
is also enabled.
BP2, BP1, BP0 bits: The Block Protection (BP2
(Pm25LV040 only), BP1, BP0) bits are used to define
the portion of memory area to be protected. Refer to Table
5 and Table 6 Block Write Protection Bits Setting for
Pm25LV512A/010A/020 and Pm25LV040. When one of
the combination of BP2, BP1 and BP0 bits were set as
“1”, the relevant memory area is protected. Any program
or erase operation to that area will be prohibited.
Especially, the Chip Erase (CHIP_ER) instruction is ex-
ecuted only if all the Block Protection Bits are set as
“0”s.
The Write Configuration Register (WRCR) instruction can
be used to write “0”s or “1”s into Configuration Register.
And the Read Configuration Register (RDCR) instruc-
tion can be used to read the setting of Configuration
Register. Refer to Table 8 for Instruction Set.
STATUS REGISTER
The Status Register contains WIP and WEL status bits
to indicate the status of the devices, the Block Protec-
tion Bits (BP0, BP1 and BP2 (Pm25LV040 only)) to
define the portion of memory blocks to be write protected,
If SCFG bit was enabled to support 1KB x4 sectores on
Sector 0, Sector 0’s protection status will respect SP0_x
in Configuration Register and ignore BPx bits status
whatever protection status.
and SRWD control bits to be set for status register write
protection. Refer to Table 3 and Table 4 for Status Reg-
ister Format and Status Register Bit Definition.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)
SRWD bit: The Status Register Write Disable (SRWD) WP# is pulled low (VIL), the non-volatile bits of Status
bit is operated in conjuction with the Write Protection Register (SRWD, BP2, BP1, BP0) become read-only
(WP#) signal to provide a Hardware Protection Mode. and the WRSR instruction will be prohibited. If the SRWD
When the SRWD is set to “0”, the Status Register is not is set to “1” but WP# is pulled high (VIH), the Status
write protected. When the SRWD is set to “1” and the
Register is still changeable by WRSR instruction.
Table 3. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
0
0
BP2
BP1
BP0
WEL
WIP
Table 4. Status Register Bit Definition
Read- Non-Volatile
/Write bit
Bit
Name
Definition
Write In Progress Bit:
"0" indicates the device is ready
"1" indicates the write cycle is in progress and the device is busy
Bit 0
WIP
R
No
No
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Bit 1
WEL
R/W
Bit 2
Bit 3
Bit 4
BP0
BP1
BP2
Block Protection Bit: (See Table 5 and Table 6 for details)
"0" indicates the specific blocks are not write protected (default)
"1" indicates the specific blocks are write protected
R/W
Yes
Yes
Reserved: Always "0"s
N/A
Bits 5 - 6 N/A
Status Register Write Disable: (See Table 7 for details)
"0" indicates the Status Register is not write protected (default)
"1" indicates the Status Register is write protected
Bit 7
SRWD
R/W
Table 5. Block Write Protect Bits for Pm25LV512A/010A/020
Status Register Bits
Protected Memory Area
BP1
BP0
Pm25LV512A
Pm25LV010A
Pm25LV020
0
0
None
None
None
Upper quarter (Block 3) Upper quarter (Block 3)
018000h - 01FFFFh 030000h - 03FFFFh
Upper half (Block 2 & 3) Upper half (Block 2 & 3)
0
1
1
1
0
1
None
None
010000h - 01FFFFh
All Blocks
020000h - 03FFFFh
All Blocks
All Blocks
000000h - 00FFFFh
000000h - 01FFFFh
000000h - 03FFFFh
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
REGISTERS (CONTINUED)
Table 6. Block Write Protect Bits for Pm25LV040
Status Register Bits
Protected Memory Area
Pm25LV040
BP2
0
BP1
0
BP0
0
None
0
0
1
Upper eighth (Block 7): 070000h - 07FFFFh
Upper quarter (Block 6 and 7): 060000h - 07FFFFh
Upper half (Block 4 and 7): 040000h - 07FFFFh
0
1
0
0
1
1
1
0
0
1
0
1
All Blocks (Block 0 to 7):
000000h - 03FFFFh
1
1
0
1
1
1
PROTECTION MODE
The Pm25LV512A/010A/020/040 have two protection
modes: hardware write protection and software write pro-
tection to prevent any irrelevant operation under a pos-
sible noisy environment and protect the data integrity.
SOFTWARE WRITE PROTECTION
The Pm25LV512A/010A/020/040 also provide two soft-
ware write protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by execution of the Write
Enable (WREN) instruction. If the WEL bit is not en-
abled first, the program, erase or write register in-
struction will be ignored.
HARDWARE WRITE PROTECTION
The devices provide two hardware write protection
features:
a. When input program instruction, the input clock pulses
must be 32 clock pulses for command and address,
and a multiple of eight for 1 to 256 of data before
execution of programming. Other write instrucstion
must fit in with the number of clock pulse what the
instruction requirement before the execution. Any
incomplete instruction command sequence will be
ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or whole memory area to be write protected.
Table 7. Hardware Write Protection on Status
Register
b. Write inhibit is 2.1V, all write sequence will be ig-
nored when Vcc drop to 2.1V and lower.
SRWD
WP#
Low
Low
High
High
Status Register
Writable
0
1
0
1
c. The devices feature a Write Protection (WP#) pin to
provide a hardware write protection method for BP2,
BP1,BP0 abd SRWD in the Status Register.
(1)When the WP# is pulled low (VIL), the Status
Register is write protected if the SRWD bit is enabled
(Refer to Table 7 for Hardware Write Protection on
Status Register). Hence part or whole memory area
can be write protected depends on the setting of BP2,
BP1 and BP0 bits.
Protected
Writable
Writable
(2) When the WP# is pulled high (VIH), the Status
Register is not protected, BP2,BP1,BP0 and SRWD
can be changed.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
DEVICE OPERATION
The Pm25LV512A/010A/020/040 utilize an 8-bit instruc- Every instruction sequence starts with a one-byte in-
tion register. Refer to Table 8 Instruction Set for the de- struction code and might be followed by address bytes,
tail Instructions and Instruction Codes. All instructions, data bytes, or address bytes and data bytes depends
addresses, and data are shifted in with the most signifi- on the type of instruction. The CE# must be driven high
cant bit (MSB) first on Serial Data Input (SI). The input (VIH) after the last bit of the instruction sequence has
data on SI is latched on the rising edge of Serial Clock been shifted in.
(SCK) after the Chip Enable (CE#) is driven low (VIL).
Table 8. Instruction Set
Instruction Name
Instruction Format
Hex Code Operation
WREN
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
1010 1011
1001 1111
0000 0010
1010 0001
1111 0001
1101 0111
1101 1000
1100 0111
06h
04h
05h
01h
03h
0Bh
ABh
9Fh
02h
A1h
F1h
D7h
D8h
C7h
Write Enable
WRDI
Write Disable
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Read Manufacturer and Product ID
Read Manufacturer and Prduct ID by JEDEC ID Command
Page Program Data Bytes Into Memory
Read Configuration Register
Write Configuration Register
Sector Erase
FAST_READ
RDID
JEDEC ID READ*1
PAGE_ PROG
RDCR
WRCR
SECTOR_ER
BLOCK_ER
CHIP_ER
Block Erase
Chip Erase
Note *1 : Pm25LV512A do not support JEDEC ID READ instruction.
HOLD OPERATION
with the master device without resetting the serial
sequence. To pause, the HOLD# must be brought low
while the SCK signal is low. To resume serial communi-
cation, the HOLD# is brought high while the SCK signal
is low (SCK may still toggle during HOLD). Inputs to the
Sl will be ignored while the SO is in the high impedance
state.
The HOLD# is used in conjunction with the CE# to se-
lect the Pm25LV512A/010A/020/040. When the devices
are selected and a serial sequence is underway, HOLD#
can be used to pause the serial communication
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
Table 9. Product Identification
READ PRODUCT IDENTIFICATION OPERATION
The Read Product Identification (RDID) instruction al-
lows the user to read the manufacturer and product ID of
the devices. Refer to Table 9 Product Identification for
pFLASH™ manufacturer ID and device ID. The RDID in-
struction code is followed by three dummy bytes, each
bit being latched-in on SI during the rising edge of SCK.
Then the first manufacturer ID (9Dh) is shifted out on SO
with the MSB first, followed by the device ID and the
second manufacturer ID (7Fh), each bit been shifted out
during the falling edge of SCK. If the CE# stays low after
the last bit of second manufacturer ID is shifted out, the
manufacturer ID and device ID will be looping until the
pulled high of CE# signal.
Product Identification
Data
9Dh
7Fh
First Byte
Second Byte
Manufacturer ID
Device ID:
Pm25LV512A
7Bh
7Ch
7Dh
7Eh
Pm25LV010A
Pm25LV020
Pm25LV040
Figure 3. Read Product Identification Sequence
CE#
7
9
46
0
1
8
38 39
47
54
31
SCK
SI
INSTRUCTION
1010 1011b
3 Dummy Bytes
HIGH IMPEDANCE
SO
Manufacture ID1
Device ID
Manufacture ID2
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ PRODUCT IDENTIFICATION BY JEDEC ID
COMMAND
The JEDEC ID READ instruction allows the user to read
the manufacturer and product ID of the devices. Refer to
Table 9 Product Identification for pFLASH™ manufac-
turer ID and device ID. The second manufacturer ID (7Fh)
is shifted out on SO with the MSB first after JEDEC ID
READ command input, followed by the first manufac-
turer ID (9Dh) and the device ID, each bit been shifted
out during the falling edge of SCK.
If the CE# stays low after the last bit of device ID is
shifted out, the manufacturer ID and device ID will be loop-
ing until the pulled high of CE# signal.
Pm25LV512A do not support this JEDEC ID READ
instruction.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
CE#
0
7
8
15 16
23 24
31
SCK
SI
INSTRUCTION
1001 1111b
HIGH IMPEDANCE
SO
Manufacture ID2
Manufacture ID1
Device ID
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
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Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the chip erase, page program, write status register, and write
Write Enable Latch (WEL) bit. The WEL bit of the configuration register operations. The WEL bit will be
Pm25LV512A/010A/020/040aresetaswritedisablestate reset back to write disable state automatically after the
after power-up. The WEL bit must be write enabled be- completion of a write operation. The WREN instruction
fore any write operation includes sector, block and
is required before any above instruction is executed.
Figure 5. Write Enable Sequence
CE#
SCK
SI
INSTRUCTION = 0000 0110b
HI-Z
SO
WRITE DISABLE OPERATION
To protect the device against inadvertent writes, the Write required after the execution of a write instruction. The
Disable (WRDI) instruction resets the WEL bit and dis- WEL will be automatically reset.
ables all write instructions. The WRDI instruction is not
Figure 6. Write Disable Sequence
CE#
SCK
SI
INSTRUCTION = 0000 0100b
HI-Z
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
13
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ STATUS REGISTER OPERATION
The Read Status Register (RDSR) instruction provides instructions will be ignored except the RDSR instruction
access to the status register. During the execution of a can be used for detecting the progress or completion of
program, erase or write status register operation, all other the operations by reading the WIP bit of status register.
Figure 7. Read Status Register Sequence
CE#
1
2
3
7
9
0
5
6
8
10 11
12 13
14 15
4
SCK
SI
INSTRUCTION = 0000 0101b
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRITE STATUS REGISTER OPERATION
The Write Status Register (WRSR) instruction allows or “1”s into those non-volatile BP2, BP1, BP0 and SRWD
the user to enable or disable the block protection and bits. The erase operation for those non-volatile bits are
status register write protection features by writting “0”s not required.
Figure 8. Write Status Register Sequence
CE#
0
1
2
3
4
5
6
7
8
7
9
6
10
11
12
13
14
15
SCK
DATA IN
3
SI
2
INSTRUCTION = 0000 0001b
5
4
1
0
HIGH IMPEDANCE
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
14
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ CONFIGURATION REGISTER OPERATION
bottom Sector 0 and the write protection setting for each
individual 1 Kbyte sector (Sector 0_0 ~ Sector 0_3) within
the Sector 0.
The Read Configuration Register (RDCR) instruction pro-
vides access to the Configuration Register. This instruc-
tion can be used to verify the configuration setting of
Figure 9. Read Configuration Register Sequence
CE#
1
2
3
7
9
0
5
6
8
10 11
12 13
14 15
4
SCK
SI
INSTRUCTION = 1010 0001b
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRITE CONFIGURATION REGISTER OPERATION
Do not require WREN command before this WRCR
operation. Because Configuration Register is a data latch
architecture.
The Write Configuration Register (WRCR) instruction al-
lows user to enable or disable four smaller 1K byte
sectors and protection for each 1K byte sector by writ-
ing “0”s or “1”s into SCFG and SP0_3 ~SP0_1 in the
congiguration register. please refer table 2 for details.
Figure 10. Write Configuration Register Sequence
CE#
0
1
2
3
4
5
6
7
8
9
6
10
11
12
13
14
15
SCK
DATA IN
SI
4
0
7
5
3
2
1
INSTRUCTION = 1111 0001b
HIGH IMPEDANCE
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
15
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ DATA OPERATION
TheReadData(READ)instructionisusedtoreadmemory
data of Pm25LV512A/010A/020/040 under normal mode
running up to 33 MHz.
The first byte data D7 - D0 addressed (can be at any
location) is then shifted out onto the SO line. A single
byte data or up to whole memory array can be read out
in one READ instruction. The address is automatically
increamented to the next higher address after each byte
of data is shifted out. The read operation can be termi-
nated any time by driving the CE# high (VIH) after the
data comes out. When the highest address of the de-
vices is reached, the address counter will roll over to the
000000h address allowing the entire memory to be read
in one continuous READ instruction.
The READ instruction is activated by pulling the CE#
line of the selected device to low (VIL), and the READ
instruction code is transmitted via the Sl line followed by
three bytes address (A23 - A0) to be read. There are
total 24 address bits will be shifted in, only the AMS (most-
significant address) - A0 will be decoded and the rest of
A23 - AMS can be don’t cared. Refer to Table 10 for the
related Address Key. Upon completion, any data on the
Sl will be ignored.
Table 10. Address Key
Address
AN
Pm25LV512A
A15 - A0
Pm25LV010A
A16 - A0
Pm25LV020
A17 - A0
Pm25LV040
A18 - A0
Don't Care Bits
A23 - A16
A23 - A17
A23 - A18
A23 - A19
Figure 11. Read Data Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10 11 28 29 30 31 32 33 34 35 36 37 38 39
SCK
3-BYTE ADDRESS
...
SI
23 22 21
3
2
1
0
INSTRUCTION = 0000 0011b
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
16
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
FAST READ DATA OPERATION
addressed is shifted out on SO line, each bit being shifted
out at a maximum frequency fCT, during the falling edge
of SCK.
The Pm25LV512A/010A/020/040 also feature a Fast
Read (FAST_READ) instruction. This FAST_READ in-
struction is used to read memory data in 100 MHz clock
rate where the FAST_READ instruction proceeding.
The first byte addressed can be at any location. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached, the address counter will roll
over to the 000000h address allowing the entire memory
to be read with a single FAST_READ instruction. The
FAST_READ instruction is terminated by driving CE#
high (VIH).
The devices are first selected by driving CE# low (VIL).
The FAST_READ instruction code followed by three bytes
address (A23 - A0) and a dummy byte (8 clocks) is
trasmitted via the SI line, each bit being latched-in dur-
ing the rising edge of SCK. Then the first data byte
Figure 12. Fast Read Data Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10 11 28 29 30 31
SCK
3-BYTE ADDRESS
...
SI
23 22 21
3
2
1
0
INSTRUCTION = 0000 1011b
HIGH IMPEDANCE
SO
CE#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
DUMMY BYTE
3
7
6
5
4
2
1
0
SI
DATA OUT 1
DATA OUT 2
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
17
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
PAGE PROGRAM OPERATION
The Page Program (PAGE_PROG) instruction allow up operation, all instructions will be ignored except the
to 256 bytes data to be programmed into memory in one RDSR instruction. The progress or completion of the pro-
program operation page by page. The destination of the gram operation can be determined by reading the WIP
memory to be programmed must be outside the pro- bit in Status Register through a RDSR instruction. If WIP
tected memory area set by the Block Protection (BP2, bit = “1”, the program operation is still in progress. If WIP
BP1, BP0) bits. A PAGE_PROG instruction attemps to bit = “0”, the program operation has completed.
program into a page which is write protected will be
ignored. Before the execution of PAGE_PROG A single PAGE_PROG instruction programs 1 to 256
instruction, the Write Enable Latch (WEL) must be en- consecutive bytes within a page if it is not write protected.
abled through a Write Enable (WREN) instruction.
If more than 256 bytes data are sent to the devices, the
address counter will roll over on the same page and the
The PAGE_PROG instruction is activated, after the CE# previously latched data are discarded and the last 256
is pulled low to select the device and staying low during bytes data are kept to be programmed into the page.
the entire instruction sequence, by shifting in the The starting byte can be anywhere within the same page.
PAGE_PROG instruction code, three address bytes and When the end of the page is reached, the address will
program data (1 to 256 bytes) to be programmed via the wrap around to the beginning of the same page. If the
Sl line. Program operation will start immediately after data to be programmed are less than a full page, the
the CE# is driven high. Chip Select (CE#) must be driven data of all other bytes on the same page will remain
high after the eighth bit of last data byte has been latch unchanged.
in, otherwise the PAGE_PROG instruction will not be
executed.
A program operation can alter “1”s into “0”s, but an erase
operation is required to change “0”s back to “1”s. The
The internal control logic automatically handles the pro- same byte cannot be reprogrammed without erasing the
gramming voltages and timing. During a program
whole sector or block first.
Figure 13. Page Program Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10 11 28 29 30 31 32 33 34
SCK
256th BYTE DATA-IN
1st BYTE DATA-IN
3-BYTE ADDRESS
SI
INSTRUCTION = 0000 0010b
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
18
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
BLOCK ERASE OPERATION
ERASEOPERATION
A Block Erase (BLOCK_ER) instruction erases a 32
Kbyte block for the Pm25LV512A/010A or a 64 Kbyte
block for the Pm25LV020/040. Before the execution of
BLOCK_ER instruction, the Write Enable Latch (WEL)
must be enabled through a Write Enable (WREN) instruc-
tion. The WEL will be reset automatically after the
completion of block erase operation.
The memory array of Pm25LV512A/010A is organized
into uniform 4 Kbyte sectors or 32 Kbyte uniform blocks
(sector group - consists of eight adjacent sectors). The
memory array of Pm25LV020/040 are organized into
uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (sec-
tor group - consists of sixteen adjacent sectors). The
Pm25LV010A/020/040 of bottom sector (Sector 0) of the
devices can be configured into four 1 Kbyte smaller
sectors.
The BLOCK_ER instruction is entered, after the CE# is
pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
BLOCK_ER instruction code and three address bytes
via the SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BLOCK_ER in-
struction will not be executed. The internal control logic
automatically handles the erase voltage and timing. Re-
fer to Figure 14 for Block Erase Sequence.
Before a byte can be reprogrammed, the sector or block
which contains this byte must be erased first. In order to
erase the devices, there are three erase instructions in-
clude Sector Erase (SECTOR_ER), Block Erase
(BLOCK_ER) and Chip Erase (CHIP_ER) instructions
can be used. A sector erase operation allows to erase
any individual sector without affecting the data in others.
A block erase operation allows to erase any individual
block. And a chip erase operation allows to erase the
whole memory array of the devices. Pre-programs the
devices are not required prior to a sector erase, block
erase or chip erase operation.
CHIP ERASE OPERATION
A Chip Erase (CHIP_ER) instruction erases the whole
memory array of Pm25LV512A/010A/020/040. Before the
execution of CHIP_ER instruction, the Write Enable Latch
(WEL) must be enabled through a Write Enable (WREN)
instruction. The WEL will be reset automatically after
the completion of chip erase operation.
SECTOR ERASE OPERATION
A SECTOR_ER instruction erases a 4 Kbyte sector or a
1 Kbyte smaller sector (Sector 0_3, Sector 0_2, Sector
0_1, Sector 0_0) if the bottom Sector 0 has been config-
ured as four smaller sectors. Before the execution of
SECTOR_ER instruction, the Write Enable Latch (WEL)
must be enabled through a Write Enable (WREN) instruc-
tion. The WEL will be reset automatically after the
completion of sector erase operation.
The CHIP_ER instruction is entered, after the CE# is
pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
CHIP_ER instruction code via the SI. Erase operation
will start immediately after the CE# is pulled high, other-
wise the CHIP_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 15 for Chip Erase
Sequence.
The SECTOR_ER instruction is entered, after the CE#
is pulled low to select the device and staying low during
the entire instruction sequence, by shifting in the
SECTOR_ER instruction code and three address bytes
via the SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the SECTOR_ER in-
struction will not be executed. The internal control logic
automatically handles the erase voltage and timing. Re-
fer to Figure 13 for Sector Erase Sequence.
During a erase operation, all instruction will be ignored
except the Read Status Register (RDSR) instruction.
The progress or completion of the erase opertion can be
determined by reading the WIP bit in Status Register
through a RDSR instruction. If WIP bit = “1”, the erase
operation is still in progress. If WIP bit = “0”, the erase
operation has been completed.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
19
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
Figure 14. Sector Erase Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10 11 28 29 30
31
SCK
SI
3-BYTE ADDRESS
...
INSTRUCTION = 1101 0111b
23 22 21
3
2
1
0
HIGH IMPEDANCE
SO
Figure 15. Block Erase Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10 11 28 29 30
31
SCK
SI
3-BYTE ADDRESS
...
INSTRUCTION = 1101 1000b
23 22 21
3
2
1
0
HIGH IMPEDANCE
SO
Figure 16. Chip Erase Sequence
CE#
0
1
2
3
4
5
6
7
SCK
SI
INSTRUCTION = 1100 0111b
HIGH IMPEDANCE
SO
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
20
Pm25LV512A/010A/020/040
BLOCK/SECTOR ADDRESS
Table 11. Block/Sector Addresses of Pm25LV512A/010A
Block Size
(Kbytes)
Sector Size
(Kbytes)
Memory Density
Block No.
Sector No.
Address Range
Sector 0(1)
000000h - 000FFFh
001000h - 001FFFh
:
4
4
:
Sector 1
Block 0
32
:
Sector 7
007000h - 007FFFh
008000h - 008FFFh
009000h - 009FFFh
000000h - 006FFFh
00F000h - 00FFFFh
010000h - 017FFFh
018000h - 01FFFFh
4
512 Kbit
1 Mbit
Sector 8
4
4
:
Sector 9
Block 1
32
:
Sector 15
4
"
"
Block 2
Block 3
32
32
"
"
Note: 1. Pm25LV010A support 1KByte small sector - Sector 0 can be configured into four smaller 1 Kbyte
sectors (Sector 0_0: 000000h - 0003FFh, Sector 0_1: 000400h - 0007FFh, Sector 0_2: 000800h -
000BFFh, and Sector 0_3: 000C00h - 000FFFh).
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
21
Pm25LV512A/010A/020/040
BLOCK/SECTOR ADDRESS (CONTINUED)
Table 12. Block/Sector Addresses of Pm25LV020/040
Block Size
(Kbytes)
Sector Size
Address Range
(Kbytes)
Memory Density
Block No.
Sector No.
Sector 0 (1)
Sector 1
4
4
000000h - 000FFFh
001000h - 001FFFh
Block 0
64
:
:
4
4
4
:
Sector 15
Sector 16
Sector 17
00F000h - 00FFFFh
010000h - 010FFFh
011000h - 011FFFh
:
2 Mbit
Block 1
Block 2
64
64
:
:
4
"
"
"
"
"
"
4 Mbit
Sector 31
01F000h - 01FFFFh
020000h - 02FFFFh
"
"
"
"
"
"
Block 3
Block 4
Block 5
64
64
64
030000h - 03FFFFh
040000h - 04FFFFh
050000h - 05FFFFh
Block 6
Block 7
64
64
060000h - 06FFFFh
070000h - 07FFFFh
Note: 1. Sector 0 can be configured into four smaller 1 Kbyte sectors (Sector 0_0: 000000h - 0003FFh, Sector
0_1: 000400h - 0007FFh, Sector 0_2: 000800h - 000BFFh, and Sector 0_3: 000C00h - 000FFFh).
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
22
Pm25LV512A/010A/020/040
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
Storage Temperature
-65oC to +125oC
-65oC to +125oC
Standard Package
Lead-free Package
240oC 3 Seconds
260oC 3 Seconds
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +6.0 V
Surface Mount Lead Soldering Temperature
(2)
Input Voltage with Respect to Ground on All Pins
All Output Voltage with Respect to Ground
(2)
VCC
Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only. The functional operation of the device or any other
conditions under those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condition for extended periods may affected
device reliability.
2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning
period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns.
Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period,
input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number
Pm25LV512A/010A/020/040
-40oC to +105oC
Operating Temperature
Vcc Power Supply
2.7 V - 3.6 V
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
23
Pm25LV512A/010A/020/040
DC CHARACTERISTICS
Applicable over recommended operating range from:
TAC = -40°C to +105°C, VCC = 2.7 V to 3.6 V (unless otherwise noted).
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC = 3.6V at 33 MHz, SO = Open
ICC1
ICC2
ISB1
ISB2
ILI
Vcc Active Read Current
Vcc Program/Erase Current
Vcc Standby Current CMOS
Vcc Standby Current TTL
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
15
15
mA
mA
VCC = 3.6V at 33 MHz, SO = Open
VCC = 3.6V, CE# = VCC
30
50
µ
A
VCC = 3.6V, CE# = VIH to VCC
VIN = 0V to VCC
3
mA
1
1
µA
µA
V
VIN = 0V to VCC, TAC = 0oC to 105oC
ILO
VIL
-0.5
0.8
VIH
VOL
VOH
Input HIgh Voltage
0.7VCC
VCC + 0.3
0.45
V
Output Low Voltage
IOL = 2.1 mA
V
2.7V < VCC < 3.6V
Output High Voltage
IOH = -100 A
VCC - 0.2
V
µ
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
24
Pm25LV512A/010A/020/040
AC CHARACTERISTICS
Applicable over recommended operating range from TA = -40°C to +105°C, VCC = 2.7 V to 3.6 V
CL = 1TTL Gate and 10 pF (unless otherwise noted).
Symbol
fCT
Parameter
Min
0
Typ
Max
100
33
8
Units
MHz
MHz
ns
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
fC
0
tRI
tFI
Input Fall Time
8
ns
tCKH
tCKL
tCEH
tCS
tCH
tDS
tDH
tHS
tHD
tV
SCK High Time
4
4
ns
SCK Low Time
ns
CE# High Time
25
10
5
ns
CE# Setup Time
ns
CE# Hold Time
ns
Data In Setup Time
Data in Hold Time
Hold Setup Time
2
ns
2
ns
15
15
ns
Hold Time
ns
Output Valid
8
ns
tOH
tLZ
Output Hold Time Normal Mode
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
0
ns
ns
200
200
100
100
5
tHZ
ns
tDIS
tEC
tPP
ns
ms
ms
ms
µs
40
2
Secter/Block/Chip Erase Time
Page Program Time
tW
Write Status Register Time
40
100
tVCS
VCC Set-up Time
50
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
25
Pm25LV512A/010A/020/040
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING(1)
tCEH
VIH
CE#
VIL
tCS
tCH
VIH
tCKL
SCK
SI
tCKH
VIL
tDS
tDH
VIH
VIL
VALID IN
tOH
tDIS
tV
VOH
HI-Z
HI-Z
SO
VOL
Note: 1. For SPI Mode 0 (0,0)
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
26
Pm25LV512A/010A/020/040
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
CE#
tH D
tH D
SCK
tH S
tH S
HOLD#
tH Z
SO
tLZ
PIN CAPACITANCE ( f = 1 MHz, T = 25°C )
Typ
4
Max
6
Units
pF
Conditions
VIN = 0 V
CIN
COUT
8
12
pF
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
3.3 V
0.8Vcc
AC
Input
1.5 V
Measurement
Level
1.8 K
0.2Vcc
OUTPUT PIN
Note: 1. Input Pulse Voltage : 0.2Vcc to 0.8Vcc.
2. Input Timing Reference Voltages :
0.3Vcc to 0.7Vcc.
1.3 K
10 pF
3. Output Timing Reference Voltage : Vcc/2.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
27
Pm25LV512A/010A/020/040
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be Register, Program or Erase instructions should be sent
selected (CE# must follow the voltage applied on Vcc) until the later of:
until Vcc reaches the correct value:
- Vcc(min) at Power-up, and then for a further delay of
tVCE
- tPUW after Vcc passed the VWI threshold
- tVCE after Vcc passed the Vcc(min) level
- Vss at Power-down
At Power-up, the device is in the following state:
Usually a simple pull-up resistor on CE# can be used to - The device is in the Standby mode
insure safe and proper Power-up and Power-down.
- The Write Enable Latch (WEL) bit is reset
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is At Power-down, when Vcc drops from the operating
included. The logic inside the device is held reset while voltage, to below the Vwi, all write operations are dis-
Vcc is less than the POR threshold value (Vwi) during abled and the device does not respond to any write
power up, the device does not respond to any instruction instruction.
until a time delay of tPUW has elapsed after the moment
that Vcc rised above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by
this time, Vcc is still below Vcc(min). No Write Status
Power-up Timing
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
Read Access Allowed
Device fully accessible
V (write inhibit)
tPUW
Time
Symbol
Parameter
Vcc(min) to CE# Low
Min.
10
Max.
Unit
*1
tVCE
us
ms
V
*1
tPUW
Power-Up time delay to Write instruction
Write Inhibit Voltage
1
10
*1
VWI
2.1
2.3
Note : *1. These parameters are characterized only.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
28
Pm25LV512A/010A/020/040
PROGRAM/ERASE PERFORMANCE
Parameter
Sector Erase Time
Block Erase Time
Chip Erase Time
Unit
ms
Typ
40
Max
100
100
100
Remarks
From writing erase command to erase completion
From writing erase command to erase completion
From writing erase command to erase completion
ms
40
ms
40
From writing program command to program
completion
Page Programming Time
ms
2
5
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Min
200,000
20
Typ
Unit
Test Method
Endurance
Cycles JEDEC Standard A117
Years JEDEC Standard A103
Volts JEDEC Standard A114
Volts JEDEC Standard A115
Volts JEDEC Standard C101-A
Data Retention
ESD - Human Body Model
ESD - Machine Model
ESD - Charged Device Model
Latch-Up
2,000
200
1,000
mA
JEDEC Standard 78
100 + ICC1
Note: These parameters are characterized and are not 100% tested.
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
29
Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION
8S
8-Pin JEDEC 150mil Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Top View
Side View
0.51
0.33
5.00
4.80
1.27 BSC
4.00
3.80
0.25
0.10
6.20
5.80
1.75
1.35
End View
45º
0.25
0.19
1.27
0.40
`
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
30
Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION
8B
8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Top View
Side View
0.48
0.35
5.38
5.18
1.27 BSC
0.25
0.05
5.38
5.18
8.10
7.70
2.16
1.75
End View
5.33
5.13
0.25
0.19
5.38
5.18
0.80
0.50
`
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
31
Pm25LV512A/010A/020/040
PACKAGE TYPE INFORMATION (CONTINUED)
8Q
8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)
Top View
Side View
5.00
BSC
6.00
BSC
0.25
0.19
0.80
0.70
Pin 1
Bottom View
1.27
BSC
0.48
0.35
0.75
0.50
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
32
Pm25LV512A/010A/020/040
REVISION HISTORY
Date
Revision No. Description of Changes
Page No.
January, 2004
March, 2004
0.3
0.4
Advanced Product Specification
All
Extend The Range of Operation Temperature
All
Correct part no for WSON package
Register status setting
3
August, 2004
0.5
6,7,8
Correct part no
Register setting for small sector feathure
All
page 7
October, 2004
January, 2005
0.6
0.7
Preliminary version release
1. Support 208mil SOIC package
2. Correct read timing for D0 latch by HOST
3. Remove Turbo mode
January, 2005
0.8
All
Support 33MHz
Removed bask side metal of WSON
Standby current
1,3,15,23,24,
30
February, 2005
May, 2005
0.9
1.0
JEDEC ID READ instruction
Correct the smaller sector (1KB) feature
6,7,10,12
Description update for the operation of Configuration
Register
June, 2005
July, 2005
1.1
2.0
8,9,15,16
All
Support 75MHz for Fast Read Mode
1. Update fast read speed to 100MHz.
2. Sectore/Block archeticture description.
3. Ordering information - remove non-pbfree parts.
4. Highligh no require WREN before WRCR command.
5. AC measurement conditions.
July, 2005
2.1
1,3,16,28
1. Change AC paramaters for 100MHz spec.
Tv 8ns with 10pF Loading, Data In Hold/Setup tiime
2ns(min), Clock high/low time 4ns(min)
TRI, TFI, 8ns(max), TDIS 10ns(max)
2. Support Commercial Grade to -40~+85degreeC
3. Partno chage for Pm25LV010 to Pm25LV010A.
November, 2005
February, 2006
2.3
2.4
3, 24,25
1,9,28
1. Update endurance to 200K cycle.
2. Update write inhibit spec. to 2.1V .
3. Update ESD CDM spec 1000V.
1.Change Logo and company name
2.Modified test condition for DC
All
24
March, 2006
March, 2006
2.5
2.6
Extend the operated temperature to +105degreeC
3,23,24,25
1. Update Pm25LV512A in the datasheet
2. Correct tCH definition
3. Power-up timing difinition
All
25,26
28
April, 2006
2.7
May, 2006
June, 2006
2.8
2.9
Correct the statement of hardware write protection
To declare 'E' pacakge for RoHS compliance
9
3
Chingis Technology Corporation
Issue Date: June, 2006, Rev: 2.9
33
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