IXDD415 [IXYS]

Dual 15 Ampere Low-Side Ultrafast MOSFET Driver; 双15安培低端超快MOSFET驱动器


型号：	IXDD415
厂家：	IXYS CORPORATION
描述：	Dual 15 Ampere Low-Side Ultrafast MOSFET Driver 双15安培低端超快MOSFET驱动器驱动器
文件：	总8页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IXDD415SI

Dual 15 Ampere Low-Side Ultrafast MOSFET Driver

General Description

Features

• Built using the advantages and compatibility

of CMOS and IXYS HDMOS^TMprocesses

• Latch-UpProtected

• High Peak Output Current: Dual 15A Peak

• Wide Operating Range: 8V to 30V

• Rise And Fall Times of <3ns

• Minimum Pulse Width Of 6ns

• Ability to Disable Output under Faults

• High Capacitive Load

Drive Capability: 4nF in <5ns

• Matched Rise And Fall Times

• 32ns Input To Output Delay Time

• LowOutputImpedance

The IXDD415 is a dual CMOS high speed high current gate

driver specifically designed to drive MOSFETs in Class D and E

HF RF applications, as well as other applications requiring

ultrafast rise and fall times or short minimum pulse widths.

Each output of the IXDD415 can source and sink 15A of peak

current while producing voltage rise and fall times of less than

3ns. The outputs of the IXDD415 may be paralleled, producing a

single output of up to 30A with comparable rise and fall times.

The input of the driver is compatible with TTL or CMOS and is

fully immune to latch up over the entire operating range.

Designed with small internal delays, cross conduction/current

shoot-throughisvirtuallyeliminatedintheIXDD415. Itsfeatures

and wide safety margin in operating voltage and power make

theIXDD415unmatchedinperformanceandvalue.

• LowSupplyCurrent

The IXDD415 has two enable inputs, ENA and ENB. These

enable inputs can be used to independently disable either of the

outputs, OUTA or OUTB, for added flexibility. Additionally, the

IXDD415 incorporates a unique ability to disable the output

under fault conditions. When a logical low is forced into the

Enable inputs, both final output stage MOSFETs (NMOS and

PMOS) are turned off. As a result, the output of the IXDD415

enters a tristate mode and achieves a Soft Turn-Off of the

MOSFET when a short circuit is detected. This helps prevent

damage that could occur to the MOSFET if it were to be

switchedoffabruptlyduetoadv/dtover-voltagetransient.

Applications

• DrivingRFMOSFETs

• Class D or E Switching Amplifier Drivers

• Multi MHz Switch Mode Power Supplies (SMPS)

• PulseGenerators

• AcousticTransducerDrivers

• PulsedLaserDiodeDrivers

• DCtoDCConverters

• PulseTransformerDriver

The IXDD415 is available in a 28 pin SO package (IXDD415SI),

incorporatingDEI'spatented⁽¹⁾RFlayouttechniquestominimize

stray lead inductances for optimum switching performance.

(1)

DEI U.S. Patent #4,891,686

Figure 1 - Functional Diagram

Vcc (1, 2)

Vcc (3, 4)

INA (7)

ENA (6)

OUTA (22, 23, 24)

200k

GND (25, 26)

Vcc (11, 12)

GND (27, 28)

Vcc (13, 14)

INB (8)

ENB (9)

OUTB (19, 20, 21)

GND (17, 18)

200k

GND (15, 16)

First Release

IXDD415SI

Absolute Maximum Ratings (Note 1)

Operating Ratings

Parameter

Value

Parameter

Value

Supply Voltage

All Other Pins

30V

-0.3V to V

Maximum Junction Temperature

150 C

+ 0.3V

Operating Temperature Range

-40 C to 85 C

Power Dissipation

Thermal Impedance (Junction To Case)

28 Pin SOIC (SI) (θ_JC)

T_AMBIENT≤25 C

0.75 C/W

12W

_CASE≤25 C

Derating Factors (to Ambient)

28-Pin SOIC

0.1W/ C

Storage Temperature

-65 C to 150 C

Soldering Lead Temperature

(10 seconds maximum)

300 C

Electrical Characteristics

Unless otherwise noted, T_A= 25 ^oC, 4.5V ≤ V_CC≤ 25V .

All voltage measurements with respect to GND. IXDD415 configured as described in Test Conditions.

S ym bol

V_IH

Param eter

Test Conditions

M in

Typ

M ax

U nits

H igh input voltage

Low input voltage

Input voltage range

Input current

3.5

V_IL

0.8

V_IN

-5

V_CC+ 0.3

I_IN

-10

0V ≤ V_IN≤ V_{C C}

µA

V_{O H}

V_{O L}

R _{O H}

H igh output voltage

Low output voltage

V_CC- 0.025

Ω

0.025

1.2

O utput resistance

@ O utput H igh

O utput resistance

@ O utput Low

I_{O UT}= 10m A, V_CC= 15V

V_CC= 15V, each output

0.8

R _{O L}

I_PEAK

I_DC

1.2

Ω

Peak output current

C ontinuous output

current

V_EN

Enable voltage range

-0.3

Vcc + 0.3

V_ENH

V_ENL

f_{M AX}

H igh En input voltage

Low En input voltage

M axim um frequency

2/3 Vcc

1/3 Vcc

C _L=1.0nF Vcc=15V, m ax CW frequency

lim ited by package pow er dissipation

C _L=1nF Vcc=15V V_{O H}=2V to 12V

C _L=4nF Vcc=15V V_{O H}=2V to 12V

C _L=1nF Vcc=15V V_{O H}=2V to 12V

C _L=4nF Vcc=15V V_{O H}=2V to 12V

C _L=4nF Vcc=15V

M H z

(1)

t_R

R ise tim e

2.5

4.5

2.0

3.5

(1)

t_F

Fall tim e

t_{O NDLY}

t_{O FFDLY}

P_{W min}

t_{ENO L}

t_{ENO H}

t_DOLD

t_DOHD

O n-tim e propagation

(1)

delay

O ff-tim e propagation

C _L=4nF Vcc=15V

(1)

delay

M inim um pulse width

FW H M C _L=1nF

+3V to +3V C _L=1nF

Vcc=15V

5.0

7.0

Enable to output low

delay tim e

Enable to output high

delay tim e

D isable to output low

D isable delay tim e

D isable to output high

D isable delay tim e

Power supply voltage

170

Vcc=15V

V_CC

I_CC

Power supply current

V_IN= 3.5V

V_IN= 0V

V_IN= + V_CC

m A

µA

⁽¹⁾Refer to Figures 2a and 2b

Specifications Subject To Change Without Notice

IXDD415SI

Pin Configurations And Package Outline

NOTE: Bottom-side heat sinking metalization is connected to ground

Pin Description

P IN #

S Y M B O L

F U N C T IO N

D E S C R IP T IO N

P ositive pow er-supply voltage input. T his pin provides pow er

to the entire chip. T he range for this voltage is from 8V to

30V .

1-4

11-14

V C C

S up ply V oltag e

IN A

Input

Input signal-T T L or C M O S com patible.

T he system enable pin. T his pin, w hen driven low , disables

the chip, forcing high im pedance state to the output.

D river O utput. F or application purposes, this pin is

connected to the G ate of a M O S F E T . In som e applications,

a low -im pedance series resistor m ay be required betw een

this output and the M O S F E T G ate.

E N A

E na ble

O utput

22-24

O U T A

IN B

Input

Input signal-T T L or C M O S com patible.

T he system enable pin. T his pin, w hen driven low , disables

the chip, forcing high im pedance state to the output.

D river O utput. F or application purposes, this pin is

connected to the G ate of a M O S F E T . In som e applications,

a low -im pedance series resistor m ay be required betw een

this output and the M O S F E T G ate.

T he system ground pins. Internally connected to all circuitry,

these pins provide ground reference for the entire chip. All of

these pins should be connected to

ground plane for optim um perform ance.

E N B

E na ble

19-21

O U T B

G N D

O utput

G round

5,10

15-18

25-28

a low noise analog

Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent

damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not

guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures

when handling and assembling this component.

Ordering Information

Part Number Package Type Temp. Range Grade

IXDD415SI

28-Pin SOIC

Industrial

-40°C to +85°C

IXDD415SI

Typical Performance Characteristics

Figure 2a - Characteristics Test Diagram

Figure 2b - Timing Diagram

90%

INPUT

2.5V

10%

PW^MIN

OFFDLY

ONDLY

VIN

Vcc

90%

OUTPUT

10%

Rise Time vs. Load Capacitance

Fig. 3

Fig. 4

Fall Time vs. Load Capacitance

V_CC= 15V, V_OH= 12V To 2V

V = 15V, V_OH= 2V To 12V

Load Capacitance (pF)

Fig. 5

Supply Current vs. Frequency

Vcc=15V

Fig. 6

Supply Current vs. Load Capacitance

Vcc=15V

4000

3000

2000

1000

4 nF

3000

2000

1000

2 nF

1 nF

25 MHz

C = 0

20 MHz

15 MHz

10 MHz

5 MHz

1 MHz

Frequency (MHz)

Load Capacitance (pF)

IXDD415SI

Fig. 7

Propagation Delay vs. Supply Voltage

C=4nF V =5V@100kHz

Fig. 8

Propagation Delay vs. Input Voltage

C=4nF V_CC=15V

t_ONDLY

t_OFFDLY

Supply Voltage (V)

Input Voltage (V)

Fig. 9

Propagation Delay vs. Junction Temperature

C=4nF, V =15V

t_ONDLY

t_OFFDLY

-40

-20

100

120

Temperature (°C)

Typical Output Waveforms

Unless otherwise noted, all waveforms are taken driving a 1nF load, 1MHz repetition frequency, V_CC=15V, Case Temperature = 25°C

Figure 10

2.2ns Rise Time

Figure 11

<6ns Minimum Pulse Width

IXDD415SI

Figure 12 500KHz CW Repetition Frequency

Figure 13 50MHz Burst Repetition Frequency

Figure 14 - High Frequency Gate Drive Circuit

IXDD415SI

APPLICATIONS INFORMATION

High Frequency Gate Drive Circuit

returning current that need to be considered: Path #1 is

betweentheIXDD415anditsload. Path#2isbetweenthe

IXDD415 and its power supply. Path #3 is between the

IXDD415andwhateverlogicisdrivingit. Allthreeofthese

paths should be as low in resistance and inductance as

possible, and thus as short as practical.

The circuit diagram in figure 14 is a circuit diagram for a

veryhighswitchingspeed, highfrequencygatedriver

circuit using the IXDD415SI. This is the circuit used in

theEVDD415EvaluationBoard,andiscapableofdriving

a MOSFET at up to the maximum operating limits of the

IXDD415. Thecircuit'sveryhighswitchingspeedand

high frequency operation dictates the close attention to

several important issues with respect to circuit design.

The three key elements are circuit loop inductance, Vcc

bypassingandgrounding.

Output Lead Inductance

Ofequalimportancetosupplybypassingandgroundingare

issues related to the output lead inductance. Every effort

should be made to keep the leads between the driver and

its load as short and wide as possible, and treated as

coplanar transmission lines.

Circuit Loop Inductance

Referring to Figure 14, the Vcc to Vcc ground current

path defines the loop which will generate the inductive

term. This loop must be kept as short as possible. The

output leads (pins 24, 23, 22, 21, 20, and 19) must be

no further than 0.375 inches (9.5mm) from the gate of

the MOSFET. Furthermore the output ground leads (pins

25, 26, 27 and 28 on one end of the IC and pins 15, 16,

17, and 18 on the other end of the IC) must provide a

balancedsymmetriccoplanargroundreturnforoptimum

Inconfigurationswheretheoptimumconfigurationofcircuit

layout and bypassing cannot be used, a series resistance

ofafewOhmsinthegateleadmaybenecessarytoprevent

ringing.

Heat Sinking

For high power operation, the bottom side metalized heat

sink pad should be epoxied to the circuit board ground

plane, or attached to an appropriate heat sink, using

thermallyconductiveepoxy.Theheatsinktabisconnected

operation.

VccBypassing

toground.

In order for the circuit to turn the MOSFET on properly,

the IXDD415 must be able to draw up to 15A of current

per output channel from the Vcc power supply in 2-6ns

(depending upon the input capacitance of the MOSFET

being driven). This means that there must be very low

impedancebetweenthedriverandthepowersupply.

The most common method of achieving this low

impedance is to bypass the power supply at the driver

with a capacitance value that is at least two orders of

magnitude larger than the load capacitance. Usually,

this is achieved by placing two or three different types of

bypassing capacitors, with complementary impedance

curves, very close to the driver itself. (These capacitors

should be carefully selected, low inductance, low

resistance,high-pulsecurrent-servicecapacitors). Care

should be taken to keep the lengths of the leads

between these bypass capacitors and the IXDD415 to an

absoluteminimum.

Figure 15: IXDD415SI Bottom Side

Heat Sinking Metalization

Thebypassingshouldbecomprisedofseveralvaluesof

chip capacitors symmetrically placed on ether side of

the IC. Recommended values are .01uF, .47uF chips

and at least two 4.7uF tantalums.

Grounding

In order for the design to turn the load off properly, the

IXDD415 must be able to drain this 15A of current into an

adequate grounding system. There are three paths for

IXDD415SI

TTL to High Voltage CMOS Level Translation

The enable (EN) input to the IXDD415 is a high voltage

CMOS logic level input where the EN input threshold is ½ V_CC,

and may not be compatible with 5V CMOS or TTL input levels.

The IXDD415 EN input was intentionally designed for

enhanced noise immunity with the high voltage CMOS logic

levels. In a typical gate driver application, V_CC=15V and the

EN input threshold at 7.5V, a 5V CMOS logical high input

applied to this typical IXDD415 application’s EN input will be

misinterpreted as a logical low, and may cause undesirable

or unexpected results. The note below is for optional

adaptation of TTL or 5V CMOS levels.

Figure 16 - TTL to High Voltage CMOS Level Translator

(From Gate Driver

Power Supply)

10K

High Voltage

(From Logic

CMOS

3.3K

Output

Power Supply)

2N3904

(To IXDD415

EN Input)

3.3K R2

The circuit in Figure 16 alleviates this potential logic level

misinterpretation by translating a TTL or 5V CMOS logic input

to high voltage CMOS logic levels needed by the IXDD415 EN

input. From the figure, V_CCis the gate driver power supply,

typically set between 8V to 20V, and V_DDis the logic power

supply, typically between 3.3V to 5.5V. Resistors R1 and R2

form a voltage divider network so that the Q1 base is posi-

tioned at the midpoint of the expected TTL logic transition

levels.

TTL

Input)

A TTL or 5V CMOS logic low, V_TTLLOW=~<0.8V, input applied to

the Q1 emitter will drive it on. This causes the level translator

output, the Q1 collector output to settle to V_CESATQ1

V_TTLLOW=<~2V, which is sufficiently low to be correctly

interpreted as a high voltage CMOS logic low (<1/3V_CC=5V for

V_CC=15V given in the IXDD415 data sheet.)

A TTL high, V_TTLHIGH=>~2.4V, or a 5V CMOS high,

V_5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in

Figure 16 will cause Q1 to be biased off. This results in Q1

collector being pulled up by R3 to V_CC=15V, and provides a

high voltage CMOS logic high output. The high voltage CMOS

logical EN output applied to the IXDD415 EN input will enable

it, allowing the gate driver to fully function as a 15 Ampere

output driver.

The total component cost of the circuit in Figure 16 is less

than $0.10 if purchased in quantities >1K pieces. It is

recommended that the physical placement of the level

translator circuit be placed close to the source of the TTL or

CMOS logic circuits to maximize noise rejection.

Directed Energy, Inc.

An IXYS Company

2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526

Tel: 970-493-1901; Fax: 970-493-1903

e-mail: deiinfo@directedenergy.com

www.directedenergy.com

IXYS Corporation

3540 Bassett St; Santa Clara, CA 95054

Tel: 408-982-0700; Fax: 408-496-0670

e-mail: sales@ixys.net

www.ixys.com

IXYS Semiconductor GmbH

Edisonstrasse15 ; D-68623; Lampertheim

Tel: +49-6206-503-0; Fax: +49-6206-503627

e-mail: marcom@ixys.de

Doc #9200-0233 R2

IXDD415 [IXYS]

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